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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger Subject: [PULL 11/23] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Date: Thu, 23 May 2024 17:00:24 +0200 Message-ID: <20240523150036.1050011-12-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476548092100001 From: Zhao Liu CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared by Intel and AMD CPUs. But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU (in CPUID[0x80000026]) have the different definitions with different enumeration values. Though CPUID[0x80000026] hasn't been implemented in QEMU, to avoid possible misunderstanding, split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] and introduce CPUID[0x1F]-specific topology types. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Babu Moger Message-ID: <20240424154929.1487382-11-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 13 +++++++++---- target/i386/cpu.c | 14 +++++++------- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9e7b9e918e9..8c83900202d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1016,10 +1016,15 @@ uint64_t x86_cpu_get_supported_feature_word(Feature= Word w, #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ =20 /* CPUID[0xB].ECX level types */ -#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) -#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) -#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) -#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) +#define CPUID_B_ECX_TOPO_LEVEL_INVALID 0 +#define CPUID_B_ECX_TOPO_LEVEL_SMT 1 +#define CPUID_B_ECX_TOPO_LEVEL_CORE 2 + +/* COUID[0x1F].ECX level types */ +#define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID +#define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT +#define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE +#define CPUID_1F_ECX_TOPO_LEVEL_DIE 5 =20 /* MSR Feature Bits */ #define MSR_ARCH_CAP_RDCL_NO (1U << 0) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8419055006c..d350eb8a736 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6418,17 +6418,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, case 0: *eax =3D apicid_core_offset(&topo_info); *ebx =3D topo_info.threads_per_core; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + *ecx |=3D CPUID_B_ECX_TOPO_LEVEL_SMT << 8; break; case 1: *eax =3D apicid_pkg_offset(&topo_info); *ebx =3D threads_per_pkg; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + *ecx |=3D CPUID_B_ECX_TOPO_LEVEL_CORE << 8; break; default: *eax =3D 0; *ebx =3D 0; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + *ecx |=3D CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; } =20 assert(!(*eax & ~0x1f)); @@ -6453,22 +6453,22 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, case 0: *eax =3D apicid_core_offset(&topo_info); *ebx =3D topo_info.threads_per_core; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_SMT << 8; break; case 1: *eax =3D apicid_die_offset(&topo_info); *ebx =3D topo_info.cores_per_die * topo_info.threads_per_core; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_CORE << 8; break; case 2: *eax =3D apicid_pkg_offset(&topo_info); *ebx =3D threads_per_pkg; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_DIE << 8; break; default: *eax =3D 0; *ebx =3D 0; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_INVALID << 8; } assert(!(*eax & ~0x1f)); *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ --=20 2.45.1