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Thu, 23 May 2024 08:00:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH4rX1SNUxqi/sea3OI+oD5NvncjNQHTmyAwiOyekA4TG0W6l9HONHCp7am9z4InagSjIuKeg== X-Received: by 2002:a19:385c:0:b0:51e:25d2:453f with SMTP id 2adb3069b0e04-526c15eb8admr2943898e87.68.1716476439095; Thu, 23 May 2024 08:00:39 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PULL 01/23] target/i386: generate simpler code for ROL/ROR with immediate count Date: Thu, 23 May 2024 17:00:14 +0200 Message-ID: <20240523150036.1050011-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476503808100001 Content-Type: text/plain; charset="utf-8" gen_rot_carry and gen_rot_overflow are meant to be called with count =3D=3D= NULL if the count cannot be zero. However this is not done in gen_ROL and gen_R= OR, and writing everywhere "can_be_zero ? count : NULL" is burdensome and less readable. Just pass can_be_zero as a separate argument. gen_RCL and gen_RCR use a conditional branch to skip the computation if count is zero, so they can pass false unconditionally to gen_rot_overflo= w. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson Message-ID: <20240522123914.608516-1-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/tcg/emit.c.inc | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 2dee33dd487..33cb59e54b8 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -2901,14 +2901,15 @@ static bool gen_eflags_adcox(DisasContext *s, X86De= codedInsn *decode, bool want_ return got_cf; } =20 -static void gen_rot_overflow(X86DecodedInsn *decode, TCGv result, TCGv old= , TCGv count) +static void gen_rot_overflow(X86DecodedInsn *decode, TCGv result, TCGv old, + bool can_be_zero, TCGv count) { MemOp ot =3D decode->op[0].ot; - TCGv temp =3D count ? tcg_temp_new() : decode->cc_src2; + TCGv temp =3D can_be_zero ? tcg_temp_new() : decode->cc_src2; =20 tcg_gen_xor_tl(temp, old, result); tcg_gen_extract_tl(temp, temp, (8 << ot) - 1, 1); - if (count) { + if (can_be_zero) { tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_src2, count, tcg_consta= nt_tl(0), decode->cc_src2, temp); } @@ -3000,7 +3001,7 @@ static void gen_RCL(DisasContext *s, CPUX86State *env= , X86DecodedInsn *decode) /* Compute result and outgoing overflow */ tcg_gen_mov_tl(decode->cc_src2, s->T0); tcg_gen_or_tl(s->T0, low, high); - gen_rot_overflow(decode, s->T0, decode->cc_src2, NULL); + gen_rot_overflow(decode, s->T0, decode->cc_src2, false, NULL); =20 if (zero_label) { gen_set_label(zero_label); @@ -3053,7 +3054,7 @@ static void gen_RCR(DisasContext *s, CPUX86State *env= , X86DecodedInsn *decode) /* Compute result and outgoing overflow */ tcg_gen_mov_tl(decode->cc_src2, s->T0); tcg_gen_or_tl(s->T0, low, high); - gen_rot_overflow(decode, s->T0, decode->cc_src2, NULL); + gen_rot_overflow(decode, s->T0, decode->cc_src2, false, NULL); =20 if (zero_label) { gen_set_label(zero_label); @@ -3129,9 +3130,10 @@ static TCGv_i32 gen_rot_replicate(MemOp ot, TCGv in) } } =20 -static void gen_rot_carry(X86DecodedInsn *decode, TCGv result, TCGv count,= int bit) +static void gen_rot_carry(X86DecodedInsn *decode, TCGv result, + bool can_be_zero, TCGv count, int bit) { - if (count =3D=3D NULL) { + if (!can_be_zero) { tcg_gen_extract_tl(decode->cc_dst, result, bit, 1); } else { TCGv temp =3D tcg_temp_new(); @@ -3165,8 +3167,8 @@ static void gen_ROL(DisasContext *s, CPUX86State *env= , X86DecodedInsn *decode) } else { tcg_gen_rotl_tl(s->T0, s->T0, count); } - gen_rot_carry(decode, s->T0, count, 0); - gen_rot_overflow(decode, s->T0, old, count); + gen_rot_carry(decode, s->T0, can_be_zero, count, 0); + gen_rot_overflow(decode, s->T0, old, can_be_zero, count); } =20 static void gen_ROR(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) @@ -3190,12 +3192,12 @@ static void gen_ROR(DisasContext *s, CPUX86State *e= nv, X86DecodedInsn *decode) tcg_gen_rotr_i32(temp32, temp32, count32); /* Zero extend to facilitate later optimization. */ tcg_gen_extu_i32_tl(s->T0, temp32); - gen_rot_carry(decode, s->T0, count, 31); + gen_rot_carry(decode, s->T0, can_be_zero, count, 31); } else { tcg_gen_rotr_tl(s->T0, s->T0, count); - gen_rot_carry(decode, s->T0, count, TARGET_LONG_BITS - 1); + gen_rot_carry(decode, s->T0, can_be_zero, count, TARGET_LONG_BITS = - 1); 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Thu, 23 May 2024 08:00:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHWQ0oj7QicNW+oP0A0wU0SLQE9fa7b8SN+jww+F0zv6DF6SPaCOrJu9nVkoPq/UmiASPKLsA== X-Received: by 2002:a17:906:a0c9:b0:a59:9d4c:eb09 with SMTP id a640c23a62f3a-a6228069286mr362105866b.27.1716476441660; Thu, 23 May 2024 08:00:41 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PULL 02/23] target/i386: clean up AAM/AAD Date: Thu, 23 May 2024 17:00:15 +0200 Message-ID: <20240523150036.1050011-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476515904100005 Content-Type: text/plain; charset="utf-8" The 32-bit AAM/AAD opcodes are using helpers that read and write flags and env->regs[R_EAX]. Clean them up so that the table correctly includes AX as a 16-bit input and output. No real reason to do it to be honest, but they are nice one-output helpers and it removes the masking of env->regs[R_EAX] that generic load/writeback code already does. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson Message-ID: <20240522123912.608497-1-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/helper.h | 4 ++-- target/i386/tcg/int_helper.c | 19 ++++++++----------- target/i386/tcg/decode-new.c.inc | 4 ++-- target/i386/tcg/emit.c.inc | 8 ++++---- 4 files changed, 16 insertions(+), 19 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 3c207ac62d6..a52a1bf0f21 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -22,8 +22,8 @@ DEF_HELPER_FLAGS_5(bndstx32, TCG_CALL_NO_WG, void, env, t= l, tl, i64, i64) DEF_HELPER_FLAGS_5(bndstx64, TCG_CALL_NO_WG, void, env, tl, tl, i64, i64) DEF_HELPER_1(bnd_jmp, void, env) =20 -DEF_HELPER_2(aam, void, env, int) -DEF_HELPER_2(aad, void, env, int) +DEF_HELPER_FLAGS_2(aam, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(aad, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_1(aaa, void, env) DEF_HELPER_1(aas, void, env) DEF_HELPER_1(daa, void, env) diff --git a/target/i386/tcg/int_helper.c b/target/i386/tcg/int_helper.c index df16130f5df..4cc59f15203 100644 --- a/target/i386/tcg/int_helper.c +++ b/target/i386/tcg/int_helper.c @@ -145,27 +145,24 @@ void helper_idivl_EAX(CPUX86State *env, target_ulong = t0) =20 /* bcd */ =20 -/* XXX: exception */ -void helper_aam(CPUX86State *env, int base) +target_ulong helper_aam(target_ulong al, target_ulong base) { - int al, ah; + int ah; =20 - al =3D env->regs[R_EAX] & 0xff; + al &=3D 0xff; ah =3D al / base; al =3D al % base; - env->regs[R_EAX] =3D (env->regs[R_EAX] & ~0xffff) | al | (ah << 8); - CC_DST =3D al; + return al | (ah << 8); } =20 -void helper_aad(CPUX86State *env, int base) +target_ulong helper_aad(target_ulong ax, target_ulong base) { int al, ah; =20 - al =3D env->regs[R_EAX] & 0xff; - ah =3D (env->regs[R_EAX] >> 8) & 0xff; + al =3D ax & 0xff; + ah =3D (ax >> 8) & 0xff; al =3D ((ah * base) + al) & 0xff; - env->regs[R_EAX] =3D (env->regs[R_EAX] & ~0xffff) | al; - CC_DST =3D al; + return al; } =20 void helper_aaa(CPUX86State *env) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index 141ab2bc560..27dc1bb146b 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -1480,8 +1480,8 @@ static const X86OpEntry opcodes_root[256] =3D { [0xD1] =3D X86_OP_GROUP1(group2, E,v), [0xD2] =3D X86_OP_GROUP2(group2, E,b, 1,b), /* CL */ [0xD3] =3D X86_OP_GROUP2(group2, E,v, 1,b), /* CL */ - [0xD4] =3D X86_OP_ENTRYr(AAM, I,b), - [0xD5] =3D X86_OP_ENTRYr(AAD, I,b), + [0xD4] =3D X86_OP_ENTRY2(AAM, 0,w, I,b), + [0xD5] =3D X86_OP_ENTRY2(AAD, 0,w, I,b), [0xD6] =3D X86_OP_ENTRYw(SALC, 0,b), [0xD7] =3D X86_OP_ENTRY1(XLAT, 0,b, zextT0), /* AL read/written */ =20 diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 33cb59e54b8..c78e35b1e28 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1084,8 +1084,8 @@ static void gen_AAA(DisasContext *s, CPUX86State *env= , X86DecodedInsn *decode) =20 static void gen_AAD(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) { - gen_helper_aad(tcg_env, tcg_constant_i32(decode->immediate)); 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476542158100007 Content-Type: text/plain; charset="utf-8" From: Bernhard Beschow In the -bios case the "isa-bios" memory region is an alias to the BIOS mapp= ed to the top of the 4G memory boundary. Do the same in the -pflash case, but = only for new machine versions for migration compatibility. This establishes comm= on behavior and makes pflash commands work in the "isa-bios" region which some real-world legacy bioses rely on. Note that in the sev_enabled() case, the "isa-bios" memory region in the -p= flash case will now also point to encrypted memory, just like it already does in = the -bios case. When running `info mtree` before and after this commit with `qemu-system-x86_64 -S -drive \ if=3Dpflash,format=3Draw,readonly=3Don,file=3D/usr/share/qemu/bios-256k.bin= ` and running `diff -u before.mtree after.mtree` results in the following changes in the memory tree: --- before.mtree +++ after.mtree @@ -71,7 +71,7 @@ 0000000000000000-ffffffffffffffff (prio -1, i/o): pci 00000000000a0000-00000000000bffff (prio 1, i/o): vga-lowmem 00000000000c0000-00000000000dffff (prio 1, rom): pc.rom - 00000000000e0000-00000000000fffff (prio 1, rom): isa-bios + 00000000000e0000-00000000000fffff (prio 1, romd): alias isa-bios = @system.flash0 0000000000020000-000000000003ffff 00000000000a0000-00000000000bffff (prio 1, i/o): alias smram-region= @pci 00000000000a0000-00000000000bffff 00000000000c0000-00000000000c3fff (prio 1, i/o): alias pam-pci @pci= 00000000000c0000-00000000000c3fff 00000000000c4000-00000000000c7fff (prio 1, i/o): alias pam-pci @pci= 00000000000c4000-00000000000c7fff @@ -108,7 +108,7 @@ 0000000000000000-ffffffffffffffff (prio -1, i/o): pci 00000000000a0000-00000000000bffff (prio 1, i/o): vga-lowmem 00000000000c0000-00000000000dffff (prio 1, rom): pc.rom - 00000000000e0000-00000000000fffff (prio 1, rom): isa-bios + 00000000000e0000-00000000000fffff (prio 1, romd): alias isa-bios = @system.flash0 0000000000020000-000000000003ffff 00000000000a0000-00000000000bffff (prio 1, i/o): alias smram-region= @pci 00000000000a0000-00000000000bffff 00000000000c0000-00000000000c3fff (prio 1, i/o): alias pam-pci @pci= 00000000000c0000-00000000000c3fff 00000000000c4000-00000000000c7fff (prio 1, i/o): alias pam-pci @pci= 00000000000c4000-00000000000c7fff @@ -131,11 +131,14 @@ memory-region: pc.ram 0000000000000000-0000000007ffffff (prio 0, ram): pc.ram +memory-region: system.flash0 + 00000000fffc0000-00000000ffffffff (prio 0, romd): system.flash0 + memory-region: pci 0000000000000000-ffffffffffffffff (prio -1, i/o): pci 00000000000a0000-00000000000bffff (prio 1, i/o): vga-lowmem 00000000000c0000-00000000000dffff (prio 1, rom): pc.rom - 00000000000e0000-00000000000fffff (prio 1, rom): isa-bios + 00000000000e0000-00000000000fffff (prio 1, romd): alias isa-bios @s= ystem.flash0 0000000000020000-000000000003ffff memory-region: smram 00000000000a0000-00000000000bffff (prio 0, ram): alias smram-low @p= c.ram 00000000000a0000-00000000000bffff Note that in both cases the "system" memory region contains the entry 00000000fffc0000-00000000ffffffff (prio 0, romd): system.flash0 but the "system.flash0" memory region only appears standalone when "isa-bio= s" is an alias. Signed-off-by: Bernhard Beschow Message-ID: <20240508175507.22270-7-shentey@gmail.com> Signed-off-by: Paolo Bonzini --- include/hw/i386/pc.h | 1 + hw/i386/pc.c | 1 + hw/i386/pc_piix.c | 3 +++ hw/i386/pc_q35.c | 2 ++ hw/i386/pc_sysfw.c | 8 +++++++- 5 files changed, 14 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index e52290916cb..ad9c3d9ba84 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -119,6 +119,7 @@ struct PCMachineClass { bool enforce_aligned_dimm; bool broken_reserved_end; bool enforce_amd_1tb_hole; + bool isa_bios_alias; =20 /* generate legacy CPU hotplug AML */ bool legacy_cpu_hotplug; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index bfb46e9b548..4a2d6f5a97f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1816,6 +1816,7 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) pcmc->has_reserved_memory =3D true; pcmc->enforce_aligned_dimm =3D true; pcmc->enforce_amd_1tb_hole =3D true; + pcmc->isa_bios_alias =3D true; /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K rep= orted * to be used at the moment, 32K should be enough for a while. */ pcmc->acpi_data_size =3D 0x20000 + 0x8000; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 99efb3c45cb..ebb51de3809 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -526,12 +526,15 @@ DEFINE_I440FX_MACHINE(v9_1, "pc-i440fx-9.1", NULL, =20 static void pc_i440fx_9_0_machine_options(MachineClass *m) { + PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); + pc_i440fx_9_1_machine_options(m); m->alias =3D NULL; m->is_default =3D false; =20 compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len); compat_props_add(m->compat_props, pc_compat_9_0, pc_compat_9_0_len); + pcmc->isa_bios_alias =3D false; } =20 DEFINE_I440FX_MACHINE(v9_0, "pc-i440fx-9.0", NULL, diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index bb53a51ac18..bd7db4abacf 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -378,10 +378,12 @@ DEFINE_Q35_MACHINE(v9_1, "pc-q35-9.1", NULL, =20 static void pc_q35_9_0_machine_options(MachineClass *m) { + PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_q35_9_1_machine_options(m); m->alias =3D NULL; compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len); compat_props_add(m->compat_props, pc_compat_9_0, pc_compat_9_0_len); + pcmc->isa_bios_alias =3D false; } =20 DEFINE_Q35_MACHINE(v9_0, "pc-q35-9.0", NULL, diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c index 82d37cb376b..ac88ad4eb91 100644 --- a/hw/i386/pc_sysfw.c +++ b/hw/i386/pc_sysfw.c @@ -135,6 +135,7 @@ static void pc_system_flash_map(PCMachineState *pcms, MemoryRegion *rom_memory) { X86MachineState *x86ms =3D X86_MACHINE(pcms); + PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); hwaddr total_size =3D 0; int i; BlockBackend *blk; @@ -184,7 +185,12 @@ static void pc_system_flash_map(PCMachineState *pcms, =20 if (i =3D=3D 0) { flash_mem =3D pflash_cfi01_get_memory(system_flash); - pc_isa_bios_init(&x86ms->isa_bios, rom_memory, flash_mem); + if (pcmc->isa_bios_alias) { + x86_isa_bios_init(&x86ms->isa_bios, rom_memory, flash_mem, + true); + } else { + pc_isa_bios_init(&x86ms->isa_bios, rom_memory, flash_mem); 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Thu, 23 May 2024 08:00:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEtAyeJnE9twfRIyB5xIl0CB00jkA8pSanx9ALQdaztBFwwBF/qaAj3YrjC6fhJyTA3AY39Sw== X-Received: by 2002:a17:906:749:b0:a5a:5496:3c76 with SMTP id a640c23a62f3a-a622806c243mr410629166b.6.1716476447348; Thu, 23 May 2024 08:00:47 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Robert Hoo , Binbin Wu , Xuelian Guo , Xiaoyao Li , Zhao Liu Subject: [PULL 04/23] target/i386: add support for LAM in CPUID enumeration Date: Thu, 23 May 2024 17:00:17 +0200 Message-ID: <20240523150036.1050011-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476578259100005 Content-Type: text/plain; charset="utf-8" From: Robert Hoo Linear Address Masking (LAM) is a new Intel CPU feature, which allows software to use of the untranslated address bits for metadata. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EAX[26] Add CPUID definition for LAM. Note LAM feature is not supported for TCG of target-i386, LAM CPIUD bit will not be added to TCG_7_1_EAX_FEATURES. More info can be found in Intel ISE Chapter "LINEAR ADDRESS MASKING(LAM)" https://cdrdv2.intel.com/v1/dl/getContent/671368 Signed-off-by: Robert Hoo Co-developed-by: Binbin Wu Signed-off-by: Binbin Wu Tested-by: Xuelian Guo Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu Message-ID: <20240112060042.19925-2-binbin.wu@linux.intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 2 ++ target/i386/cpu.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ccccb62fc35..107f263429a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -927,6 +927,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, #define CPUID_7_1_EAX_AMX_FP16 (1U << 21) /* Support for VPMADD52[H,L]UQ */ #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) +/* Linear Address Masking */ +#define CPUID_7_1_EAX_LAM (1U << 26) =20 /* Support for VPDPB[SU,UU,SS]D[,S] */ #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index cfe7c92d6bc..de1ad7270cf 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -969,7 +969,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "fsrc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "amx-fp16", NULL, "avx-ifma", - NULL, NULL, NULL, NULL, + NULL, NULL, "lam", NULL, NULL, NULL, NULL, NULL, }, .cpuid =3D { --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 23 May 2024 08:00:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFm1M09VvNVArFCumNveWJtkXO3dKW0qJg/6a/ry97/O/Nziuf/a/Shg89WXuDgWHcOGfykiQ== X-Received: by 2002:ac2:4154:0:b0:523:97ee:c1f4 with SMTP id 2adb3069b0e04-526bf545f4dmr3424907e87.56.1716476449667; Thu, 23 May 2024 08:00:49 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Binbin Wu , Xuelian Guo , Xiaoyao Li , Zhao Liu Subject: [PULL 05/23] target/i386: add control bits support for LAM Date: Thu, 23 May 2024 17:00:18 +0200 Message-ID: <20240523150036.1050011-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476469720100001 Content-Type: text/plain; charset="utf-8" From: Binbin Wu LAM uses CR3[61] and CR3[62] to configure/enable LAM on user pointers. LAM uses CR4[28] to configure/enable LAM on supervisor pointers. For CR3 LAM bits, no additional handling needed: - TCG LAM is not supported for TCG of target-i386. helper_write_crN() and helper_vmrun() check max physical address bits before calling cpu_x86_update_cr3(), no change needed, i.e. CR3 LAM bits are not allowed to be set in TCG. - gdbstub x86_cpu_gdb_write_register() will call cpu_x86_update_cr3() to update cr3. Allow gdb to set the LAM bit(s) to CR3, if vcpu doesn't support LAM, KVM_SET_SREGS will fail as other reserved bits. For CR4 LAM bit, its reservation depends on vcpu supporting LAM feature or not. - TCG LAM is not supported for TCG of target-i386. helper_write_crN() and helper_vmrun() check CR4 reserved bit before calling cpu_x86_update_cr4(), i.e. CR4 LAM bit is not allowed to be set in TCG. - gdbstub x86_cpu_gdb_write_register() will call cpu_x86_update_cr4() to update cr4. Mask out LAM bit on CR4 if vcpu doesn't support LAM. - x86_cpu_reset_hold() doesn't need special handling. Signed-off-by: Binbin Wu Tested-by: Xuelian Guo Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu Message-ID: <20240112060042.19925-3-binbin.wu@linux.intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 7 ++++++- target/i386/helper.c | 4 ++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 107f263429a..ccf6811794e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -258,6 +258,7 @@ typedef enum X86Seg { #define CR4_SMAP_MASK (1U << 21) #define CR4_PKE_MASK (1U << 22) #define CR4_PKS_MASK (1U << 24) +#define CR4_LAM_SUP_MASK (1U << 28) =20 #define CR4_RESERVED_MASK \ (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ @@ -266,7 +267,8 @@ typedef enum X86Seg { | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \ | CR4_LA57_MASK \ | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ - | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_M= ASK)) + | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_M= ASK \ + | CR4_LAM_SUP_MASK)) =20 #define DR6_BD (1 << 13) #define DR6_BS (1 << 14) @@ -2563,6 +2565,9 @@ static inline uint64_t cr4_reserved_bits(CPUX86State = *env) if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { reserved_bits |=3D CR4_PKS_MASK; } + if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) { + reserved_bits |=3D CR4_LAM_SUP_MASK; + } return reserved_bits; } =20 diff --git a/target/i386/helper.c b/target/i386/helper.c index 48d1513a35a..f9d1381f90b 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -219,6 +219,10 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new= _cr4) new_cr4 &=3D ~CR4_PKS_MASK; } =20 + if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) { + new_cr4 &=3D ~CR4_LAM_SUP_MASK; + } + env->cr[4] =3D new_cr4; env->hflags =3D hflags; =20 --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1716476503; cv=none; d=zohomail.com; s=zohoarc; b=etYyoG0nDl+HiY2ZdacPWFb7C2KT0N+LdTWv5oZoRYPGOAowdqJXKTdTsp73pHcL/Psj/2GmWP5CSk32hbChwQU2B7tE1+Okgyqa6OXTV1AiyWQESzl76guM0Hu6ugUGUTW0gDwRa/XaeVIzBXMrpWZBUhPnblVnn3LvoMsuURg= ARC-Message-Signature: i=1; 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Thu, 23 May 2024 08:00:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IESRppVHw6OSjrP8Qr8czZVtfHjhw7DkxPSJYwN9zh+MHrd1dc/Jhz8C9J9feD7SDDHUGnkpA== X-Received: by 2002:a17:906:1854:b0:a62:2b65:1dd5 with SMTP id a640c23a62f3a-a622b65233cmr319042866b.58.1716476452207; Thu, 23 May 2024 08:00:52 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Robert Hoo , Xiaoyao Li , Babu Moger , Yongwei Ma , "Michael S . Tsirkin" Subject: [PULL 06/23] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Date: Thu, 23 May 2024 17:00:19 +0200 Message-ID: <20240523150036.1050011-7-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476503855100002 Content-Type: text/plain; charset="utf-8" From: Zhao Liu For i-cache and d-cache, current QEMU hardcodes the maximum IDs for CPUs sharing cache (CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) to 0, and this means i-cache and d-cache are shared in the SMT level. This is correct if there's single thread per core, but is wrong for the hyper threading case (one core contains multiple threads) since the i-cache and d-cache are shared in the core level other than SMT level. For AMD CPU, commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information for cpuid 0x8000001D") has already introduced i/d cache topology as core level by default. Therefore, in order to be compatible with both multi-threaded and single-threaded situations, we should set i-cache and d-cache be shared at the core level by default. This fix changes the default i/d cache topology from per-thread to per-core. Potentially, this change in L1 cache topology may affect the performance of the VM if the user does not specifically specify the topology or bind the vCPU. However, the way to achieve optimal performance should be to create a reasonable topology and set the appropriate vCPU affinity without relying on QEMU's default topology structure. Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistentl= y") Suggested-by: Robert Hoo Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Message-ID: <20240424154929.1487382-6-zhao1.liu@intel.com> [Add compat property. - Paolo] Signed-off-by: Paolo Bonzini --- hw/i386/pc.c | 1 + target/i386/cpu.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 4a2d6f5a97f..6126bfdd2a7 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -79,6 +79,7 @@ { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, =20 GlobalProperty pc_compat_9_0[] =3D { + { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, { TYPE_X86_CPU, "guest-phys-bits", "0" }, { "sev-guest", "legacy-vm-type", "true" }, { TYPE_X86_CPU, "legacy-multi-node", "on" }, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index de1ad7270cf..3c66242f6d3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6258,15 +6258,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, *eax =3D *ebx =3D *ecx =3D *edx =3D 0; } else { *eax =3D 0; + int apic_ids_sharing_l1 =3D cpu->l1_cache_per_core ? cs->nr_th= reads : 1; switch (count) { case 0: /* L1 dcache info */ encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - 1, cs->nr_cores, + apic_ids_sharing_l1, cs->nr_cores, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - 1, cs->nr_cores, + apic_ids_sharing_l1, cs->nr_cores, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ @@ -8105,6 +8106,7 @@ static Property x86_cpu_properties[] =3D { false), DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, true), + DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, t= rue), DEFINE_PROP_END_OF_LIST() }; =20 --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Thu, 23 May 2024 08:00:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHLhQjuaMmnqZnOhZnc8p+AieE+ED4aduMULZnVF2+HgTQfVSbKulXKBrC5G13MSFm84L+I0Q== X-Received: by 2002:a17:906:a38f:b0:a59:c23d:85d8 with SMTP id a640c23a62f3a-a6228156097mr314606466b.51.1716476454530; Thu, 23 May 2024 08:00:54 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Robert Hoo , Yongwei Ma , Babu Moger Subject: [PULL 07/23] i386/cpu: Use APIC ID info to encode cache topo in CPUID[4] Date: Thu, 23 May 2024 17:00:20 +0200 Message-ID: <20240523150036.1050011-8-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476654736100005 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the nearest power-of-2 integer. The nearest power-of-2 integer can be calculated by pow2ceil() or by using APIC ID offset/width (like L3 topology using 1 << die_offset [3]). But in fact, CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] are associated with APIC ID. For example, in linux kernel, the field "num_threads_sharing" (Bits 25 - 14) is parsed with APIC ID. And for another example, on Alder Lake P, the CPUID.04H:EAX[bits 31:26] is not matched with actual core numbers and it's calculated by: "(1 << (pkg_offset - core_offset)) - 1". Therefore the topology information of APIC ID should be preferred to calculate nearest power-of-2 integer for CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26]: 1. d/i cache is shared in a core, 1 << core_offset should be used instead of "cs->nr_threads" in encode_cache_cpuid4() for CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]. 2. L2 cache is supposed to be shared in a core as for now, thereby 1 << core_offset should also be used instead of "cs->nr_threads" in encode_cache_cpuid4() for CPUID.04H.02H:EAX[bits 25:14]. 3. Similarly, the value for CPUID.04H:EAX[bits 31:26] should also be calculated with the bit width between the package and SMT levels in the APIC ID (1 << (pkg_offset - core_offset) - 1). In addition, use APIC ID bits calculations to replace "pow2ceil()" for cache_info_passthrough case. [1]: efb3934adf9e ("x86: cpu: make sure number of addressable IDs for proce= ssor cores meets the spec") [2]: d7caf13b5fcf ("x86: cpu: fixup number of addressable IDs for logical p= rocessors sharing cache") [3]: d65af288a84d ("i386: Update new x86_apicid parsing rules with die_offs= et support") Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistentl= y") Suggested-by: Robert Hoo Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Tested-by: Babu Moger Message-ID: <20240424154929.1487382-7-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 50 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 40 insertions(+), 10 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3c66242f6d3..f3d2b8053b2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6162,7 +6162,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, { X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); - uint32_t die_offset; uint32_t limit; uint32_t signature[3]; X86CPUTopoInfo topo_info; @@ -6234,7 +6233,18 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) = << 8) | (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); break; - case 4: + case 4: { + /* + * CPUID.04H:EAX[bits 25:14]: Maximum number of addressable IDs for + * logical processors sharing this cache. + */ + int addressable_threads_width; + /* + * CPUID.04H:EAX[bits 31:26]: Maximum number of addressable IDs for + * processor cores in the physical package. + */ + int addressable_cores_width; + /* cache info: needed for Core compatibility */ if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); @@ -6246,40 +6256,59 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); int vcpus_per_socket =3D cs->nr_cores * cs->nr_threads; if (cs->nr_cores > 1) { + addressable_cores_width =3D apicid_pkg_offset(&topo_in= fo) - + apicid_core_offset(&topo_inf= o); + *eax &=3D ~0xFC000000; - *eax |=3D (pow2ceil(cs->nr_cores) - 1) << 26; + *eax |=3D ((1 << addressable_cores_width) - 1) << 26; } if (host_vcpus_per_cache > vcpus_per_socket) { + /* Share the cache at package level. */ + addressable_threads_width =3D apicid_pkg_offset(&topo_= info); + *eax &=3D ~0x3FFC000; - *eax |=3D (pow2ceil(vcpus_per_socket) - 1) << 14; + *eax |=3D ((1 << addressable_threads_width) - 1) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; } else { *eax =3D 0; - int apic_ids_sharing_l1 =3D cpu->l1_cache_per_core ? cs->nr_th= reads : 1; + addressable_cores_width =3D apicid_pkg_offset(&topo_info) - + apicid_core_offset(&topo_info); + switch (count) { case 0: /* L1 dcache info */ + addressable_threads_width =3D cpu->l1_cache_per_core + ? apicid_core_offset(&topo_info) + : 0; encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - apic_ids_sharing_l1, cs->nr_cores, + (1 << addressable_threads_width), + (1 << addressable_cores_width), eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ + addressable_threads_width =3D cpu->l1_cache_per_core + ? apicid_core_offset(&topo_info) + : 0; encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - apic_ids_sharing_l1, cs->nr_cores, + (1 << addressable_threads_width), + (1 << addressable_cores_width), eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ + addressable_threads_width =3D apicid_core_offset(&topo_inf= o); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - cs->nr_threads, cs->nr_cores, + (1 << addressable_threads_width), + (1 << addressable_cores_width), eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - die_offset =3D apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { + addressable_threads_width =3D apicid_die_offset(&topo_= info); encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << die_offset), cs->nr_cores, + (1 << addressable_threads_width), + (1 << addressable_cores_width), eax, ebx, ecx, edx); break; } @@ -6290,6 +6319,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, } } break; 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Thu, 23 May 2024 08:00:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF/Jd+10a5QOCxHN7FohL3jqfVV9WJ8VXZOV2ru77aqUuREjvc7MTQZGWfAb3XrQ/quXCGoUQ== X-Received: by 2002:a17:906:f2ce:b0:a62:c02:425a with SMTP id a640c23a62f3a-a62281c804amr373190166b.74.1716476456742; Thu, 23 May 2024 08:00:56 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Yongwei Ma , Babu Moger , Xiaoyao Li Subject: [PULL 08/23] i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Date: Thu, 23 May 2024 17:00:21 +0200 Message-ID: <20240523150036.1050011-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476540151100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information for cpuid 0x8000001D") adds the cache topology for AMD CPU by encoding the number of sharing threads directly. From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14]) means [1]: The number of logical processors sharing this cache is the value of this field incremented by 1. To determine which logical processors are sharing a cache, determine a Share Id for each processor as follows: ShareId =3D LocalApicId >> log2(NumSharingCache+1) Logical processors with the same ShareId then share a cache. If NumSharingCache+1 is not a power of two, round it up to the next power of two. From the description above, the calculation of this field should be same as CPUID[4].EAX[bits 25:14] for Intel CPUs. So also use the offsets of APIC ID to calculate this field. [1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology Information Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Reviewed-by: Babu Moger Tested-by: Babu Moger Reviewed-by: Xiaoyao Li Message-ID: <20240424154929.1487382-8-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f3d2b8053b2..22a8ca1c9b4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -331,7 +331,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *ca= che, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t l3_threads; + uint32_t num_sharing_cache; assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 @@ -340,11 +340,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_threads =3D topo_info->cores_per_die * topo_info->threads_per_c= ore; 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Thu, 23 May 2024 08:01:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGChYLkUZANX7KubOBc9U7PW6Kck59/D6CINuJZYufReVR+uKaFg9YHVQOzdytWHAWLIGgKxQ== X-Received: by 2002:a17:906:b1d5:b0:a59:d063:f5f3 with SMTP id a640c23a62f3a-a622818ebabmr346329466b.63.1716476459812; Thu, 23 May 2024 08:00:59 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Robert Hoo , Yongwei Ma , Xiaoyao Li , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger Subject: [PULL 09/23] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Date: Thu, 23 May 2024 17:00:22 +0200 Message-ID: <20240523150036.1050011-10-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476503889100004 From: Zhao Liu In cpu_x86_cpuid(), there are many variables in representing the cpu topology, e.g., topo_info, cs->nr_cores and cs->nr_threads. Since the names of cs->nr_cores and cs->nr_threads do not accurately represent its meaning, the use of cs->nr_cores or cs->nr_threads is prone to confusion and mistakes. And the structure X86CPUTopoInfo names its members clearly, thus the variable "topo_info" should be preferred. In addition, in cpu_x86_cpuid(), to uniformly use the topology variable, replace env->dies with topo_info.dies_per_pkg as well. Suggested-by: Robert Hoo Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Babu Moger Message-ID: <20240424154929.1487382-9-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 22a8ca1c9b4..363f5ee4bec 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6165,11 +6165,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, uint32_t limit; uint32_t signature[3]; X86CPUTopoInfo topo_info; + uint32_t cores_per_pkg; + uint32_t threads_per_pkg; =20 topo_info.dies_per_pkg =3D env->nr_dies; topo_info.cores_per_die =3D cs->nr_cores / env->nr_dies; topo_info.threads_per_core =3D cs->nr_threads; =20 + cores_per_pkg =3D topo_info.cores_per_die * topo_info.dies_per_pkg; + threads_per_pkg =3D cores_per_pkg * topo_info.threads_per_core; + /* Calculate & apply limits for different index ranges */ if (index >=3D 0xC0000000) { limit =3D env->cpuid_xlevel2; @@ -6205,8 +6210,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *ecx |=3D CPUID_EXT_OSXSAVE; } *edx =3D env->features[FEAT_1_EDX]; - if (cs->nr_cores * cs->nr_threads > 1) { - *ebx |=3D (cs->nr_cores * cs->nr_threads) << 16; + if (threads_per_pkg > 1) { + *ebx |=3D threads_per_pkg << 16; *edx |=3D CPUID_HT; } if (!cpu->enable_pmu) { @@ -6254,15 +6259,15 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, */ if (*eax & 31) { int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); - int vcpus_per_socket =3D cs->nr_cores * cs->nr_threads; - if (cs->nr_cores > 1) { + + if (cores_per_pkg > 1) { addressable_cores_width =3D apicid_pkg_offset(&topo_in= fo) - apicid_core_offset(&topo_inf= o); =20 *eax &=3D ~0xFC000000; *eax |=3D ((1 << addressable_cores_width) - 1) << 26; } - if (host_vcpus_per_cache > vcpus_per_socket) { + if (host_vcpus_per_cache > threads_per_pkg) { /* Share the cache at package level. */ addressable_threads_width =3D apicid_pkg_offset(&topo_= info); =20 @@ -6412,12 +6417,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, switch (count) { case 0: *eax =3D apicid_core_offset(&topo_info); - *ebx =3D cs->nr_threads; + *ebx =3D topo_info.threads_per_core; *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: *eax =3D apicid_pkg_offset(&topo_info); - *ebx =3D cs->nr_cores * cs->nr_threads; + *ebx =3D threads_per_pkg; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; default: @@ -6437,7 +6442,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 0x1F: /* V2 Extended Topology Enumeration Leaf */ - if (env->nr_dies < 2) { + if (topo_info.dies_per_pkg < 2) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; break; } @@ -6447,7 +6452,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, switch (count) { case 0: *eax =3D apicid_core_offset(&topo_info); - *ebx =3D cs->nr_threads; + *ebx =3D topo_info.threads_per_core; *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: @@ -6457,7 +6462,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 2: *eax =3D apicid_pkg_offset(&topo_info); - *ebx =3D cs->nr_cores * cs->nr_threads; + *ebx =3D threads_per_pkg; *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; break; default: @@ -6685,7 +6690,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, * discards multiple thread information if it is set. * So don't set it here for Intel to make Linux guests happy. */ - if (cs->nr_cores * cs->nr_threads > 1) { + if (threads_per_pkg > 1) { if (env->cpuid_vendor1 !=3D CPUID_VENDOR_INTEL_1 || env->cpuid_vendor2 !=3D CPUID_VENDOR_INTEL_2 || env->cpuid_vendor3 !=3D CPUID_VENDOR_INTEL_3) { @@ -6752,7 +6757,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *eax |=3D (cpu->guest_phys_bits << 16); } *ebx =3D env->features[FEAT_8000_0008_EBX]; - if (cs->nr_cores * cs->nr_threads > 1) { + if (threads_per_pkg > 1) { /* * Bits 15:12 is "The number of bits in the initial * Core::X86::Apic::ApicId[ApicId] value that indicate @@ -6760,7 +6765,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, * Bits 7:0 is "The number of threads in the package is NC+1" */ *ecx =3D (apicid_pkg_offset(&topo_info) << 12) | - ((cs->nr_cores * cs->nr_threads) - 1); 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Thu, 23 May 2024 08:01:02 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH3yK90brmvquuNyKtI4pE51gWv7k6JKRubOEDQzN2Ma4zAumw8u1yib6lH4YBnDleNSyEwmw== X-Received: by 2002:a17:906:a1d4:b0:a59:a033:3e2 with SMTP id a640c23a62f3a-a622820b853mr492903166b.74.1716476462152; Thu, 23 May 2024 08:01:02 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Yongwei Ma , Babu Moger , Xiaoyao Li Subject: [PULL 10/23] i386/cpu: Introduce bitmap to cache available CPU topology levels Date: Thu, 23 May 2024 17:00:23 +0200 Message-ID: <20240523150036.1050011-11-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476503866100003 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Currently, QEMU checks the specify number of topology domains to detect if there's extended topology levels (e.g., checking nr_dies). With this bitmap, the extended CPU topology (the levels other than SMT, core and package) could be easier to detect without touching the topology details. This is also in preparation for the follow-up to decouple CPUID[0x1F] subleaf with specific topology level. Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Tested-by: Babu Moger Reviewed-by: Xiaoyao Li Message-ID: <20240424154929.1487382-10-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- include/hw/i386/topology.h | 23 +++++++++++++++++++++++ target/i386/cpu.h | 4 ++++ hw/i386/x86-common.c | 5 ++++- target/i386/cpu.c | 18 +++++++++++++++--- target/i386/kvm/kvm.c | 3 ++- 5 files changed, 48 insertions(+), 5 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index d4eeb7ab829..befeb92b0b1 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -60,6 +60,21 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; =20 +/* + * CPUTopoLevel is the general i386 topology hierarchical representation, + * ordered by increasing hierarchical relationship. + * Its enumeration value is not bound to the type value of Intel (CPUID[0x= 1F]) + * or AMD (CPUID[0x80000026]). + */ +enum CPUTopoLevel { + CPU_TOPO_LEVEL_INVALID, + CPU_TOPO_LEVEL_SMT, + CPU_TOPO_LEVEL_CORE, + CPU_TOPO_LEVEL_DIE, + CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPO_LEVEL_MAX, +}; + /* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) { @@ -168,4 +183,12 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CPU= TopoInfo *topo_info, return x86_apicid_from_topo_ids(topo_info, &topo_ids); } =20 +/* + * Check whether there's extended topology level (die)? + */ +static inline bool x86_has_extended_topo(unsigned long *topo_bitmap) +{ + return test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap); +} + #endif /* HW_I386_TOPOLOGY_H */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ccf6811794e..9e7b9e918e9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -24,6 +24,7 @@ #include "cpu-qom.h" #include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" +#include "hw/i386/topology.h" #include "qapi/qapi-types-common.h" #include "qemu/cpu-float.h" #include "qemu/timer.h" @@ -1891,6 +1892,9 @@ typedef struct CPUArchState { =20 /* Number of dies within this CPU package. */ unsigned nr_dies; + + /* Bitmap of available CPU topology levels for this CPU. */ + DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX); } CPUX86State; =20 struct kvm_msrs; diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 67b03c913a5..7d4f9b20f23 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -271,7 +271,10 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 init_topo_info(&topo_info, x86ms); =20 - env->nr_dies =3D ms->smp.dies; + if (ms->smp.dies > 1) { + env->nr_dies =3D ms->smp.dies; + set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo); + } =20 /* * If APIC ID is not set, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 363f5ee4bec..8419055006c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6442,7 +6442,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 0x1F: /* V2 Extended Topology Enumeration Leaf */ - if (topo_info.dies_per_pkg < 2) { + if (!x86_has_extended_topo(env->avail_cpu_topo)) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; break; } @@ -7275,7 +7275,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **err= p) * cpu->vendor_cpuid_only has been unset for compatibility with ol= der * machine types. */ - if ((env->nr_dies > 1) && + if (x86_has_extended_topo(env->avail_cpu_topo) && (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); } @@ -7798,13 +7798,25 @@ static void x86_cpu_post_initfn(Object *obj) accel_cpu_instance_init(CPU(obj)); } =20 +static void x86_cpu_init_default_topo(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + + env->nr_dies =3D 1; + + /* SMT, core and package levels are set by default. */ + set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); + set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); + set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); +} + static void x86_cpu_initfn(Object *obj) { X86CPU *cpu =3D X86_CPU(obj); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(obj); CPUX86State *env =3D &cpu->env; =20 - env->nr_dies =3D 1; + x86_cpu_init_default_topo(cpu); =20 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", x86_cpu_get_feature_words, diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index c5943605ee3..6c864e4611f 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -51,6 +51,7 @@ #include "hw/i386/apic_internal.h" #include "hw/i386/apic-msidef.h" #include "hw/i386/intel_iommu.h" +#include "hw/i386/topology.h" #include "hw/i386/x86-iommu.h" #include "hw/i386/e820_memory_layout.h" =20 @@ -1791,7 +1792,7 @@ static uint32_t kvm_x86_build_cpuid(CPUX86State *env, break; } case 0x1f: - if (env->nr_dies < 2) { + if (!x86_has_extended_topo(env->avail_cpu_topo)) { cpuid_i--; break; } --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1716476547; cv=none; d=zohomail.com; s=zohoarc; b=XVYVk/lfUexr3WqdEWv4G2eJZm6Pdh4DDqn6nl0afL7SzY885C/ZDdjbdihf1O3fzOKOtP+pPyzKDrLiHpobEEwVIKCcb6BMdKLeNHY6TAgEDVeTvXHZNhV9V2IEGoGmTpO9F4PoHzJlZQc71Ap5OQ5vdnyvS+svkIHUJ0kgTvA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716476547; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger Subject: [PULL 11/23] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Date: Thu, 23 May 2024 17:00:24 +0200 Message-ID: <20240523150036.1050011-12-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476548092100001 From: Zhao Liu CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared by Intel and AMD CPUs. But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU (in CPUID[0x80000026]) have the different definitions with different enumeration values. Though CPUID[0x80000026] hasn't been implemented in QEMU, to avoid possible misunderstanding, split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] and introduce CPUID[0x1F]-specific topology types. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Babu Moger Message-ID: <20240424154929.1487382-11-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 13 +++++++++---- target/i386/cpu.c | 14 +++++++------- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9e7b9e918e9..8c83900202d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1016,10 +1016,15 @@ uint64_t x86_cpu_get_supported_feature_word(Feature= Word w, #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ =20 /* CPUID[0xB].ECX level types */ -#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) -#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) -#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) -#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) +#define CPUID_B_ECX_TOPO_LEVEL_INVALID 0 +#define CPUID_B_ECX_TOPO_LEVEL_SMT 1 +#define CPUID_B_ECX_TOPO_LEVEL_CORE 2 + +/* COUID[0x1F].ECX level types */ +#define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID +#define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT +#define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE +#define CPUID_1F_ECX_TOPO_LEVEL_DIE 5 =20 /* MSR Feature Bits */ #define MSR_ARCH_CAP_RDCL_NO (1U << 0) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8419055006c..d350eb8a736 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6418,17 +6418,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, case 0: *eax =3D apicid_core_offset(&topo_info); *ebx =3D topo_info.threads_per_core; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + *ecx |=3D CPUID_B_ECX_TOPO_LEVEL_SMT << 8; break; case 1: *eax =3D apicid_pkg_offset(&topo_info); *ebx =3D threads_per_pkg; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + *ecx |=3D CPUID_B_ECX_TOPO_LEVEL_CORE << 8; break; default: *eax =3D 0; *ebx =3D 0; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + *ecx |=3D CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; } =20 assert(!(*eax & ~0x1f)); @@ -6453,22 +6453,22 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, case 0: *eax =3D apicid_core_offset(&topo_info); *ebx =3D topo_info.threads_per_core; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_SMT << 8; break; case 1: *eax =3D apicid_die_offset(&topo_info); *ebx =3D topo_info.cores_per_die * topo_info.threads_per_core; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_CORE << 8; break; case 2: *eax =3D apicid_pkg_offset(&topo_info); *ebx =3D threads_per_pkg; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_DIE << 8; break; default: *eax =3D 0; *ebx =3D 0; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_INVALID << 8; } assert(!(*eax & ~0x1f)); *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1716476541; cv=none; d=zohomail.com; s=zohoarc; b=m0MqWgJ1yKaF+wZYqxeJHjTT/TX0PSTgNCEqfFFTSvxWFLNozH1Gxecw3Gv4HMGx/Ov3xHbFe9yZQ9/BH5sP/bt7l8B0W9FMpnE7K2Pg+0N7EagPLWIxHdQQwqZVJcuggpXgpPalxTfUo58Pox8ZQQgDiETXv/22hKJHjwwBBD0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716476541; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 23 May 2024 08:01:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHb2pvwBpXQweIh+EVpst7RURPmvK8GQkeesuouQvuOgxInbbWjzKNU6TdCzYnLEcxJdqQf8Q== X-Received: by 2002:a17:906:254d:b0:a5a:88a9:3ef5 with SMTP id a640c23a62f3a-a622812e4femr331517366b.39.1716476467661; Thu, 23 May 2024 08:01:07 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Yongwei Ma , Babu Moger , Xiaoyao Li Subject: [PULL 12/23] i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level Date: Thu, 23 May 2024 17:00:25 +0200 Message-ID: <20240523150036.1050011-13-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476542121100006 Content-Type: text/plain; charset="utf-8" From: Zhao Liu At present, the subleaf 0x02 of CPUID[0x1F] is bound to the "die" level. In fact, the specific topology level exposed in 0x1F depends on the platform's support for extension levels (module, tile and die). To help expose "module" level in 0x1F, decouple CPUID[0x1F] subleaf with specific topology level. Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Tested-by: Babu Moger Reviewed-by: Xiaoyao Li Message-ID: <20240424154929.1487382-12-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 135 +++++++++++++++++++++++++++++++++++++--------- 1 file changed, 110 insertions(+), 25 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d350eb8a736..f95d539eeff 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -269,6 +269,115 @@ static void encode_cache_cpuid4(CPUCacheInfo *cache, (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); } =20 +static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, + enum CPUTopoLevel topo_level) +{ + switch (topo_level) { + case CPU_TOPO_LEVEL_SMT: + return 1; + case CPU_TOPO_LEVEL_CORE: + return topo_info->threads_per_core; + case CPU_TOPO_LEVEL_DIE: + return topo_info->threads_per_core * topo_info->cores_per_die; + case CPU_TOPO_LEVEL_PACKAGE: + return topo_info->threads_per_core * topo_info->cores_per_die * + topo_info->dies_per_pkg; + default: + g_assert_not_reached(); + } + return 0; +} + +static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, + enum CPUTopoLevel topo_level) +{ + switch (topo_level) { + case CPU_TOPO_LEVEL_SMT: + return 0; + case CPU_TOPO_LEVEL_CORE: + return apicid_core_offset(topo_info); + case CPU_TOPO_LEVEL_DIE: + return apicid_die_offset(topo_info); + case CPU_TOPO_LEVEL_PACKAGE: + return apicid_pkg_offset(topo_info); + default: + g_assert_not_reached(); + } + return 0; +} + +static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) +{ + switch (topo_level) { + case CPU_TOPO_LEVEL_INVALID: + return CPUID_1F_ECX_TOPO_LEVEL_INVALID; + case CPU_TOPO_LEVEL_SMT: + return CPUID_1F_ECX_TOPO_LEVEL_SMT; + case CPU_TOPO_LEVEL_CORE: + return CPUID_1F_ECX_TOPO_LEVEL_CORE; + case CPU_TOPO_LEVEL_DIE: + return CPUID_1F_ECX_TOPO_LEVEL_DIE; + default: + /* Other types are not supported in QEMU. */ + g_assert_not_reached(); + } + return 0; +} + +static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, + X86CPUTopoInfo *topo_info, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) +{ + X86CPU *cpu =3D env_archcpu(env); + unsigned long level, next_level; + uint32_t num_threads_next_level, offset_next_level; + + assert(count + 1 < CPU_TOPO_LEVEL_MAX); + + /* + * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. + * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). + */ + level =3D CPU_TOPO_LEVEL_INVALID; + for (int i =3D 0; i <=3D count; i++) { + level =3D find_next_bit(env->avail_cpu_topo, + CPU_TOPO_LEVEL_PACKAGE, + level + 1); + + /* + * CPUID[0x1f] doesn't explicitly encode the package level, + * and it just encodes the invalid level (all fields are 0) + * into the last subleaf of 0x1f. + */ + if (level =3D=3D CPU_TOPO_LEVEL_PACKAGE) { + level =3D CPU_TOPO_LEVEL_INVALID; + break; + } + } + + if (level =3D=3D CPU_TOPO_LEVEL_INVALID) { + num_threads_next_level =3D 0; + offset_next_level =3D 0; + } else { + next_level =3D find_next_bit(env->avail_cpu_topo, + CPU_TOPO_LEVEL_PACKAGE, + level + 1); + num_threads_next_level =3D num_threads_by_topo_level(topo_info, + next_level); + offset_next_level =3D apicid_offset_by_topo_level(topo_info, + next_level); + } + + *eax =3D offset_next_level; + /* The count (bits 15-00) doesn't need to be reliable. */ + *ebx =3D num_threads_next_level & 0xffff; + *ecx =3D (count & 0xff) | (cpuid1f_topo_type(level) << 8); + *edx =3D cpu->apic_id; + + assert(!(*eax & ~0x1f)); +} + /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) { @@ -6447,31 +6556,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, break; } =20 - *ecx =3D count & 0xff; - *edx =3D cpu->apic_id; - switch (count) { - case 0: - *eax =3D apicid_core_offset(&topo_info); - *ebx =3D topo_info.threads_per_core; - *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_SMT << 8; - break; - case 1: - *eax =3D apicid_die_offset(&topo_info); - *ebx =3D topo_info.cores_per_die * topo_info.threads_per_core; - *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_CORE << 8; - break; - case 2: - *eax =3D apicid_pkg_offset(&topo_info); - *ebx =3D threads_per_pkg; - *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_DIE << 8; - break; - default: - *eax =3D 0; - *ebx =3D 0; - *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_INVALID << 8; - } - assert(!(*eax & ~0x1f)); - *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ + encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx); break; case 0xD: { /* Processor Extended State */ --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Thu, 23 May 2024 08:01:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEWgFAkvYU8dlsswJzloFiOybHVreP+VN+veAttkceMPmIpl/XfkHLOvMSmQyTiu2rIyJPjGw== X-Received: by 2002:a17:906:6a02:b0:a59:c319:f1e0 with SMTP id a640c23a62f3a-a6228171b37mr385429166b.75.1716476470212; Thu, 23 May 2024 08:01:10 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Yongwei Ma , Zhuocheng Ding , Babu Moger Subject: [PULL 13/23] i386: Introduce module level cpu topology to CPUX86State Date: Thu, 23 May 2024 17:00:26 +0200 Message-ID: <20240523150036.1050011-14-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476576245100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Intel CPUs implement module level on hybrid client products (e.g., ADL-N, MTL, etc) and E-core server products. A module contains a set of cores that share certain resources (in current products, the resource usually includes L2 cache, as well as module scoped features and MSRs). Module level support is the prerequisite for L2 cache topology on module level. With module level, we can implement the Guest's CPU topology and future cache topology to be consistent with the Host's on Intel hybrid client/E-core server platforms. Tested-by: Yongwei Ma Co-developed-by: Zhuocheng Ding Signed-off-by: Zhuocheng Ding Signed-off-by: Zhao Liu Tested-by: Babu Moger Message-ID: <20240424154929.1487382-13-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 3 +++ hw/i386/x86-common.c | 5 +++++ target/i386/cpu.c | 1 + 3 files changed, 9 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8c83900202d..e79293158a0 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1898,6 +1898,9 @@ typedef struct CPUArchState { /* Number of dies within this CPU package. */ unsigned nr_dies; =20 + /* Number of modules within one die. */ + unsigned nr_modules; + /* Bitmap of available CPU topology levels for this CPU. */ DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX); } CPUX86State; diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 7d4f9b20f23..994f8424889 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -271,6 +271,11 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 init_topo_info(&topo_info, x86ms); =20 + if (ms->smp.modules > 1) { + env->nr_modules =3D ms->smp.modules; + /* TODO: Expose module level in CPUID[0x1F]. */ + } + if (ms->smp.dies > 1) { env->nr_dies =3D ms->smp.dies; set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f95d539eeff..eb1642c253c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7887,6 +7887,7 @@ static void x86_cpu_init_default_topo(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; =20 + env->nr_modules =3D 1; env->nr_dies =3D 1; =20 /* SMT, core and package levels are set by default. */ --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1716476813; cv=none; d=zohomail.com; s=zohoarc; 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Thu, 23 May 2024 08:01:13 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Yongwei Ma , Zhuocheng Ding , Babu Moger Subject: [PULL 14/23] i386: Support modules_per_die in X86CPUTopoInfo Date: Thu, 23 May 2024 17:00:27 +0200 Message-ID: <20240523150036.1050011-15-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476815643100006 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Support module level in i386 cpu topology structure "X86CPUTopoInfo". Since x86 does not yet support the "modules" parameter in "-smp", X86CPUTopoInfo.modules_per_die is currently always 1. Therefore, the module level width in APIC ID, which can be calculated by "apicid_bitwidth_for_count(topo_info->modules_per_die)", is always 0 for now, so we can directly add APIC ID related helpers to support module level parsing. In addition, update topology structure in test-x86-topo.c. Tested-by: Yongwei Ma Co-developed-by: Zhuocheng Ding Signed-off-by: Zhuocheng Ding Signed-off-by: Zhao Liu Tested-by: Babu Moger Message-ID: <20240424154929.1487382-14-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- include/hw/i386/topology.h | 22 +++++++++++++++---- hw/i386/x86.c | 9 +++++++- target/i386/cpu.c | 13 ++++++----- tests/unit/test-x86-topo.c | 45 ++++++++++++++++++++------------------ 4 files changed, 58 insertions(+), 31 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index befeb92b0b1..7622d806932 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -56,7 +56,8 @@ typedef struct X86CPUTopoIDs { =20 typedef struct X86CPUTopoInfo { unsigned dies_per_pkg; - unsigned cores_per_die; + unsigned modules_per_die; + unsigned cores_per_module; unsigned threads_per_core; } X86CPUTopoInfo; =20 @@ -92,7 +93,13 @@ static inline unsigned apicid_smt_width(X86CPUTopoInfo *= topo_info) /* Bit width of the Core_ID field */ static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(topo_info->cores_per_die); + return apicid_bitwidth_for_count(topo_info->cores_per_module); +} + +/* Bit width of the Module_ID field */ +static inline unsigned apicid_module_width(X86CPUTopoInfo *topo_info) +{ + return apicid_bitwidth_for_count(topo_info->modules_per_die); } =20 /* Bit width of the Die_ID field */ @@ -107,10 +114,16 @@ static inline unsigned apicid_core_offset(X86CPUTopoI= nfo *topo_info) return apicid_smt_width(topo_info); } =20 +/* Bit offset of the Module_ID field */ +static inline unsigned apicid_module_offset(X86CPUTopoInfo *topo_info) +{ + return apicid_core_offset(topo_info) + apicid_core_width(topo_info); +} + /* Bit offset of the Die_ID field */ static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info) { - return apicid_core_offset(topo_info) + apicid_core_width(topo_info); + return apicid_module_offset(topo_info) + apicid_module_width(topo_info= ); } =20 /* Bit offset of the Pkg_ID (socket ID) field */ @@ -142,7 +155,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo= *topo_info, X86CPUTopoIDs *topo_ids) { unsigned nr_dies =3D topo_info->dies_per_pkg; - unsigned nr_cores =3D topo_info->cores_per_die; + unsigned nr_cores =3D topo_info->cores_per_module * + topo_info->modules_per_die; unsigned nr_threads =3D topo_info->threads_per_core; =20 topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 0b5cc599566..d5d668e814d 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -45,7 +45,14 @@ void init_topo_info(X86CPUTopoInfo *topo_info, MachineState *ms =3D MACHINE(x86ms); =20 topo_info->dies_per_pkg =3D ms->smp.dies; - topo_info->cores_per_die =3D ms->smp.cores; + /* + * Though smp.modules means the number of modules in one cluster, + * i386 doesn't support cluster level so that the smp.clusters + * always defaults to 1, therefore using smp.modules directly is + * fine here. + */ + topo_info->modules_per_die =3D ms->smp.modules; + topo_info->cores_per_module =3D ms->smp.cores; topo_info->threads_per_core =3D ms->smp.threads; } =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index eb1642c253c..92aa4498551 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -278,10 +278,11 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoI= nfo *topo_info, case CPU_TOPO_LEVEL_CORE: return topo_info->threads_per_core; case CPU_TOPO_LEVEL_DIE: - return topo_info->threads_per_core * topo_info->cores_per_die; + return topo_info->threads_per_core * topo_info->cores_per_module * + topo_info->modules_per_die; case CPU_TOPO_LEVEL_PACKAGE: - return topo_info->threads_per_core * topo_info->cores_per_die * - topo_info->dies_per_pkg; + return topo_info->threads_per_core * topo_info->cores_per_module * + topo_info->modules_per_die * topo_info->dies_per_pkg; default: g_assert_not_reached(); } @@ -6278,10 +6279,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, uint32_t threads_per_pkg; =20 topo_info.dies_per_pkg =3D env->nr_dies; - topo_info.cores_per_die =3D cs->nr_cores / env->nr_dies; + topo_info.modules_per_die =3D env->nr_modules; + topo_info.cores_per_module =3D cs->nr_cores / env->nr_dies / env->nr_m= odules; topo_info.threads_per_core =3D cs->nr_threads; =20 - cores_per_pkg =3D topo_info.cores_per_die * topo_info.dies_per_pkg; + cores_per_pkg =3D topo_info.cores_per_module * topo_info.modules_per_d= ie * + topo_info.dies_per_pkg; threads_per_pkg =3D cores_per_pkg * topo_info.threads_per_core; =20 /* Calculate & apply limits for different index ranges */ diff --git a/tests/unit/test-x86-topo.c b/tests/unit/test-x86-topo.c index 2b104f86d7c..f21b8a5d95c 100644 --- a/tests/unit/test-x86-topo.c +++ b/tests/unit/test-x86-topo.c @@ -30,13 +30,16 @@ static void test_topo_bits(void) { X86CPUTopoInfo topo_info =3D {0}; =20 - /* simple tests for 1 thread per core, 1 core per die, 1 die per packa= ge */ - topo_info =3D (X86CPUTopoInfo) {1, 1, 1}; + /* + * simple tests for 1 thread per core, 1 core per module, + * 1 module per die, 1 die per package + */ + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); =20 - topo_info =3D (X86CPUTopoInfo) {1, 1, 1}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), =3D=3D, 0); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), =3D=3D, 1); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), =3D=3D, 2); @@ -45,39 +48,39 @@ static void test_topo_bits(void) =20 /* Test field width calculation for multiple values */ - topo_info =3D (X86CPUTopoInfo) {1, 1, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 2}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 1); - topo_info =3D (X86CPUTopoInfo) {1, 1, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 3}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); - topo_info =3D (X86CPUTopoInfo) {1, 1, 4}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 4}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); =20 - topo_info =3D (X86CPUTopoInfo) {1, 1, 14}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 14}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); - topo_info =3D (X86CPUTopoInfo) {1, 1, 15}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 15}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); - topo_info =3D (X86CPUTopoInfo) {1, 1, 16}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 16}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); - topo_info =3D (X86CPUTopoInfo) {1, 1, 17}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 17}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 5); =20 =20 - topo_info =3D (X86CPUTopoInfo) {1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 30, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); - topo_info =3D (X86CPUTopoInfo) {1, 31, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 31, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); - topo_info =3D (X86CPUTopoInfo) {1, 32, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 32, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); - topo_info =3D (X86CPUTopoInfo) {1, 33, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 33, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 6); =20 - topo_info =3D (X86CPUTopoInfo) {1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); - topo_info =3D (X86CPUTopoInfo) {2, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {2, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 1); - topo_info =3D (X86CPUTopoInfo) {3, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {3, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); - topo_info =3D (X86CPUTopoInfo) {4, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {4, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); =20 /* build a weird topology and see if IDs are calculated correctly @@ -85,18 +88,18 @@ static void test_topo_bits(void) =20 /* This will use 2 bits for thread ID and 3 bits for core ID */ - topo_info =3D (X86CPUTopoInfo) {1, 6, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); g_assert_cmpuint(apicid_core_offset(&topo_info), =3D=3D, 2); g_assert_cmpuint(apicid_die_offset(&topo_info), =3D=3D, 5); g_assert_cmpuint(apicid_pkg_offset(&topo_info), =3D=3D, 5); =20 - topo_info =3D (X86CPUTopoInfo) {1, 6, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), =3D=3D, 0); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), =3D=3D, 1); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), =3D=3D, 2); =20 - topo_info =3D (X86CPUTopoInfo) {1, 6, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 0), =3D= =3D, (1 << 2) | 0); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 1), =3D= =3D, --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1716476652; cv=none; d=zohomail.com; s=zohoarc; b=RFe/ImMiDHRsEzvDNyyzEL/DwWh9WkiAd3OH4E34j+6Fkiul/upKKK653DtQzTPHXwvY3St4khnBQ17JIxTFmwxu1EWfDHTTI/0KvJptTMRZ/eJAcGqivuglWuSqg/2ZLh1LX8ab8aiUJnTvAiaq+SSQlOu21nuurwp6J5jEp4A= ARC-Message-Signature: i=1; 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476654720100004 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix erroneous smp_num_siblings on Intel Hybrid platforms") is able to handle platforms with Module level enumerated via CPUID.1F. Expose the module level in CPUID[0x1F] if the machine has more than 1 modules. Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Tested-by: Babu Moger Message-ID: <20240424154929.1487382-15-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- include/hw/i386/topology.h | 6 ++++-- target/i386/cpu.h | 1 + hw/i386/x86-common.c | 2 +- target/i386/cpu.c | 6 ++++++ 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 7622d806932..ea871045779 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -71,6 +71,7 @@ enum CPUTopoLevel { CPU_TOPO_LEVEL_INVALID, CPU_TOPO_LEVEL_SMT, CPU_TOPO_LEVEL_CORE, + CPU_TOPO_LEVEL_MODULE, CPU_TOPO_LEVEL_DIE, CPU_TOPO_LEVEL_PACKAGE, CPU_TOPO_LEVEL_MAX, @@ -198,11 +199,12 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CP= UTopoInfo *topo_info, } =20 /* - * Check whether there's extended topology level (die)? + * Check whether there's extended topology level (module or die)? */ static inline bool x86_has_extended_topo(unsigned long *topo_bitmap) { - return test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap); + return test_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap) || + test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap); } =20 #endif /* HW_I386_TOPOLOGY_H */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e79293158a0..196b068614c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1024,6 +1024,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWo= rd w, #define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID #define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT #define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE +#define CPUID_1F_ECX_TOPO_LEVEL_MODULE 3 #define CPUID_1F_ECX_TOPO_LEVEL_DIE 5 =20 /* MSR Feature Bits */ diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 994f8424889..34dfa894879 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -273,7 +273,7 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 if (ms->smp.modules > 1) { env->nr_modules =3D ms->smp.modules; - /* TODO: Expose module level in CPUID[0x1F]. */ + set_bit(CPU_TOPO_LEVEL_MODULE, env->avail_cpu_topo); } =20 if (ms->smp.dies > 1) { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 92aa4498551..4aea6e3dd24 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -277,6 +277,8 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInf= o *topo_info, return 1; case CPU_TOPO_LEVEL_CORE: return topo_info->threads_per_core; + case CPU_TOPO_LEVEL_MODULE: + return topo_info->threads_per_core * topo_info->cores_per_module; case CPU_TOPO_LEVEL_DIE: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die; @@ -297,6 +299,8 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoI= nfo *topo_info, return 0; case CPU_TOPO_LEVEL_CORE: return apicid_core_offset(topo_info); + case CPU_TOPO_LEVEL_MODULE: + return apicid_module_offset(topo_info); case CPU_TOPO_LEVEL_DIE: return apicid_die_offset(topo_info); case CPU_TOPO_LEVEL_PACKAGE: @@ -316,6 +320,8 @@ static uint32_t cpuid1f_topo_type(enum CPUTopoLevel top= o_level) return CPUID_1F_ECX_TOPO_LEVEL_SMT; case CPU_TOPO_LEVEL_CORE: return CPUID_1F_ECX_TOPO_LEVEL_CORE; + case CPU_TOPO_LEVEL_MODULE: + return CPUID_1F_ECX_TOPO_LEVEL_MODULE; case CPU_TOPO_LEVEL_DIE: return CPUID_1F_ECX_TOPO_LEVEL_DIE; default: --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1716476770; cv=none; d=zohomail.com; s=zohoarc; b=QavbIfFxO0rO3cqlaMQzI1Hy3Bysv4t3hNUqOltb4bedhesAl9W1o5gIO314uCLeU6pekf0Sld50rEeILQ68QnDdsGCSlw0dFpaKVBZjdyTg9sDlZ737YOSZBSVLCqffjMAZggV5M1wHh/cnRo00pEKYPpI0DeBbf5XrdPYL8f0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716476770; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 23 May 2024 08:01:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGB7l5ddttGfdZZFMB7ES5jLOE9IGSW7P1pwZdy0+1zazMMtF62Hn1Q98ELBTRnatIt6qDVLw== X-Received: by 2002:a17:906:36ce:b0:a55:8f2a:950d with SMTP id a640c23a62f3a-a622806bb8bmr404527166b.16.1716476478458; Thu, 23 May 2024 08:01:18 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Yongwei Ma , Zhuocheng Ding , Babu Moger Subject: [PULL 16/23] i386: Support module_id in X86CPUTopoIDs Date: Thu, 23 May 2024 17:00:29 +0200 Message-ID: <20240523150036.1050011-17-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476771384100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Add module_id member in X86CPUTopoIDs. module_id can be parsed from APIC ID, so also update APIC ID parsing rule to support module level. With this support, the conversions with module level between X86CPUTopoIDs, X86CPUTopoInfo and APIC ID are completed. module_id can be also generated from cpu topology, and before i386 supports "modules" in smp, the default "modules per die" (modules * clusters) is only 1, thus the module_id generated in this way is 0, so that it will not conflict with the module_id generated by APIC ID. Tested-by: Yongwei Ma Signed-off-by: Zhuocheng Ding Co-developed-by: Zhuocheng Ding Signed-off-by: Zhao Liu Tested-by: Babu Moger Message-ID: <20240424154929.1487382-16-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- include/hw/i386/topology.h | 17 +++++++++++++---- hw/i386/x86-common.c | 27 +++++++++++++++++---------- hw/i386/x86.c | 4 ++++ 3 files changed, 34 insertions(+), 14 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index ea871045779..dff49fce115 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -50,6 +50,7 @@ typedef uint32_t apic_id_t; typedef struct X86CPUTopoIDs { unsigned pkg_id; unsigned die_id; + unsigned module_id; unsigned core_id; unsigned smt_id; } X86CPUTopoIDs; @@ -143,6 +144,7 @@ static inline apic_id_t x86_apicid_from_topo_ids(X86CPU= TopoInfo *topo_info, { return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) | (topo_ids->die_id << apicid_die_offset(topo_info)) | + (topo_ids->module_id << apicid_module_offset(topo_info)) | (topo_ids->core_id << apicid_core_offset(topo_info)) | topo_ids->smt_id; } @@ -156,12 +158,16 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoIn= fo *topo_info, X86CPUTopoIDs *topo_ids) { unsigned nr_dies =3D topo_info->dies_per_pkg; - unsigned nr_cores =3D topo_info->cores_per_module * - topo_info->modules_per_die; + unsigned nr_modules =3D topo_info->modules_per_die; + unsigned nr_cores =3D topo_info->cores_per_module; unsigned nr_threads =3D topo_info->threads_per_core; =20 - topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); - topo_ids->die_id =3D cpu_index / (nr_cores * nr_threads) % nr_dies; + topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_modules * + nr_cores * nr_threads); + topo_ids->die_id =3D cpu_index / (nr_modules * nr_cores * + nr_threads) % nr_dies; + topo_ids->module_id =3D cpu_index / (nr_cores * nr_threads) % + nr_modules; topo_ids->core_id =3D cpu_index / nr_threads % nr_cores; topo_ids->smt_id =3D cpu_index % nr_threads; } @@ -179,6 +185,9 @@ static inline void x86_topo_ids_from_apicid(apic_id_t a= picid, topo_ids->core_id =3D (apicid >> apicid_core_offset(topo_info)) & ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); + topo_ids->module_id =3D + (apicid >> apicid_module_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_module_width(topo_info)); topo_ids->die_id =3D (apicid >> apicid_die_offset(topo_info)) & ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 34dfa894879..4d27279901c 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -283,12 +283,9 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 /* * If APIC ID is not set, - * set it based on socket/die/core/thread properties. + * set it based on socket/die/module/core/thread properties. */ if (cpu->apic_id =3D=3D UNASSIGNED_APIC_ID) { - int max_socket =3D (ms->smp.max_cpus - 1) / - smp_threads / smp_cores / ms->smp.dies; - /* * die-id was optional in QEMU 4.0 and older, so keep it optional * if there's only one die per socket. @@ -300,9 +297,9 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, if (cpu->socket_id < 0) { error_setg(errp, "CPU socket-id is not set"); return; - } else if (cpu->socket_id > max_socket) { + } else if (cpu->socket_id > ms->smp.sockets - 1) { error_setg(errp, "Invalid CPU socket-id: %u must be in range 0= :%u", - cpu->socket_id, max_socket); + cpu->socket_id, ms->smp.sockets - 1); return; } if (cpu->die_id < 0) { @@ -334,17 +331,27 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.die_id =3D cpu->die_id; topo_ids.core_id =3D cpu->core_id; topo_ids.smt_id =3D cpu->thread_id; + + /* + * TODO: This is the temporary initialization for topo_ids.module_= id to + * avoid "maybe-uninitialized" compilation errors. Will remove when + * X86CPU supports module_id. + */ + topo_ids.module_id =3D 0; + cpu->apic_id =3D x86_apicid_from_topo_ids(&topo_info, &topo_ids); } =20 cpu_slot =3D x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); if (!cpu_slot) { x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + error_setg(errp, - "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" - " APIC ID %" PRIu32 ", valid index range 0:%d", - topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.s= mt_id, - cpu->apic_id, ms->possible_cpus->len - 1); + "Invalid CPU [socket: %u, die: %u, module: %u, core: %u, threa= d: %u]" + " with APIC ID %" PRIu32 ", valid index range 0:%d", + topo_ids.pkg_id, topo_ids.die_id, topo_ids.module_id, + topo_ids.core_id, topo_ids.smt_id, cpu->apic_id, + ms->possible_cpus->len - 1); return; } =20 diff --git a/hw/i386/x86.c b/hw/i386/x86.c index d5d668e814d..a4aa8e08109 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -135,6 +135,10 @@ static const CPUArchIdList *x86_possible_cpu_arch_ids(= MachineState *ms) ms->possible_cpus->cpus[i].props.has_die_id =3D true; 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Thu, 23 May 2024 08:01:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFJXKVwSFB9axrqTFDAmqI+yuO8z6TV9uALWcFZpU1QN5b33tY7urW+LzJWkG2d4JKYfP0u8g== X-Received: by 2002:a17:906:b46:b0:a62:c5f:e34a with SMTP id a640c23a62f3a-a62280a275cmr330833966b.39.1716476481390; Thu, 23 May 2024 08:01:21 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Yongwei Ma , Zhuocheng Ding , Babu Moger Subject: [PULL 17/23] i386/cpu: Introduce module-id to X86CPU Date: Thu, 23 May 2024 17:00:30 +0200 Message-ID: <20240523150036.1050011-18-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476807486100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Introduce module-id to be consistent with the module-id field in CpuInstanceProperties. Following the legacy smp check rules, also add the module_id validity into x86_cpu_pre_plug(). Tested-by: Yongwei Ma Co-developed-by: Zhuocheng Ding Signed-off-by: Zhuocheng Ding Signed-off-by: Zhao Liu Tested-by: Babu Moger Message-ID: <20240424154929.1487382-17-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 1 + hw/i386/x86-common.c | 33 +++++++++++++++++++++++++-------- target/i386/cpu.c | 2 ++ 3 files changed, 28 insertions(+), 8 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 196b068614c..269c30c291b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2064,6 +2064,7 @@ struct ArchCPU { int32_t node_id; /* NUMA node this CPU belongs to */ int32_t socket_id; int32_t die_id; + int32_t module_id; int32_t core_id; int32_t thread_id; =20 diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 4d27279901c..ee9046d9a80 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -294,6 +294,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, cpu->die_id =3D 0; } =20 + /* + * module-id was optional in QEMU 9.0 and older, so keep it option= al + * if there's only one module per die. + */ + if (cpu->module_id < 0 && ms->smp.modules =3D=3D 1) { + cpu->module_id =3D 0; + } + if (cpu->socket_id < 0) { error_setg(errp, "CPU socket-id is not set"); return; @@ -310,6 +318,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, cpu->die_id, ms->smp.dies - 1); return; } + if (cpu->module_id < 0) { + error_setg(errp, "CPU module-id is not set"); + return; + } else if (cpu->module_id > ms->smp.modules - 1) { + error_setg(errp, "Invalid CPU module-id: %u must be in range 0= :%u", + cpu->module_id, ms->smp.modules - 1); + return; + } if (cpu->core_id < 0) { error_setg(errp, "CPU core-id is not set"); return; @@ -329,16 +345,9 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 topo_ids.pkg_id =3D cpu->socket_id; topo_ids.die_id =3D cpu->die_id; + topo_ids.module_id =3D cpu->module_id; topo_ids.core_id =3D cpu->core_id; topo_ids.smt_id =3D cpu->thread_id; - - /* - * TODO: This is the temporary initialization for topo_ids.module_= id to - * avoid "maybe-uninitialized" compilation errors. Will remove when - * X86CPU supports module_id. - */ - topo_ids.module_id =3D 0; - cpu->apic_id =3D x86_apicid_from_topo_ids(&topo_info, &topo_ids); } =20 @@ -383,6 +392,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, } cpu->die_id =3D topo_ids.die_id; =20 + if (cpu->module_id !=3D -1 && cpu->module_id !=3D topo_ids.module_id) { + error_setg(errp, "property module-id: %u doesn't match set apic-id= :" + " 0x%x (module-id: %u)", cpu->module_id, cpu->apic_id, + topo_ids.module_id); + return; + } + cpu->module_id =3D topo_ids.module_id; + if (cpu->core_id !=3D -1 && cpu->core_id !=3D topo_ids.core_id) { error_setg(errp, "property core-id: %u doesn't match set apic-id:" " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4aea6e3dd24..4d811130b1e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8118,12 +8118,14 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), + DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), #else DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), + DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), #endif --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" Subject: [PULL 18/23] tests: Add test case of APIC ID for module level parsing Date: Thu, 23 May 2024 17:00:31 +0200 Message-ID: <20240523150036.1050011-19-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476513885100001 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding After i386 supports module level, it's time to add the test for module level's parsing. Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu Reviewed-by: Yanan Wang Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Message-ID: <20240424154929.1487382-18-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- tests/unit/test-x86-topo.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/tests/unit/test-x86-topo.c b/tests/unit/test-x86-topo.c index f21b8a5d95c..55b731ccae5 100644 --- a/tests/unit/test-x86-topo.c +++ b/tests/unit/test-x86-topo.c @@ -37,6 +37,7 @@ static void test_topo_bits(void) topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 0); + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); =20 topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; @@ -74,13 +75,22 @@ static void test_topo_bits(void) topo_info =3D (X86CPUTopoInfo) {1, 1, 33, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 6); =20 - topo_info =3D (X86CPUTopoInfo) {1, 1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 6, 30, 2}; + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 3); + topo_info =3D (X86CPUTopoInfo) {1, 7, 30, 2}; + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 3); + topo_info =3D (X86CPUTopoInfo) {1, 8, 30, 2}; + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 3); + topo_info =3D (X86CPUTopoInfo) {1, 9, 30, 2}; + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 4); + + topo_info =3D (X86CPUTopoInfo) {1, 6, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); - topo_info =3D (X86CPUTopoInfo) {2, 1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {2, 6, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 1); - topo_info =3D (X86CPUTopoInfo) {3, 1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {3, 6, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); - topo_info =3D (X86CPUTopoInfo) {4, 1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {4, 6, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); =20 /* build a weird topology and see if IDs are calculated correctly @@ -91,6 +101,7 @@ static void test_topo_bits(void) topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); g_assert_cmpuint(apicid_core_offset(&topo_info), =3D=3D, 2); + g_assert_cmpuint(apicid_module_offset(&topo_info), =3D=3D, 5); g_assert_cmpuint(apicid_die_offset(&topo_info), =3D=3D, 5); g_assert_cmpuint(apicid_pkg_offset(&topo_info), =3D=3D, 5); =20 --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1716476813; cv=none; d=zohomail.com; s=zohoarc; b=eUL/FbBonTL9Ik8DjzvFaAeQmqZdfbWWteiQk5KCqyGWRuTpVIpr/uWu1DrZ3cIL2ahwyFn7R3Lb8M5g2RanETbSk1JCRoZ5CH+bSk7x8VI8j37zw5d26vv/TzaGOYP6gMN98AIGaVFtHSNaUNF/ku/1AJ6lX2aBZYpKAej5Fyk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716476813; 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Thu, 23 May 2024 08:01:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGbcF3+fXwCypRxfjpnpXkUjfvuUquXjGrPBlxFwUFEA1MK2JR/HBw1JlM9goij8dgyS1SoMQ== X-Received: by 2002:a50:d789:0:b0:578:25c9:b990 with SMTP id 4fb4d7f45d1cf-57832a3a1b2mr5199756a12.20.1716476486788; Thu, 23 May 2024 08:01:26 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Yongwei Ma , Zhuocheng Ding , Babu Moger Subject: [PULL 19/23] hw/i386/pc: Support smp.modules for x86 PC machine Date: Thu, 23 May 2024 17:00:32 +0200 Message-ID: <20240523150036.1050011-20-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476815529100005 Content-Type: text/plain; charset="utf-8" From: Zhao Liu As module-level topology support is added to X86CPU, now we can enable the support for the modules parameter on PC machines. With this support, we can define a 5-level x86 CPU topology with "-smp": -smp cpus=3D*,maxcpus=3D*,sockets=3D*,dies=3D*,modules=3D*,cores=3D*,thread= s=3D*. So, add the 5-level topology example in description of "-smp". Additionally, add the missed drawers and books options in previous example. Tested-by: Yongwei Ma Co-developed-by: Zhuocheng Ding Signed-off-by: Zhuocheng Ding Signed-off-by: Zhao Liu Tested-by: Babu Moger Reviewed-by: Babu Moger Message-ID: <20240424154929.1487382-19-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- hw/i386/pc.c | 1 + qemu-options.hx | 18 ++++++++++-------- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 6126bfdd2a7..7b638da7aaa 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1843,6 +1843,7 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) mc->default_cpu_type =3D TARGET_DEFAULT_CPU_TYPE; mc->nvdimm_supported =3D true; mc->smp_props.dies_supported =3D true; + mc->smp_props.modules_supported =3D true; mc->default_ram_id =3D "pc.ram"; pcmc->default_smbios_ep_type =3D SMBIOS_ENTRY_POINT_TYPE_AUTO; =20 diff --git a/qemu-options.hx b/qemu-options.hx index 4d196603368..8ca7f34ef0c 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -281,7 +281,8 @@ ERST =20 DEF("smp", HAS_ARG, QEMU_OPTION_smp, "-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,drawers=3Ddrawers][,books=3Dbo= oks][,sockets=3Dsockets]\n" - " [,dies=3Ddies][,clusters=3Dclusters][,cores=3Dcores][,= threads=3Dthreads]\n" + " [,dies=3Ddies][,clusters=3Dclusters][,modules=3Dmodule= s][,cores=3Dcores]\n" + " [,threads=3Dthreads]\n" " set the number of initial CPUs to 'n' [default=3D1]\n" " maxcpus=3D maximum number of total CPUs, including\n" " offline CPUs for hotplug, etc\n" @@ -290,7 +291,8 @@ DEF("smp", HAS_ARG, QEMU_OPTION_smp, " sockets=3D number of sockets in one book\n" " dies=3D number of dies in one socket\n" " clusters=3D number of clusters in one die\n" - " cores=3D number of cores in one cluster\n" + " modules=3D number of modules in one cluster\n" + " cores=3D number of cores in one module\n" " threads=3D number of threads in one core\n" "Note: Different machines may have different subsets of the CPU topolo= gy\n" " parameters supported, so the actual meaning of the supported pa= rameters\n" @@ -306,7 +308,7 @@ DEF("smp", HAS_ARG, QEMU_OPTION_smp, " must be set as 1 in the purpose of correct parsing.\n", QEMU_ARCH_ALL) SRST -``-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,sockets=3Dsockets][,dies=3Ddies][= ,clusters=3Dclusters][,cores=3Dcores][,threads=3Dthreads]`` +``-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,drawers=3Ddrawers][,books=3Dbooks= ][,sockets=3Dsockets][,dies=3Ddies][,clusters=3Dclusters][,modules=3Dmodule= s][,cores=3Dcores][,threads=3Dthreads]`` Simulate a SMP system with '\ ``n``\ ' CPUs initially present on the machine type board. On boards supporting CPU hotplug, the optional '\ ``maxcpus``\ ' parameter can be set to enable further CPUs to be @@ -345,14 +347,14 @@ SRST -smp 8,sockets=3D2,cores=3D2,threads=3D2,maxcpus=3D8 =20 The following sub-option defines a CPU topology hierarchy (2 sockets - totally on the machine, 2 dies per socket, 2 cores per die, 2 threads - per core) for PC machines which support sockets/dies/cores/threads. - Some members of the option can be omitted but their values will be - automatically computed: + totally on the machine, 2 dies per socket, 2 modules per die, 2 cores = per + module, 2 threads per core) for PC machines which support sockets/dies + /modules/cores/threads. Some members of the option can be omitted but + their values will be automatically computed: =20 :: =20 - -smp 16,sockets=3D2,dies=3D2,cores=3D2,threads=3D2,maxcpus=3D16 + -smp 32,sockets=3D2,dies=3D2,modules=3D2,cores=3D2,threads=3D2,max= cpus=3D32 =20 The following sub-option defines a CPU topology hierarchy (2 sockets totally on the machine, 2 clusters per socket, 2 cores per cluster, --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1716476517; cv=none; d=zohomail.com; s=zohoarc; b=UIer2OMXE3Kv6mXbCBkANZBZN+SklfxvhQ8JncYj6jiWY6ecMIK9mlxUIfWAw0fGHpxt0AIafe9NXlyf4Ds6uxmcjoY3YYiie0KxFRvQ2zjDyvFzp2t79AH5MKoGRYDSz9WtXhjJOoBDFq8KTjia2Jds2Mt1B4ejY3HsXtm7RQ8= ARC-Message-Signature: i=1; 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Tsirkin" Subject: [PULL 20/23] i386: Add cache topology info in CPUCacheInfo Date: Thu, 23 May 2024 17:00:33 +0200 Message-ID: <20240523150036.1050011-21-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476517894100009 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Currently, by default, the cache topology is encoded as: 1. i/d cache is shared in one core. 2. L2 cache is shared in one core. 3. L3 cache is shared in one die. This default general setting has caused a misunderstanding, that is, the cache topology is completely equated with a specific cpu topology, such as the connection between L2 cache and core level, and the connection between L3 cache and die level. In fact, the settings of these topologies depend on the specific platform and are not static. For example, on Alder Lake-P, every four Atom cores share the same L2 cache. Thus, we should explicitly define the corresponding cache topology for different cache models to increase scalability. Except legacy_l2_cache_cpuid2 (its default topo level is CPU_TOPO_LEVEL_UNKNOW), explicitly set the corresponding topology level for all other cache models. In order to be compatible with the existing cache topology, set the CPU_TOPO_LEVEL_CORE level for the i/d cache, set the CPU_TOPO_LEVEL_CORE level for L2 cache, and set the CPU_TOPO_LEVEL_DIE level for L3 cache. The field for CPUID[4].EAX[bits 25:14] or CPUID[0x8000001D].EAX[bits 25:14] will be set based on CPUCacheInfo.share_level. Signed-off-by: Zhao Liu Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Message-ID: <20240424154929.1487382-20-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 7 +++++++ target/i386/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 269c30c291b..9f152812b60 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1589,6 +1589,13 @@ typedef struct CPUCacheInfo { * address bits. CPUID[4].EDX[bit 2]. */ bool complex_indexing; + + /* + * Cache Topology. The level that cache is shared in. + * Used to encode CPUID[4].EAX[bits 25:14] or + * CPUID[0x8000001D].EAX[bits 25:14]. + */ + enum CPUTopoLevel share_level; } CPUCacheInfo; =20 =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4d811130b1e..656b65ad333 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -552,6 +552,7 @@ static CPUCacheInfo legacy_l1d_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -566,6 +567,7 @@ static CPUCacheInfo legacy_l1d_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /* L1 instruction cache: */ @@ -579,6 +581,7 @@ static CPUCacheInfo legacy_l1i_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -593,6 +596,7 @@ static CPUCacheInfo legacy_l1i_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /* Level 2 unified cache: */ @@ -606,6 +610,7 @@ static CPUCacheInfo legacy_l2_cache =3D { .sets =3D 4096, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ @@ -615,6 +620,7 @@ static CPUCacheInfo legacy_l2_cache_cpuid2 =3D { .size =3D 2 * MiB, .line_size =3D 64, .associativity =3D 8, + .share_level =3D CPU_TOPO_LEVEL_INVALID, }; =20 =20 @@ -628,6 +634,7 @@ static CPUCacheInfo legacy_l2_cache_amd =3D { .associativity =3D 16, .sets =3D 512, .partitions =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /* Level 3 unified cache: */ @@ -643,6 +650,7 @@ static CPUCacheInfo legacy_l3_cache =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }; =20 /* TLB definitions: */ @@ -1941,6 +1949,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -1953,6 +1962,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1963,6 +1973,7 @@ static const CPUCaches epyc_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1976,6 +1987,7 @@ static const CPUCaches epyc_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -1991,6 +2003,7 @@ static CPUCaches epyc_v4_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2003,6 +2016,7 @@ static CPUCaches epyc_v4_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2013,6 +2027,7 @@ static CPUCaches epyc_v4_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2026,6 +2041,7 @@ static CPUCaches epyc_v4_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2041,6 +2057,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2053,6 +2070,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2063,6 +2081,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2076,6 +2095,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2091,6 +2111,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2103,6 +2124,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2113,6 +2135,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2126,6 +2149,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2141,6 +2165,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2153,6 +2178,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2163,6 +2189,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2176,6 +2203,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2191,6 +2219,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2203,6 +2232,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2213,6 +2243,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2226,6 +2257,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2241,6 +2273,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2253,6 +2286,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2263,6 +2297,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .partitions =3D 1, .sets =3D 2048, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2276,6 +2311,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; 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Thu, 23 May 2024 08:01:30 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHMVQtw3Pw6vNCLtFeKbn7/hXyQnL0jRzYNavVWySRmMackuAl76fV7AhEGoDt9jzxfn9ogzg== X-Received: by 2002:a17:906:b844:b0:a5a:6686:ff9 with SMTP id a640c23a62f3a-a62281723ccmr273246366b.77.1716476490403; Thu, 23 May 2024 08:01:30 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Yongwei Ma , Babu Moger Subject: [PULL 21/23] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4] Date: Thu, 23 May 2024 17:00:34 +0200 Message-ID: <20240523150036.1050011-22-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476596409100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu CPUID[4].EAX[bits 25:14] is used to represent the cache topology for Intel CPUs. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[4].EAX[bits 25:14]. And since with the helper max_processor_ids_for_cache(), the filed CPUID[4].EAX[bits 25:14] (original virable "num_apic_ids") is parsed based on cpu topology levels, which are verified when parsing -smp, it's no need to check this value by "assert(num_apic_ids > 0)" again, so remove this assert(). Additionally, wrap the encoding of CPUID[4].EAX[bits 31:26] into a helper to make the code cleaner. Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Tested-by: Babu Moger Message-ID: <20240424154929.1487382-21-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 5 +++ target/i386/cpu.c | 94 +++++++++++++++++++++++++---------------------- 2 files changed, 56 insertions(+), 43 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9f152812b60..c500a69a696 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2011,6 +2011,11 @@ struct ArchCPU { */ bool enable_l3_cache; =20 + /* Compatibility bits for old machine types. + * If true present L1 cache as per-thread, not per-core. + */ + bool l1_cache_per_core; + /* Compatibility bits for old machine types. * If true present the old cache topology information */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 656b65ad333..f91e1500266 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -235,22 +235,53 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *= cache) ((t) =3D=3D UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 0 /* Invalid value */) =20 +static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, + enum CPUTopoLevel share_level) +{ + uint32_t num_ids =3D 0; + + switch (share_level) { + case CPU_TOPO_LEVEL_CORE: + num_ids =3D 1 << apicid_core_offset(topo_info); + break; + case CPU_TOPO_LEVEL_DIE: + num_ids =3D 1 << apicid_die_offset(topo_info); + break; + case CPU_TOPO_LEVEL_PACKAGE: + num_ids =3D 1 << apicid_pkg_offset(topo_info); + break; + default: + /* + * Currently there is no use case for SMT and MODULE, so use + * assert directly to facilitate debugging. + */ + g_assert_not_reached(); + } + + return num_ids - 1; +} + +static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) +{ + uint32_t num_cores =3D 1 << (apicid_pkg_offset(topo_info) - + apicid_core_offset(topo_info)); + return num_cores - 1; +} =20 /* Encode cache info for CPUID[4] */ static void encode_cache_cpuid4(CPUCacheInfo *cache, - int num_apic_ids, int num_cores, + X86CPUTopoInfo *topo_info, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 - assert(num_apic_ids > 0); *eax =3D CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | - ((num_cores - 1) << 26) | - ((num_apic_ids - 1) << 14); + (max_core_ids_in_package(topo_info) << 26) | + (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); =20 assert(cache->line_size > 0); assert(cache->partitions > 0); @@ -6392,18 +6423,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) = << 8) | (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); break; - case 4: { - /* - * CPUID.04H:EAX[bits 25:14]: Maximum number of addressable IDs for - * logical processors sharing this cache. - */ - int addressable_threads_width; - /* - * CPUID.04H:EAX[bits 31:26]: Maximum number of addressable IDs for - * processor cores in the physical package. - */ - int addressable_cores_width; - + case 4: /* cache info: needed for Core compatibility */ if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); @@ -6415,59 +6435,48 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); =20 if (cores_per_pkg > 1) { - addressable_cores_width =3D apicid_pkg_offset(&topo_in= fo) - - apicid_core_offset(&topo_inf= o); - *eax &=3D ~0xFC000000; - *eax |=3D ((1 << addressable_cores_width) - 1) << 26; + *eax |=3D max_core_ids_in_package(&topo_info) << 26; } if (host_vcpus_per_cache > threads_per_pkg) { - /* Share the cache at package level. */ - addressable_threads_width =3D apicid_pkg_offset(&topo_= info); - *eax &=3D ~0x3FFC000; - *eax |=3D ((1 << addressable_threads_width) - 1) << 14; + + /* Share the cache at package level. */ + *eax |=3D max_thread_ids_for_cache(&topo_info, + CPU_TOPO_LEVEL_PACKAGE) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; } else { *eax =3D 0; - addressable_cores_width =3D apicid_pkg_offset(&topo_info) - - apicid_core_offset(&topo_info); =20 switch (count) { case 0: /* L1 dcache info */ - addressable_threads_width =3D cpu->l1_cache_per_core - ? apicid_core_offset(&topo_info) - : 0; encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - (1 << addressable_threads_width), - (1 << addressable_cores_width), + &topo_info, eax, ebx, ecx, edx); + if (!cpu->l1_cache_per_core) { + *eax &=3D ~MAKE_64BIT_MASK(14, 12); + } break; case 1: /* L1 icache info */ - addressable_threads_width =3D cpu->l1_cache_per_core - ? apicid_core_offset(&topo_info) - : 0; encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - (1 << addressable_threads_width), - (1 << addressable_cores_width), + &topo_info, eax, ebx, ecx, edx); + if (!cpu->l1_cache_per_core) { + *eax &=3D ~MAKE_64BIT_MASK(14, 12); + } break; case 2: /* L2 cache info */ - addressable_threads_width =3D apicid_core_offset(&topo_inf= o); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - (1 << addressable_threads_width), - (1 << addressable_cores_width), + &topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ if (cpu->enable_l3_cache) { - addressable_threads_width =3D apicid_die_offset(&topo_= info); encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << addressable_threads_width), - (1 << addressable_cores_width), + &topo_info, eax, ebx, ecx, edx); break; } @@ -6478,7 +6487,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, } } break; 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Thu, 23 May 2024 08:01:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFWUvHz/WWG9n92xS9THX5XlIQgWnlW34CNhdGutSmy/oCptKLRru/5YxvHBMfmdMV5Q/2SjA== X-Received: by 2002:ac2:4831:0:b0:51d:a87e:27ec with SMTP id 2adb3069b0e04-526bd6935camr3149288e87.9.1716476492704; Thu, 23 May 2024 08:01:32 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Yongwei Ma , Babu Moger Subject: [PULL 22/23] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] Date: Thu, 23 May 2024 17:00:35 +0200 Message-ID: <20240523150036.1050011-23-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476542110100005 Content-Type: text/plain; charset="utf-8" From: Zhao Liu CPUID[0x8000001D].EAX[bits 25:14] NumSharingCache: number of logical processors sharing cache. The number of logical processors sharing this cache is NumSharingCache + 1. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[0x8000001D].EAX[bits 25:14]. Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Tested-by: Babu Moger Reviewed-by: Babu Moger Message-ID: <20240424154929.1487382-22-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f91e1500266..bc2dceb647f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -478,20 +478,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t num_sharing_cache; assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 *eax =3D CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); - - /* L3 is shared among multiple cores */ - if (cache->level =3D=3D 3) { - num_sharing_cache =3D 1 << apicid_die_offset(topo_info); - } else { - num_sharing_cache =3D 1 << apicid_core_offset(topo_info); - } - *eax |=3D (num_sharing_cache - 1) << 14; + *eax |=3D max_thread_ids_for_cache(topo_info, cache->share_level) << 1= 4; =20 assert(cache->line_size > 0); assert(cache->partitions > 0); --=20 2.45.1 From nobody Mon Nov 25 07:42:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1716476654; cv=none; d=zohomail.com; s=zohoarc; b=ZavK2sq4yutWqDdUFd165UKawMdRpTqZHTBSLPiLTEIheyVCHuMrAaEsUU5rrNFxGWheavrKAIGkaKTZaUHGTZ/glqm+YX/sSUerP2p3v/fk0GW0QWVlIcbGLoO1QMhfe2UH/SciU0Lvdf+VUu5etyD0UmixisCLDXeylm4Jbwc= ARC-Message-Signature: i=1; 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helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476654712100003 From: donsheng This bug fix addresses the incorrect return value of kvm_hv_handle_exit for KVM_EXIT_HYPERV_SYNIC, which should be EXCP_INTERRUPT. Handling of KVM_EXIT_HYPERV_SYNIC in QEMU needs to be synchronous. This means that async_synic_update should run in the current QEMU vCPU thread before returning to KVM, returning EXCP_INTERRUPT to guarantee this. Returning 0 can cause async_synic_update to run asynchronously. One problem (kvm-unit-tests's hyperv_synic test fails with timeout error) caused by this bug: When a guest VM writes to the HV_X64_MSR_SCONTROL MSR to enable Hyper-V Syn= IC, a VM exit is triggered and processed by the kvm_hv_handle_exit function of = the QEMU vCPU. This function then calls the async_synic_update function to set synic->sctl_enabled to true. A true value of synic->sctl_enabled is required before creating SINT routes using the hyperv_sint_route_new() function. If kvm_hv_handle_exit returns 0 for KVM_EXIT_HYPERV_SYNIC, the current QEMU vCPU thread may return to KVM and enter the guest VM before running async_synic_update. In such case, the hyperv_synic test=E2=80=99s subsequen= t call to synic_ctl(HV_TEST_DEV_SINT_ROUTE_CREATE, ...) immediately after writing to HV_X64_MSR_SCONTROL can cause QEMU=E2=80=99s hyperv_sint_route_new() functi= on to return prematurely (because synic->sctl_enabled is false). If the SINT route is not created successfully, the SINT interrupt will not = be fired, resulting in a timeout error in the hyperv_synic test. Fixes: 267e071bd6d6 (=E2=80=9Chyperv: make overlay pages for SynIC=E2=80=9D) Suggested-by: Chao Gao Signed-off-by: Dongsheng Zhang Message-ID: <20240521200114.11588-1-dongsheng.x.zhang@intel.com> Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini --- target/i386/kvm/hyperv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/kvm/hyperv.c b/target/i386/kvm/hyperv.c index f2a3fe650a1..b94f12acc2c 100644 --- a/target/i386/kvm/hyperv.c +++ b/target/i386/kvm/hyperv.c @@ -81,7 +81,7 @@ int kvm_hv_handle_exit(X86CPU *cpu, struct kvm_hyperv_exi= t *exit) */ async_safe_run_on_cpu(CPU(cpu), async_synic_update, RUN_ON_CPU_NUL= L); =20 - return 0; + return EXCP_INTERRUPT; case KVM_EXIT_HYPERV_HCALL: { uint16_t code =3D exit->u.hcall.input & 0xffff; bool fast =3D exit->u.hcall.input & HV_HYPERCALL_FAST; --=20 2.45.1