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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=137.194.2.223; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy4.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1716410482036100002 Content-Type: text/plain; charset="utf-8" The previous implementation for EXTI interrupts only handled "configurable" interrupts, like those originating from STM32L4x5 SYSCFG (the only device currently connected to the EXTI up until now). In order to connect STM32L4x5 USART to the EXTI, this commit adds handling for direct interrupts (interrupts without configurable edge). The implementation of configurable interrupts (interrupts supporting edge selection) was incorrectly expecting alternating input levels : this commits adds a new status field `irq_levels` to actually detect edges. Signed-off-by: In=C3=A8s Varhol --- include/hw/misc/stm32l4x5_exti.h | 2 ++ hw/misc/stm32l4x5_exti.c | 25 ++++++++++++++++++++----- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/include/hw/misc/stm32l4x5_exti.h b/include/hw/misc/stm32l4x5_e= xti.h index 82f75a2417..62f79362f2 100644 --- a/include/hw/misc/stm32l4x5_exti.h +++ b/include/hw/misc/stm32l4x5_exti.h @@ -45,6 +45,8 @@ struct Stm32l4x5ExtiState { uint32_t swier[EXTI_NUM_REGISTER]; uint32_t pr[EXTI_NUM_REGISTER]; =20 + /* used for edge detection */ + uint32_t irq_levels[EXTI_NUM_REGISTER]; qemu_irq irq[EXTI_NUM_LINES]; }; =20 diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c index eebefc6cd3..bdc3dc10d6 100644 --- a/hw/misc/stm32l4x5_exti.c +++ b/hw/misc/stm32l4x5_exti.c @@ -87,6 +87,7 @@ static void stm32l4x5_exti_reset_hold(Object *obj, ResetT= ype type) s->ftsr[bank] =3D 0x00000000; s->swier[bank] =3D 0x00000000; s->pr[bank] =3D 0x00000000; + s->irq_levels[bank] =3D 0x00000000; } } =20 @@ -106,17 +107,30 @@ static void stm32l4x5_exti_set_irq(void *opaque, int = irq, int level) return; } =20 + /* In case of a direct line interrupt */ + if (extract32(exti_romask[bank], irq, 1)) { + qemu_set_irq(s->irq[oirq], level); + return; + } + + /* In case of a configurable interrupt */ if (((1 << irq) & s->rtsr[bank]) && level) { /* Rising Edge */ - s->pr[bank] |=3D 1 << irq; - qemu_irq_pulse(s->irq[oirq]); + if (!extract32(s->irq_levels[bank], irq, 1)) { + s->pr[bank] |=3D 1 << irq; + qemu_irq_pulse(s->irq[oirq]); + } + s->irq_levels[bank] |=3D 1 << irq; } else if (((1 << irq) & s->ftsr[bank]) && !level) { /* Falling Edge */ - s->pr[bank] |=3D 1 << irq; - qemu_irq_pulse(s->irq[oirq]); + if (extract32(s->irq_levels[bank], irq, 1)) { + s->pr[bank] |=3D 1 << irq; + qemu_irq_pulse(s->irq[oirq]); + } + s->irq_levels[bank] &=3D ~(1 << irq); } /* - * In the following situations : + * In the following situations (for configurable interrupts) : * - falling edge but rising trigger selected * - rising edge but falling trigger selected * - no trigger selected @@ -262,6 +276,7 @@ static const VMStateDescription vmstate_stm32l4x5_exti = =3D { VMSTATE_UINT32_ARRAY(ftsr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), VMSTATE_UINT32_ARRAY(swier, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), VMSTATE_UINT32_ARRAY(pr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), + VMSTATE_UINT32_ARRAY(irq_levels, Stm32l4x5ExtiState, EXTI_NUM_REGI= STER), VMSTATE_END_OF_LIST() } }; --=20 2.43.2