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Wed, 22 May 2024 22:40:30 +0200 (CEST) Received: from zproxy4.enst.fr ([IPv6:::1]) by localhost (zproxy4.enst.fr [IPv6:::1]) (amavis, port 10032) with ESMTP id 8C8cAXd4xaTx; Wed, 22 May 2024 22:40:29 +0200 (CEST) Received: from localhost (localhost [IPv6:::1]) by zproxy4.enst.fr (Postfix) with ESMTP id D662B2051F; Wed, 22 May 2024 22:40:29 +0200 (CEST) Received: from zproxy4.enst.fr ([IPv6:::1]) by localhost (zproxy4.enst.fr [IPv6:::1]) (amavis, port 10026) with ESMTP id td9S-ob-MxTV; Wed, 22 May 2024 22:40:29 +0200 (CEST) Received: from inesv-Inspiron-3501.enst.fr (unknown [IPv6:2a04:8ec0:0:124::190c]) by zproxy4.enst.fr (Postfix) with ESMTPSA id CF6F420553; Wed, 22 May 2024 22:40:28 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.10.3 zproxy4.enst.fr D662B2051F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telecom-paris.fr; s=A35C7578-1106-11E5-A17F-C303FDDA8F2E; t=1716410429; bh=Hf+j5l5Um/1eDJkNGHCyRdqMWpG6lfb1t4t+e09R38g=; h=From:To:Date:Message-ID:MIME-Version; b=4vxD+AiSuYEQvBRu0CY6MH6oWKGiGxTJb2cNEfowCtKDcj2jhtUAQ63BfJwX4Jre4 1tiXTXfDajzpllfFROqek0DsWHOuESpBsDkGEoiPNMjRslu2et+tVuROO21mE6z0vn mNS/gs1LWUtbSx5Q2KRhYIBlWOGd/GSgqNvsfw18= X-Virus-Scanned: amavis at enst.fr From: =?UTF-8?q?In=C3=A8s=20Varhol?= To: qemu-devel@nongnu.org Cc: Arnaud Minier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, =?UTF-8?q?In=C3=A8s=20Varhol?= , Peter Maydell Subject: [PATCH v2 1/3] hw/misc: In STM32L4x5 EXTI, consolidate 2 constants Date: Wed, 22 May 2024 22:39:38 +0200 Message-ID: <20240522204020.203905-2-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240522204020.203905-1-ines.varhol@telecom-paris.fr> References: <20240522204020.203905-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=137.194.2.223; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy4.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1716410507114100003 Content-Type: text/plain; charset="utf-8" Up until now, the EXTI implementation had 16 inbound GPIOs connected to the 16 outbound GPIOs of STM32L4x5 SYSCFG. The EXTI actually handles 40 lines (namely 5 from STM32L4x5 USART devices which are already implemented in QEMU). In order to connect USART devices to EXTI, this commit consolidates constants `EXTI_NUM_INTERRUPT_OUT_LINES` (40) and `EXTI_NUM_GPIO_EVENT_IN_LINES` (16) into `EXTI_NUM_LINES` (40). Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell --- include/hw/misc/stm32l4x5_exti.h | 4 ++-- hw/misc/stm32l4x5_exti.c | 6 ++---- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/include/hw/misc/stm32l4x5_exti.h b/include/hw/misc/stm32l4x5_e= xti.h index be961d2f01..82f75a2417 100644 --- a/include/hw/misc/stm32l4x5_exti.h +++ b/include/hw/misc/stm32l4x5_exti.h @@ -30,7 +30,7 @@ #define TYPE_STM32L4X5_EXTI "stm32l4x5-exti" OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5ExtiState, STM32L4X5_EXTI) =20 -#define EXTI_NUM_INTERRUPT_OUT_LINES 40 +#define EXTI_NUM_LINES 40 #define EXTI_NUM_REGISTER 2 =20 struct Stm32l4x5ExtiState { @@ -45,7 +45,7 @@ struct Stm32l4x5ExtiState { uint32_t swier[EXTI_NUM_REGISTER]; uint32_t pr[EXTI_NUM_REGISTER]; =20 - qemu_irq irq[EXTI_NUM_INTERRUPT_OUT_LINES]; + qemu_irq irq[EXTI_NUM_LINES]; }; =20 #endif diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c index 495a0004ab..eebefc6cd3 100644 --- a/hw/misc/stm32l4x5_exti.c +++ b/hw/misc/stm32l4x5_exti.c @@ -42,7 +42,6 @@ #define EXTI_SWIER2 0x30 #define EXTI_PR2 0x34 =20 -#define EXTI_NUM_GPIO_EVENT_IN_LINES 16 #define EXTI_MAX_IRQ_PER_BANK 32 #define EXTI_IRQS_BANK0 32 #define EXTI_IRQS_BANK1 8 @@ -241,7 +240,7 @@ static void stm32l4x5_exti_init(Object *obj) { Stm32l4x5ExtiState *s =3D STM32L4X5_EXTI(obj); =20 - for (size_t i =3D 0; i < EXTI_NUM_INTERRUPT_OUT_LINES; i++) { + for (size_t i =3D 0; i < EXTI_NUM_LINES; i++) { sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); } =20 @@ -249,8 +248,7 @@ static void stm32l4x5_exti_init(Object *obj) TYPE_STM32L4X5_EXTI, 0x400); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); =20 - qdev_init_gpio_in(DEVICE(obj), stm32l4x5_exti_set_irq, - EXTI_NUM_GPIO_EVENT_IN_LINES); + qdev_init_gpio_in(DEVICE(obj), stm32l4x5_exti_set_irq, EXTI_NUM_LINES); } =20 static const VMStateDescription vmstate_stm32l4x5_exti =3D { --=20 2.43.2 From nobody Mon Nov 25 07:46:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=telecom-paris.fr ARC-Seal: i=1; a=rsa-sha256; t=1716410479; cv=none; d=zohomail.com; s=zohoarc; b=kQG0TRIE4kqwAjhDL82vMU/pp66sk1n9exizfaImeraKMA++nbx9dAE8k03XcZE4IzAy3Px5SwUUImXZvYgC0JmYcYdiD2FQDF+Y9bxVFg2Nm9ypyjGAThgmFeGblgt/V/ZpEkiqo94flzFl+IKiq2iktXacr9R3VHyMmRD3wCE= ARC-Message-Signature: i=1; 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Wed, 22 May 2024 22:40:30 +0200 (CEST) Received: from inesv-Inspiron-3501.enst.fr (unknown [IPv6:2a04:8ec0:0:124::190c]) by zproxy4.enst.fr (Postfix) with ESMTPSA id E297620528; Wed, 22 May 2024 22:40:29 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.10.3 zproxy4.enst.fr 7F6202051F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telecom-paris.fr; s=A35C7578-1106-11E5-A17F-C303FDDA8F2E; t=1716410430; bh=+tvBKMu0XXeF5GQuHi/fty3M0h+oQiCaDstZEhKD8F4=; h=From:To:Date:Message-ID:MIME-Version; b=n62QhYoSfJFeSwGZHsiwa2BMI7AOVIh3AMfAc5/OXbucFSX/xsyS4pw9/rX76LBu+ QeB4twHZt2ihLwK4BLo1kNR045btABKVuhMMZkvPXfGaP+DmCWmhs/cNxt7rPEijBu hX6aO3T7X9EEpTahnMssn/Lg1lTdiSE/eJAOuGBI= X-Virus-Scanned: amavis at enst.fr From: =?UTF-8?q?In=C3=A8s=20Varhol?= To: qemu-devel@nongnu.org Cc: Arnaud Minier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, =?UTF-8?q?In=C3=A8s=20Varhol?= , Peter Maydell Subject: [PATCH v2 2/3] hw/misc: In STM32L4x5 EXTI, handle direct and configurable interrupts Date: Wed, 22 May 2024 22:39:39 +0200 Message-ID: <20240522204020.203905-3-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240522204020.203905-1-ines.varhol@telecom-paris.fr> References: <20240522204020.203905-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=137.194.2.223; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy4.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1716410482036100002 Content-Type: text/plain; charset="utf-8" The previous implementation for EXTI interrupts only handled "configurable" interrupts, like those originating from STM32L4x5 SYSCFG (the only device currently connected to the EXTI up until now). In order to connect STM32L4x5 USART to the EXTI, this commit adds handling for direct interrupts (interrupts without configurable edge). The implementation of configurable interrupts (interrupts supporting edge selection) was incorrectly expecting alternating input levels : this commits adds a new status field `irq_levels` to actually detect edges. Signed-off-by: In=C3=A8s Varhol --- include/hw/misc/stm32l4x5_exti.h | 2 ++ hw/misc/stm32l4x5_exti.c | 25 ++++++++++++++++++++----- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/include/hw/misc/stm32l4x5_exti.h b/include/hw/misc/stm32l4x5_e= xti.h index 82f75a2417..62f79362f2 100644 --- a/include/hw/misc/stm32l4x5_exti.h +++ b/include/hw/misc/stm32l4x5_exti.h @@ -45,6 +45,8 @@ struct Stm32l4x5ExtiState { uint32_t swier[EXTI_NUM_REGISTER]; uint32_t pr[EXTI_NUM_REGISTER]; =20 + /* used for edge detection */ + uint32_t irq_levels[EXTI_NUM_REGISTER]; qemu_irq irq[EXTI_NUM_LINES]; }; =20 diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c index eebefc6cd3..bdc3dc10d6 100644 --- a/hw/misc/stm32l4x5_exti.c +++ b/hw/misc/stm32l4x5_exti.c @@ -87,6 +87,7 @@ static void stm32l4x5_exti_reset_hold(Object *obj, ResetT= ype type) s->ftsr[bank] =3D 0x00000000; s->swier[bank] =3D 0x00000000; s->pr[bank] =3D 0x00000000; + s->irq_levels[bank] =3D 0x00000000; } } =20 @@ -106,17 +107,30 @@ static void stm32l4x5_exti_set_irq(void *opaque, int = irq, int level) return; } =20 + /* In case of a direct line interrupt */ + if (extract32(exti_romask[bank], irq, 1)) { + qemu_set_irq(s->irq[oirq], level); + return; + } + + /* In case of a configurable interrupt */ if (((1 << irq) & s->rtsr[bank]) && level) { /* Rising Edge */ - s->pr[bank] |=3D 1 << irq; - qemu_irq_pulse(s->irq[oirq]); + if (!extract32(s->irq_levels[bank], irq, 1)) { + s->pr[bank] |=3D 1 << irq; + qemu_irq_pulse(s->irq[oirq]); + } + s->irq_levels[bank] |=3D 1 << irq; } else if (((1 << irq) & s->ftsr[bank]) && !level) { /* Falling Edge */ - s->pr[bank] |=3D 1 << irq; - qemu_irq_pulse(s->irq[oirq]); + if (extract32(s->irq_levels[bank], irq, 1)) { + s->pr[bank] |=3D 1 << irq; + qemu_irq_pulse(s->irq[oirq]); + } + s->irq_levels[bank] &=3D ~(1 << irq); } /* - * In the following situations : + * In the following situations (for configurable interrupts) : * - falling edge but rising trigger selected * - rising edge but falling trigger selected * - no trigger selected @@ -262,6 +276,7 @@ static const VMStateDescription vmstate_stm32l4x5_exti = =3D { VMSTATE_UINT32_ARRAY(ftsr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), VMSTATE_UINT32_ARRAY(swier, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), VMSTATE_UINT32_ARRAY(pr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER), + VMSTATE_UINT32_ARRAY(irq_levels, Stm32l4x5ExtiState, EXTI_NUM_REGI= STER), VMSTATE_END_OF_LIST() } }; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=137.194.2.223; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy4.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1716410511102100001 Content-Type: text/plain; charset="utf-8" The USART devices were previously connecting their outbound IRQs directly to the CPU because the EXTI wasn't handling direct lines interrupts. Now the USART connects to the EXTI inbound GPIOs, and the EXTI connects its IRQs to the CPU. The existing QTest for the USART (tests/qtest/stm32l4x5_usart-test.c) checks that USART1_IRQ in the CPU is pending when expected so it confirms that the connection through the EXTI still works. Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell --- hw/arm/stm32l4x5_soc.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 38f7a2d5d9..fac83d349c 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -81,6 +81,10 @@ static const int exti_irq[NUM_EXTI_IRQ] =3D { #define RCC_BASE_ADDRESS 0x40021000 #define RCC_IRQ 5 =20 +#define EXTI_USART1_IRQ 26 +#define EXTI_UART4_IRQ 29 +#define EXTI_LPUART1_IRQ 31 + static const int exti_or_gates_out[NUM_EXTI_OR_GATES] =3D { 23, 40, 63, 1, }; @@ -129,10 +133,6 @@ static const hwaddr uart_addr[] =3D { =20 #define LPUART_BASE_ADDRESS 0x40008000 =20 -static const int usart_irq[] =3D { 37, 38, 39 }; -static const int uart_irq[] =3D { 52, 53 }; -#define LPUART_IRQ 70 - static void stm32l4x5_soc_initfn(Object *obj) { Stm32l4x5SocState *s =3D STM32L4X5_SOC(obj); @@ -297,6 +297,7 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) } } =20 + /* Connect SYSCFG to EXTI */ for (unsigned i =3D 0; i < GPIO_NUM_PINS; i++) { qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(DEVICE(&s->exti), i)); @@ -322,15 +323,10 @@ static void stm32l4x5_soc_realize(DeviceState *dev_so= c, Error **errp) return; } sysbus_mmio_map(busdev, 0, usart_addr[i]); - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i= ])); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti), + EXTI_USART1_IRQ + i= )); } =20 - /* - * TODO: Connect the USARTs, UARTs and LPUART to the EXTI once the EXTI - * can handle other gpio-in than the gpios. (e.g. Direct Lines for the - * usarts) - */ - /* UART devices */ for (int i =3D 0; i < STM_NUM_UARTS; i++) { g_autofree char *name =3D g_strdup_printf("uart%d-out", STM_NUM_US= ARTS + i + 1); @@ -343,7 +339,8 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) return; } sysbus_mmio_map(busdev, 0, uart_addr[i]); - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, uart_irq[i]= )); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti), + EXTI_UART4_IRQ + i)= ); } =20 /* LPUART device*/ @@ -356,7 +353,8 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) return; } sysbus_mmio_map(busdev, 0, LPUART_BASE_ADDRESS); - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, LPUART_IRQ)); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti), + EXTI_LPUART1_IRQ)); =20 /* APB1 BUS */ create_unimplemented_device("TIM2", 0x40000000, 0x400); --=20 2.43.2