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charset="utf-8" The 32-bit AAM/AAD opcodes are using helpers that read and write flags and env->regs[R_EAX]. Clean them up so that the table correctly includes AX as a 16-bit input and output. No real reason to do it to be honest, but they are nice one-output helpers and it removes the masking of env->regs[R_EAX] that generic load/writeback code already does. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/helper.h | 4 ++-- target/i386/tcg/int_helper.c | 19 ++++++++----------- target/i386/tcg/decode-new.c.inc | 4 ++-- target/i386/tcg/emit.c.inc | 8 ++++---- 4 files changed, 16 insertions(+), 19 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 3c207ac62d6..a52a1bf0f21 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -22,8 +22,8 @@ DEF_HELPER_FLAGS_5(bndstx32, TCG_CALL_NO_WG, void, env, t= l, tl, i64, i64) DEF_HELPER_FLAGS_5(bndstx64, TCG_CALL_NO_WG, void, env, tl, tl, i64, i64) DEF_HELPER_1(bnd_jmp, void, env) =20 -DEF_HELPER_2(aam, void, env, int) -DEF_HELPER_2(aad, void, env, int) +DEF_HELPER_FLAGS_2(aam, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(aad, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_1(aaa, void, env) DEF_HELPER_1(aas, void, env) DEF_HELPER_1(daa, void, env) diff --git a/target/i386/tcg/int_helper.c b/target/i386/tcg/int_helper.c index df16130f5df..4cc59f15203 100644 --- a/target/i386/tcg/int_helper.c +++ b/target/i386/tcg/int_helper.c @@ -145,27 +145,24 @@ void helper_idivl_EAX(CPUX86State *env, target_ulong = t0) =20 /* bcd */ =20 -/* XXX: exception */ -void helper_aam(CPUX86State *env, int base) +target_ulong helper_aam(target_ulong al, target_ulong base) { - int al, ah; + int ah; =20 - al =3D env->regs[R_EAX] & 0xff; + al &=3D 0xff; ah =3D al / base; al =3D al % base; - env->regs[R_EAX] =3D (env->regs[R_EAX] & ~0xffff) | al | (ah << 8); - CC_DST =3D al; + return al | (ah << 8); } =20 -void helper_aad(CPUX86State *env, int base) +target_ulong helper_aad(target_ulong ax, target_ulong base) { int al, ah; =20 - al =3D env->regs[R_EAX] & 0xff; - ah =3D (env->regs[R_EAX] >> 8) & 0xff; + al =3D ax & 0xff; + ah =3D (ax >> 8) & 0xff; al =3D ((ah * base) + al) & 0xff; - env->regs[R_EAX] =3D (env->regs[R_EAX] & ~0xffff) | al; - CC_DST =3D al; + return al; } =20 void helper_aaa(CPUX86State *env) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index 141ab2bc560..27dc1bb146b 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -1480,8 +1480,8 @@ static const X86OpEntry opcodes_root[256] =3D { [0xD1] =3D X86_OP_GROUP1(group2, E,v), [0xD2] =3D X86_OP_GROUP2(group2, E,b, 1,b), /* CL */ [0xD3] =3D X86_OP_GROUP2(group2, E,v, 1,b), /* CL */ - [0xD4] =3D X86_OP_ENTRYr(AAM, I,b), - [0xD5] =3D X86_OP_ENTRYr(AAD, I,b), + [0xD4] =3D X86_OP_ENTRY2(AAM, 0,w, I,b), + [0xD5] =3D X86_OP_ENTRY2(AAD, 0,w, I,b), [0xD6] =3D X86_OP_ENTRYw(SALC, 0,b), [0xD7] =3D X86_OP_ENTRY1(XLAT, 0,b, zextT0), /* AL read/written */ =20 diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 2dee33dd487..ecfdeb1e668 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1084,8 +1084,8 @@ static void gen_AAA(DisasContext *s, CPUX86State *env= , X86DecodedInsn *decode) =20 static void gen_AAD(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) { - gen_helper_aad(tcg_env, tcg_constant_i32(decode->immediate)); - set_cc_op(s, CC_OP_LOGICB); + gen_helper_aad(s->T0, s->T0, s->T1); + prepare_update1_cc(decode, s, CC_OP_LOGICB); } =20 static void gen_AAM(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) @@ -1093,8 +1093,8 @@ static void gen_AAM(DisasContext *s, CPUX86State *env= , X86DecodedInsn *decode) if (decode->immediate =3D=3D 0) { gen_exception(s, EXCP00_DIVZ); } else { - gen_helper_aam(tcg_env, tcg_constant_i32(decode->immediate)); - set_cc_op(s, CC_OP_LOGICB); + gen_helper_aam(s->T0, s->T0, s->T1); + prepare_update1_cc(decode, s, CC_OP_LOGICB); } } =20 --=20 2.45.1