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charset="utf-8" Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- disas/riscv.c | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index e236c8b5b7..4cd769f165 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -906,6 +906,46 @@ typedef enum { rv_op_amocas_w =3D 875, rv_op_amocas_d =3D 876, rv_op_amocas_q =3D 877, + rv_mop_r_0 =3D 878, + rv_mop_r_1 =3D 879, + rv_mop_r_2 =3D 880, + rv_mop_r_3 =3D 881, + rv_mop_r_4 =3D 882, + rv_mop_r_5 =3D 883, + rv_mop_r_6 =3D 884, + rv_mop_r_7 =3D 885, + rv_mop_r_8 =3D 886, + rv_mop_r_9 =3D 887, + rv_mop_r_10 =3D 888, + rv_mop_r_11 =3D 889, + rv_mop_r_12 =3D 890, + rv_mop_r_13 =3D 891, + rv_mop_r_14 =3D 892, + rv_mop_r_15 =3D 893, + rv_mop_r_16 =3D 894, + rv_mop_r_17 =3D 895, + rv_mop_r_18 =3D 896, + rv_mop_r_19 =3D 897, + rv_mop_r_20 =3D 898, + rv_mop_r_21 =3D 899, + rv_mop_r_22 =3D 900, + rv_mop_r_23 =3D 901, + rv_mop_r_24 =3D 902, + rv_mop_r_25 =3D 903, + rv_mop_r_26 =3D 904, + rv_mop_r_27 =3D 905, + rv_mop_r_28 =3D 906, + rv_mop_r_29 =3D 907, + rv_mop_r_30 =3D 908, + rv_mop_r_31 =3D 909, + rv_mop_rr_0 =3D 910, + rv_mop_rr_1 =3D 911, + rv_mop_rr_2 =3D 912, + rv_mop_rr_3 =3D 913, + rv_mop_rr_4 =3D 914, + rv_mop_rr_5 =3D 915, + rv_mop_rr_6 =3D 916, + rv_mop_rr_7 =3D 917, } rv_op; =20 /* register names */ @@ -2096,6 +2136,46 @@ const rv_opcode_data rvi_opcode_data[] =3D { { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, + { "mop.r.0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.2", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.3", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.4", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.5", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.6", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.7", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.9", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.10", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.11", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.12", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.13", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.14", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.15", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.16", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.17", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.18", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.19", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.20", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.21", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.22", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.23", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.24", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.25", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.26", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.27", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.28", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.29", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.30", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.r.31", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, + { "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, }; =20 /* CSR names */ @@ -2945,6 +3025,26 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) break; case 13: op =3D rv_op_lui; break; case 14: + if (dec->cfg->ext_zimop) { + int imm_mop5, imm_mop3; + if (extract32(inst, 12, 3) =3D=3D 0b100) { + if ((extract32(inst, 22, 10) & 0b1011001111) + =3D=3D 0b1000000111) { + imm_mop5 =3D deposit32(deposit32(extract32(inst, 2= 0, 2), + 2, 2, + extract32(inst, 26,= 2)), + 4, 1, extract32(inst, 30, 1)); + op =3D rv_mop_r_0 + imm_mop5; + break; + } else if ((extract32(inst, 25, 7) & 0b1011001) + =3D=3D 0b1000001) { + imm_mop3 =3D deposit32(extract32(inst, 26, 2), + 2, 1, extract32(inst, 30, 1)); + op =3D rv_mop_rr_0 + imm_mop3; + break; + } + } + } switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { case 0: op =3D rv_op_addw; break; --=20 2.25.1