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a="37972573" X-IronPort-AV: E=Sophos;i="6.08,179,1712646000"; d="scan'208";a="37972573" X-CSE-ConnectionGUID: CBQ+VyBzQHOM3zQcJpjZzA== X-CSE-MsgGUID: 7YBgPqafRMyBkN+1Sa/B+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,179,1712646000"; d="scan'208";a="33597823" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH rfcv2 10/17] intel_iommu: Process PASID-based iotlb invalidation Date: Wed, 22 May 2024 14:23:06 +0800 Message-Id: <20240522062313.453317-11-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240522062313.453317-1-zhenzhong.duan@intel.com> References: <20240522062313.453317-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1716359465317100023 Content-Type: text/plain; charset="utf-8" PASID-based iotlb (piotlb) is used during walking Intel VT-d stage-1 page table. This emulates the stage-1 page table iotlb invalidation requested by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB). Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 45 ++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index c0a94af820..8a375d038a 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -453,6 +453,9 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) #define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ VTD_DOMAIN_ID_MASK) +#define VTD_INV_DESC_PIOTLB_ADDR(val) ((val) & ~0xfffULL) +#define VTD_INV_DESC_PIOTLB_AM(val) ((val) & 0x3fULL) +#define VTD_INV_DESC_PIOTLB_IH(val) (((val) >> 6) & 0x1) =20 /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 0078bad9d4..f6c429ae4c 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -304,6 +304,28 @@ static gboolean vtd_hash_remove_by_page(gpointer key, = gpointer value, return (entry->gfn & info->mask) =3D=3D gfn || entry->gfn =3D=3D gfn_t= lb; } =20 +static gboolean vtd_hash_remove_by_page_piotlb(gpointer key, gpointer valu= e, + gpointer user_data) +{ + VTDIOTLBEntry *entry =3D (VTDIOTLBEntry *)value; + VTDIOTLBPageInvInfo *info =3D (VTDIOTLBPageInvInfo *)user_data; + uint64_t gfn =3D (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask; + uint64_t gfn_tlb =3D (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K; + + /* + * According to spec, PASID-based-IOTLB Invalidation in page granulari= ty + * doesn't invalidate IOTLB entries caching second-stage (PGTT=3D010b) + * or pass-through (PGTT=3D100b) mappings. Nested isn't supported yet, + * so only need to check first-stage (PGTT=3D001b) mappings. + */ + if (entry->pgtt !=3D VTD_SM_PASID_ENTRY_FLT) { + return false; + } + + return entry->domain_id =3D=3D info->domain_id && entry->pasid =3D=3D = info->pasid && + ((entry->gfn & info->mask) =3D=3D gfn || entry->gfn =3D=3D gfn_= tlb); +} + /* Reset all the gen of VTDAddressSpace to zero and set the gen of * IntelIOMMUState to 1. Must be called with IOMMU lock held. */ @@ -2866,11 +2888,30 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUS= tate *s, } } =20 +static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain= _id, + uint32_t pasid, hwaddr addr, uint8_= t am, + bool ih) +{ + VTDIOTLBPageInvInfo info; + + info.domain_id =3D domain_id; + info.pasid =3D pasid; + info.addr =3D addr; + info.mask =3D ~((1 << am) - 1); + + vtd_iommu_lock(s); + g_hash_table_foreach_remove(s->iotlb, + vtd_hash_remove_by_page_piotlb, &info); + vtd_iommu_unlock(s); +} + static bool vtd_process_piotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { uint16_t domain_id; uint32_t pasid; + uint8_t am; + hwaddr addr; =20 if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { @@ -2887,6 +2928,10 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState = *s, break; =20 case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: + am =3D VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]); + addr =3D (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]); + vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am, + VTD_INV_DESC_PIOTLB_IH(inv_desc->val[1]= )); break; =20 default: --=20 2.34.1