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a="37972551" X-IronPort-AV: E=Sophos;i="6.08,179,1712646000"; d="scan'208";a="37972551" X-CSE-ConnectionGUID: i3CxBjhBTG++xFsUmObw7Q== X-CSE-MsgGUID: SlMmBEhAQ3qSTSd+BK7lFA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,179,1712646000"; d="scan'208";a="33597804" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH rfcv2 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Date: Wed, 22 May 2024 14:23:05 +0800 Message-Id: <20240522062313.453317-10-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240522062313.453317-1-zhenzhong.duan@intel.com> References: <20240522062313.453317-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1716359431131100003 Content-Type: text/plain; charset="utf-8" According to spec, Page-Selective-within-Domain Invalidation (11b): 1. IOTLB entries caching second-stage mappings (PGTT=3D010b) or pass-through (PGTT=3D100b) mappings associated with the specified domain-id and the input-address range are invalidated. 2. IOTLB entries caching first-stage (PGTT=3D001b) or nested (PGTT=3D011b) mapping associated with specified domain-id are invalidated. So per spec definition the Page-Selective-within-Domain Invalidation needs to flush first stage and nested cached IOTLB enties as well. We don't support nested yet and pass-through mapping is never cached, so what in iotlb cache are only first-stage and second-stage mappings. Add a tag pgtt in VTDIOTLBEntry to mark PGTT type of the mapping and invalidate entries based on PGTT type. Signed-off-by: Zhenzhong Duan --- include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 20 +++++++++++++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 011f374883..b0d5b5a5be 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -156,6 +156,7 @@ struct VTDIOTLBEntry { uint64_t pte; uint64_t mask; uint8_t access_flags; + uint8_t pgtt; }; =20 /* VT-d Source-ID Qualifier types */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 0801112e2e..0078bad9d4 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -287,9 +287,21 @@ static gboolean vtd_hash_remove_by_page(gpointer key, = gpointer value, VTDIOTLBPageInvInfo *info =3D (VTDIOTLBPageInvInfo *)user_data; uint64_t gfn =3D (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask; uint64_t gfn_tlb =3D (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K; - return (entry->domain_id =3D=3D info->domain_id) && - (((entry->gfn & info->mask) =3D=3D gfn) || - (entry->gfn =3D=3D gfn_tlb)); + + if (entry->domain_id !=3D info->domain_id) { + return false; + } + + /* + * According to spec, IOTLB entries caching first-stage (PGTT=3D001b) = or + * nested (PGTT=3D011b) mapping associated with specified domain-id are + * invalidated. Nested isn't supported yet, so only need to check 001b. + */ + if (entry->pgtt =3D=3D VTD_SM_PASID_ENTRY_FLT) { + return true; + } + + return (entry->gfn & info->mask) =3D=3D gfn || entry->gfn =3D=3D gfn_t= lb; } =20 /* Reset all the gen of VTDAddressSpace to zero and set the gen of @@ -382,6 +394,8 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16= _t source_id, entry->access_flags =3D access_flags; entry->mask =3D vtd_slpt_level_page_mask(level); entry->pasid =3D pasid; + entry->pgtt =3D s->scalable_modern ? VTD_SM_PASID_ENTRY_FLT + : VTD_SM_PASID_ENTRY_SLT; =20 key->gfn =3D gfn; key->sid =3D source_id; --=20 2.34.1