From nobody Mon Nov 25 07:38:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=yandex-team.ru ARC-Seal: i=1; a=rsa-sha256; t=1716308729; cv=none; d=zohomail.com; s=zohoarc; b=jrnIn4ZhLkbGvl/PHg5phJb/UCh/FtjQu0NQP9M7klxXZu4u3MQUea47YLIYkCXM8IAyz3J71FDiolbPsRyEl5lAL0cdgVB6vz0i94JU1kJRjpcrJw2c/dk0s5glVu2x8kuqW+Thrcpj8dk/6/VlkPHtjpcV+4BFK0UbfxyA4yk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716308729; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8dmXIG071P4jqpkop1qyTQRp9nX2PPjwWXGr8cvbSk8=; b=GzQibQFxBXgMR3Y2aAjtCsBHd2AwvUUOvihiGTr3WN8cps13zJ1Hm2gNCYcsMTV6ngTa32ZqgDnCFQjm7xriaYwExsYKM/1wihMJEyRtCoKs3jS3WHOSIJ2PxXQr1R+qwPaBHHlaRK3f8xvpz9nvwu5yp3X1sIS14GNw7YQCcOk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716308728624758.8273857031811; Tue, 21 May 2024 09:25:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s9SHb-00061R-JL; Tue, 21 May 2024 12:24:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s9SHX-000610-Fo for qemu-devel@nongnu.org; Tue, 21 May 2024 12:24:07 -0400 Received: from forwardcorp1b.mail.yandex.net ([178.154.239.136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s9SHU-0005kU-Aq for qemu-devel@nongnu.org; Tue, 21 May 2024 12:24:07 -0400 Received: from mail-nwsmtp-smtp-corp-main-69.vla.yp-c.yandex.net (mail-nwsmtp-smtp-corp-main-69.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:6401:0:640:7e6f:0]) by forwardcorp1b.mail.yandex.net (Yandex) with ESMTPS id 9F30960D98; Tue, 21 May 2024 19:23:56 +0300 (MSK) Received: from davydov-max-nux.yandex-team.ru (unknown [2a02:6b8:b081:b738::1:8]) by mail-nwsmtp-smtp-corp-main-69.vla.yp-c.yandex.net (smtpcorp/Yandex) with ESMTPSA id lNMBDR0IZqM0-iRaZq5ub; Tue, 21 May 2024 19:23:56 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex-team.ru; s=default; t=1716308636; bh=8dmXIG071P4jqpkop1qyTQRp9nX2PPjwWXGr8cvbSk8=; h=Message-Id:Date:Cc:Subject:To:From; b=0q9uMo3VXP17D04KK+iYnSwsCzOlG1aqtMf9KZL/+PZ9ohqaG94DjjMz4lJA7/i63 XoTxC8YWT2F4N+be1LVD8ezbGtol+klSwmUNUqYazdKzO9IjjzIIqHQtAjv/u/6GVY rRekeGbrmg0KbK6r9aBlEIoPy9ytdV6bghghOBSU= Authentication-Results: mail-nwsmtp-smtp-corp-main-69.vla.yp-c.yandex.net; dkim=pass header.i=@yandex-team.ru From: Maksim Davydov To: qemu-devel@nongnu.org Cc: davydov-max@yandex-team.ru, babu.moger@amd.com, pbonzini@redhat.com Subject: [PATCH] target/i386: Add x-amd-ccx-size property Date: Tue, 21 May 2024 19:23:47 +0300 Message-Id: <20240521162347.9149-1-davydov-max@yandex-team.ru> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.154.239.136; envelope-from=davydov-max@yandex-team.ru; helo=forwardcorp1b.mail.yandex.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @yandex-team.ru) X-ZM-MESSAGEID: 1716308732306100001 Content-Type: text/plain; charset="utf-8" According to AMD64 Architecture Programmer's Manual volume 3, information about the cache topology is exposed by 0x8000001D CPUID leaf, and 0x8000001E CPUID leaf is exposing information about the topology of the entire processor. For example, CPUID on the real EPYC Milan 7713 shows: * 0x8000001D_EAX_3 =3D 0x0003c163 * 0x8000001E_ECX =3D 0x00000001 This means that 16 logical processors share one L3 cache, which gives 8 CCXs per processor, but only 1 node per processor. Thus, on real processor models, nodes and CCX are different things. What is more, Zen2, for example, has 2 CCX per die. It is also worth considering that for some desktop processors the number of cores is not a power of two, so the CCX size may vary within single family. Therefore, I suggest making it possible to set the CCX size as a property of the CPU. In this case, one will be able to set the CCX size if needed, but for others the default value will remain. Signed-off-by: Maksim Davydov --- target/i386/cpu.c | 19 +++++++++++++------ target/i386/cpu.h | 3 +++ 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index cfe7c92d6b..bbf8fb137c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -328,10 +328,10 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *= l2, /* Encode cache info for CPUID[8000001D] */ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, X86CPUTopoInfo *topo_info, + uint32_t l3_threads, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t l3_threads; assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 @@ -340,7 +340,8 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *ca= che, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_threads =3D topo_info->cores_per_die * topo_info->threads_per_c= ore; + l3_threads =3D (l3_threads ? l3_threads : + topo_info->cores_per_die * topo_info->threads_per_co= re); *eax |=3D (l3_threads - 1) << 14; } else { *eax |=3D ((topo_info->threads_per_core - 1) << 14); @@ -6757,19 +6758,23 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, switch (count) { case 0: /* L1 dcache info */ encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, - &topo_info, eax, ebx, ecx, edx); + &topo_info, cpu->amd_ccx_size, + eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, - &topo_info, eax, ebx, ecx, edx); + &topo_info, cpu->amd_ccx_size, + eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, - &topo_info, eax, ebx, ecx, edx); + &topo_info, cpu->amd_ccx_size, + eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, - &topo_info, eax, ebx, ecx, edx); + &topo_info, cpu->amd_ccx_size, + eax, ebx, ecx, edx); break; default: /* end of info */ *eax =3D *ebx =3D *ecx =3D *edx =3D 0; @@ -8105,6 +8110,8 @@ static Property x86_cpu_properties[] =3D { false), DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, true), + DEFINE_PROP_UINT32("x-amd-ccx-size", X86CPU, amd_ccx_size, 0), + DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ccccb62fc3..01104847a1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2036,6 +2036,9 @@ struct ArchCPU { */ uint32_t guest_phys_bits; =20 + /* Number of logical processors that shares L3 cache */ + uint32_t amd_ccx_size; + /* in order to simplify APIC support, we leave this pointer to the user */ struct DeviceState *apic_state; --=20 2.34.1