From nobody Mon Nov 25 07:24:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716295810753791.520370252106; Tue, 21 May 2024 05:50:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s9OwB-0006y6-Ke; Tue, 21 May 2024 08:49:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s9Ow4-0006n6-82 for qemu-devel@nongnu.org; Tue, 21 May 2024 08:49:45 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s9Ovy-00055v-Ho for qemu-devel@nongnu.org; Tue, 21 May 2024 08:49:44 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Axz69emExmbUkCAA--.1429S3; Tue, 21 May 2024 20:49:34 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxusZdmExmqDkEAA--.12666S3; Tue, 21 May 2024 20:49:34 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org Subject: [PATCH v3 1/3] hw/intc/loongarch_extioi: Add extioi virt extension definition Date: Tue, 21 May 2024 20:32:23 +0800 Message-Id: <20240521123225.231072-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20240521123225.231072-1-gaosong@loongson.cn> References: <20240521123225.231072-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DxusZdmExmqDkEAA--.12666S3 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716295817459100009 Content-Type: text/plain; charset="utf-8" On LoongArch, IRQs can be routed to four vcpus with hardware extioi. This patch adds the extioi virt extension definition so that the IRQ can route to 256 vcpus. Signed-off-by: Song Gao Reviewed-by: Bibo Mao --- include/hw/intc/loongarch_extioi.h | 21 +++++++ hw/intc/loongarch_extioi.c | 88 ++++++++++++++++++++++++++++-- 2 files changed, 105 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch= _extioi.h index 410c6e1121..eccc2e0d18 100644 --- a/include/hw/intc/loongarch_extioi.h +++ b/include/hw/intc/loongarch_extioi.h @@ -41,6 +41,24 @@ #define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET) #define EXTIOI_SIZE 0x800 =20 +#define EXTIOI_VIRT_BASE (0x40000000) +#define EXTIOI_VIRT_SIZE (0x1000) +#define EXTIOI_VIRT_FEATURES (0x0) +#define EXTIOI_HAS_VIRT_EXTENSION (0) +#define EXTIOI_HAS_ENABLE_OPTION (1) +#define EXTIOI_HAS_INT_ENCODE (2) +#define EXTIOI_HAS_CPU_ENCODE (3) +#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \ + | BIT(EXTIOI_HAS_ENABLE_OPTION) \ + | BIT(EXTIOI_HAS_INT_ENCODE) \ + | BIT(EXTIOI_HAS_CPU_ENCODE)) +#define EXTIOI_VIRT_CONFIG (0x4) +#define EXTIOI_ENABLE (1) +#define EXTIOI_ENABLE_INT_ENCODE (2) +#define EXTIOI_ENABLE_CPU_ENCODE (3) +#define EXTIOI_VIRT_COREMAP_START (0x40) +#define EXTIOI_VIRT_COREMAP_END (0x240) + typedef struct ExtIOICore { uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT]; DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS); @@ -52,6 +70,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXT= IOI) struct LoongArchExtIOI { SysBusDevice parent_obj; uint32_t num_cpu; + uint32_t features; + uint32_t status; /* hardware state */ uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2]; uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT]; @@ -65,5 +85,6 @@ struct LoongArchExtIOI { qemu_irq irq[EXTIOI_IRQS]; ExtIOICore *cpu; MemoryRegion extioi_system_mem; + MemoryRegion virt_extend; }; #endif /* LOONGARCH_EXTIOI_H */ diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c index 0b358548eb..e605ca64d5 100644 --- a/hw/intc/loongarch_extioi.c +++ b/hw/intc/loongarch_extioi.c @@ -143,10 +143,13 @@ static inline void extioi_update_sw_coremap(LoongArch= ExtIOI *s, int irq, =20 for (i =3D 0; i < 4; i++) { cpu =3D val & 0xff; - cpu =3D ctz32(cpu); - cpu =3D (cpu >=3D 4) ? 0 : cpu; val =3D val >> 8; =20 + if (!(s->status & BIT(EXTIOI_ENABLE_CPU_ENCODE))) { + cpu =3D ctz32(cpu); + cpu =3D (cpu >=3D 4) ? 0 : cpu; + } + if (s->sw_coremap[irq + i] =3D=3D cpu) { continue; } @@ -265,6 +268,61 @@ static const MemoryRegionOps extioi_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static MemTxResult extioi_virt_readw(void *opaque, hwaddr addr, uint64_t *= data, + unsigned size, MemTxAttrs attrs) +{ + LoongArchExtIOI *s =3D LOONGARCH_EXTIOI(opaque); + + switch (addr) { + case EXTIOI_VIRT_FEATURES: + *data =3D s->features; + break; + case EXTIOI_VIRT_CONFIG: + *data =3D s->status; + break; + default: + break; + } + + return MEMTX_OK; +} + +static MemTxResult extioi_virt_writew(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + LoongArchExtIOI *s =3D LOONGARCH_EXTIOI(opaque); + + switch (addr) { + case EXTIOI_VIRT_FEATURES: + return MEMTX_ACCESS_ERROR; + + case EXTIOI_VIRT_CONFIG: + /* + * extioi features can only be set at disabled status + */ + if ((s->status & BIT(EXTIOI_ENABLE)) && val) { + return MEMTX_ACCESS_ERROR; + } + + s->status =3D val & s->features; + break; + default: + break; + } + return MEMTX_OK; +} + +static const MemoryRegionOps extioi_virt_ops =3D { + .read_with_attrs =3D extioi_virt_readw, + .write_with_attrs =3D extioi_virt_writew, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + static void loongarch_extioi_realize(DeviceState *dev, Error **errp) { LoongArchExtIOI *s =3D LOONGARCH_EXTIOI(dev); @@ -284,6 +342,16 @@ static void loongarch_extioi_realize(DeviceState *dev,= Error **errp) memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_ops, s, "extioi_system_mem", 0x900); sysbus_init_mmio(sbd, &s->extioi_system_mem); + + if (s->features & BIT(EXTIOI_HAS_VIRT_EXTENSION)) { + memory_region_init_io(&s->virt_extend, OBJECT(s), &extioi_virt_ops, + s, "extioi_virt", EXTIOI_VIRT_SIZE); + sysbus_init_mmio(sbd, &s->virt_extend); + s->features |=3D EXTIOI_VIRT_HAS_FEATURES; + } else { + s->status |=3D BIT(EXTIOI_ENABLE); + } + s->cpu =3D g_new0(ExtIOICore, s->num_cpu); if (s->cpu =3D=3D NULL) { error_setg(errp, "Memory allocation for ExtIOICore faile"); @@ -304,6 +372,13 @@ static void loongarch_extioi_finalize(Object *obj) g_free(s->cpu); } =20 +static void loongarch_extioi_reset(DeviceState *d) +{ + LoongArchExtIOI *s =3D LOONGARCH_EXTIOI(d); + + s->status =3D 0; +} + static int vmstate_extioi_post_load(void *opaque, int version_id) { LoongArchExtIOI *s =3D LOONGARCH_EXTIOI(opaque); @@ -333,8 +408,8 @@ static const VMStateDescription vmstate_extioi_core =3D= { =20 static const VMStateDescription vmstate_loongarch_extioi =3D { .name =3D TYPE_LOONGARCH_EXTIOI, - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .post_load =3D vmstate_extioi_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_CO= UNT), @@ -347,12 +422,16 @@ static const VMStateDescription vmstate_loongarch_ext= ioi =3D { =20 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu, vmstate_extioi_core, ExtIOICore), + VMSTATE_UINT32(features, LoongArchExtIOI), + VMSTATE_UINT32(status, LoongArchExtIOI), VMSTATE_END_OF_LIST() } }; =20 static Property extioi_properties[] =3D { DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1), + DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOI, featu= res, + EXTIOI_HAS_VIRT_EXTENSION, 0), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -361,6 +440,7 @@ static void loongarch_extioi_class_init(ObjectClass *kl= ass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D loongarch_extioi_realize; + dc->reset =3D loongarch_extioi_reset; device_class_set_props(dc, extioi_properties); dc->vmsd =3D &vmstate_loongarch_extioi; } --=20 2.34.1 From nobody Mon Nov 25 07:24:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716295815378451.2428507757545; Tue, 21 May 2024 05:50:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s9OwF-0007AX-40; Tue, 21 May 2024 08:49:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s9Ow4-0006n8-HQ for qemu-devel@nongnu.org; Tue, 21 May 2024 08:49:44 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s9Ovy-00055t-GT for qemu-devel@nongnu.org; Tue, 21 May 2024 08:49:44 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxDOtfmExmb0kCAA--.4815S3; Tue, 21 May 2024 20:49:35 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxusZdmExmqDkEAA--.12666S4; Tue, 21 May 2024 20:49:34 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org Subject: [PATCH v3 2/3] hw/loongarch/virt: Enable extioi virt extension Date: Tue, 21 May 2024 20:32:24 +0800 Message-Id: <20240521123225.231072-3-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20240521123225.231072-1-gaosong@loongson.cn> References: <20240521123225.231072-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DxusZdmExmqDkEAA--.12666S4 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716295817511100010 Content-Type: text/plain; charset="utf-8" This patch adds a new board attribute 'v-eiointc'. A value of true enables the virt extended I/O interrupt controller. VMs working in kvm mode have 'v-eiointc' enabled by default. Signed-off-by: Song Gao --- include/hw/loongarch/virt.h | 1 + target/loongarch/cpu.h | 1 + hw/loongarch/virt.c | 100 ++++++++++++++++++++++++++++++++---- 3 files changed, 93 insertions(+), 9 deletions(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 2c4f5cf9c8..8fdfacf268 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -50,6 +50,7 @@ struct LoongArchVirtMachineState { Notifier machine_done; Notifier powerdown_notifier; OnOffAuto acpi; + OnOffAuto veiointc; char *oem_id; char *oem_table_id; DeviceState *acpi_ged; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 41b8e6d96d..6c41fafb70 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -36,6 +36,7 @@ #define CPUNAME_REG 0x20 #define MISC_FUNC_REG 0x420 #define IOCSRM_EXTIOI_EN 48 +#define IOCSRM_EXTIOI_INT_ENCODE 49 =20 #define IOCSR_MEM_SIZE 0x428 =20 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 95f9ed5cae..e7edc6c9f9 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -11,6 +11,7 @@ #include "hw/boards.h" #include "hw/char/serial.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "sysemu/sysemu.h" #include "sysemu/qtest.h" #include "sysemu/runstate.h" @@ -47,6 +48,31 @@ #include "hw/block/flash.h" #include "qemu/error-report.h" =20 +static bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvms) +{ + if (lvms->veiointc =3D=3D ON_OFF_AUTO_OFF) { + return false; + } + return true; +} + +static void virt_get_veiointc(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); + OnOffAuto veiointc =3D lvms->veiointc; + + visit_type_OnOffAuto(v, name, &veiointc, errp); +} + +static void virt_set_veiointc(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); + + visit_type_OnOffAuto(v, name, &lvms->veiointc, errp); +} + static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms, const char *name, const char *alias_prop_name) @@ -724,9 +750,16 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) /* Create EXTIOI device */ extioi =3D qdev_new(TYPE_LOONGARCH_EXTIOI); qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); + if (virt_is_veiointc_enabled(lvms)) { + qdev_prop_set_bit(extioi, "has-virtualization-extension", true); + } sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE, - sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); + sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); + if (virt_is_veiointc_enabled(lvms)) { + memory_region_add_subregion(&lvms->system_iocsr, EXTIOI_VIRT_BASE, + sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 1)); + } =20 /* * connect ext irq to the cpu irq @@ -833,33 +866,74 @@ static void virt_firmware_init(LoongArchVirtMachineSt= ate *lvms) } } =20 - static void virt_iocsr_misc_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(opaque); + uint64_t features; + + switch (addr) { + case MISC_FUNC_REG: + if (!virt_is_veiointc_enabled(lvms)) { + return; + } + + features =3D address_space_ldl(&lvms->as_iocsr, + EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, + MEMTXATTRS_UNSPECIFIED, NULL); + if (val & BIT_ULL(IOCSRM_EXTIOI_EN)) { + features |=3D BIT(EXTIOI_ENABLE); + } + if (val & BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE)) { + features |=3D BIT(EXTIOI_ENABLE_INT_ENCODE); + } + + address_space_stl(&lvms->as_iocsr, + EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, + features, MEMTXATTRS_UNSPECIFIED, NULL); + } } =20 static uint64_t virt_iocsr_misc_read(void *opaque, hwaddr addr, unsigned s= ize) { - uint64_t ret; + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(opaque); + uint64_t ret =3D 0; + int features; =20 switch (addr) { case VERSION_REG: - return 0x11ULL; + ret =3D 0x11ULL; + break; case FEATURE_REG: ret =3D BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); if (kvm_enabled()) { ret |=3D BIT(IOCSRF_VM); } - return ret; + break; case VENDOR_REG: - return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ + ret =3D 0x6e6f73676e6f6f4cULL; /* "Loongson" */ + break; case CPUNAME_REG: - return 0x303030354133ULL; /* "3A5000" */ + ret =3D 0x303030354133ULL; /* "3A5000" */ + break; case MISC_FUNC_REG: - return BIT_ULL(IOCSRM_EXTIOI_EN); + if (!virt_is_veiointc_enabled(lvms)) { + ret |=3D BIT_ULL(IOCSRM_EXTIOI_EN); + break; + } + + features =3D address_space_ldl(&lvms->as_iocsr, + EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, + MEMTXATTRS_UNSPECIFIED, NULL); + if (features & BIT(EXTIOI_ENABLE)) { + ret |=3D BIT_ULL(IOCSRM_EXTIOI_EN); + } + if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { + ret |=3D BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); + } } - return 0ULL; + + return ret; } =20 static const MemoryRegionOps virt_iocsr_misc_ops =3D { @@ -1045,6 +1119,9 @@ static void virt_initfn(Object *obj) { LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); =20 + if (tcg_enabled()) { + lvms->veiointc =3D ON_OFF_AUTO_OFF; + } lvms->acpi =3D ON_OFF_AUTO_AUTO; lvms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); lvms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); @@ -1231,6 +1308,11 @@ static void virt_class_init(ObjectClass *oc, void *d= ata) NULL, NULL); object_class_property_set_description(oc, "acpi", "Enable ACPI"); + object_class_property_add(oc, "v-eiointc", "OnOffAuto", + virt_get_veiointc, virt_set_veiointc, + NULL, NULL); + object_class_property_set_description(oc, "v-eiointc", + "Enable Virt Extend I/O Interrupt Controller."= ); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); #ifdef CONFIG_TPM machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); --=20 2.34.1 From nobody Mon Nov 25 07:24:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716295842103302.0562835438319; Tue, 21 May 2024 05:50:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s9OwC-00073l-Fn; Tue, 21 May 2024 08:49:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s9Ow4-0006n2-3Z for qemu-devel@nongnu.org; Tue, 21 May 2024 08:49:44 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s9Ovy-00055n-UO for qemu-devel@nongnu.org; Tue, 21 May 2024 08:49:43 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxSepfmExmcEkCAA--.1543S3; Tue, 21 May 2024 20:49:35 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxusZdmExmqDkEAA--.12666S5; Tue, 21 May 2024 20:49:35 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org Subject: [PATCH v3 3/3] hw/loongarch/virt: Use MemTxAttrs interface for misc ops Date: Tue, 21 May 2024 20:32:25 +0800 Message-Id: <20240521123225.231072-4-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20240521123225.231072-1-gaosong@loongson.cn> References: <20240521123225.231072-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DxusZdmExmqDkEAA--.12666S5 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716295843565100003 Content-Type: text/plain; charset="utf-8" Use MemTxAttrs interface read_with_attrs/write_with_attrs for virt_iocsr_misc_ops. Signed-off-by: Song Gao --- hw/loongarch/virt.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index e7edc6c9f9..0ab2b6860a 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -866,8 +866,9 @@ static void virt_firmware_init(LoongArchVirtMachineStat= e *lvms) } } =20 -static void virt_iocsr_misc_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult virt_iocsr_misc_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(opaque); uint64_t features; @@ -875,12 +876,12 @@ static void virt_iocsr_misc_write(void *opaque, hwadd= r addr, switch (addr) { case MISC_FUNC_REG: if (!virt_is_veiointc_enabled(lvms)) { - return; + return MEMTX_OK; } =20 features =3D address_space_ldl(&lvms->as_iocsr, EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, - MEMTXATTRS_UNSPECIFIED, NULL); + attrs, NULL); if (val & BIT_ULL(IOCSRM_EXTIOI_EN)) { features |=3D BIT(EXTIOI_ENABLE); } @@ -890,11 +891,15 @@ static void virt_iocsr_misc_write(void *opaque, hwadd= r addr, =20 address_space_stl(&lvms->as_iocsr, EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, - features, MEMTXATTRS_UNSPECIFIED, NULL); + features, attrs, NULL); } + + return MEMTX_OK; } =20 -static uint64_t virt_iocsr_misc_read(void *opaque, hwaddr addr, unsigned s= ize) +static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr, + uint64_t *data, + unsigned size, MemTxAttrs attrs) { LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(opaque); uint64_t ret =3D 0; @@ -924,7 +929,7 @@ static uint64_t virt_iocsr_misc_read(void *opaque, hwad= dr addr, unsigned size) =20 features =3D address_space_ldl(&lvms->as_iocsr, EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, - MEMTXATTRS_UNSPECIFIED, NULL); + attrs, NULL); if (features & BIT(EXTIOI_ENABLE)) { ret |=3D BIT_ULL(IOCSRM_EXTIOI_EN); } @@ -933,12 +938,13 @@ static uint64_t virt_iocsr_misc_read(void *opaque, hw= addr addr, unsigned size) } } =20 - return ret; + *data =3D ret; + return MEMTX_OK; } =20 static const MemoryRegionOps virt_iocsr_misc_ops =3D { - .read =3D virt_iocsr_misc_read, - .write =3D virt_iocsr_misc_write, + .read_with_attrs =3D virt_iocsr_misc_read, + .write_with_attrs =3D virt_iocsr_misc_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 4, --=20 2.34.1