From nobody Mon Nov 25 08:18:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1716248072; cv=none; d=zohomail.com; s=zohoarc; b=PLZM+cafwrGrxdAjMDD27oz0qKzNNIrRhGb6g58656Tl4qzoPi/Vz9bHFT3/lMcFGOBuB/Q27dTWwq0QfKKoZdIGVs0LP6cKbFfxJNXyvMyI1IMH1cjO70ITn6T4UFtuvD1wuxnJ6jWhJ5S/5ycITiaHdgMdqEXgW1hL1z0xyIs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716248072; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=lR1AKulc+PyyuuIw1+eePac8yeo7uus1uVSf5soatpY=; b=IYJ5/vB4+NspiVgYYZEM7uTmsfMvmj/7wtaSiF/JfLZi+vIQQo905TLhIDjhkl94syJV+32ydY7zFZJ5WLiULZ1P+EiMqUmNbQBYCcn6nMC8UUp+4LB7kZtP8oe/yAe1Uf/lY8Im145qoAOnIYJFNv9IQWvutB90TGROaNphgsA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716248072196404.13606477720884; Mon, 20 May 2024 16:34:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s9CVy-0004zM-PH; Mon, 20 May 2024 19:33:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s9CVw-0004yJ-PE; Mon, 20 May 2024 19:33:56 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s9CVt-0001c9-NR; Mon, 20 May 2024 19:33:55 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Vjv4v3c4yz6J682; Tue, 21 May 2024 07:33:03 +0800 (CST) Received: from lhrpeml500001.china.huawei.com (unknown [7.191.163.213]) by mail.maildlp.com (Postfix) with ESMTPS id 2425F1400D4; Tue, 21 May 2024 07:33:51 +0800 (CST) Received: from 00293818-MRGF.china.huawei.com (10.126.174.235) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 21 May 2024 00:33:28 +0100 To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Jonathan Cameron , Shaoqin Huang Subject: [PATCH V10 1/8] accel/kvm: Extract common KVM vCPU {creation, parking} code Date: Tue, 21 May 2024 00:32:34 +0100 Message-ID: <20240520233241.229675-2-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240520233241.229675-1-salil.mehta@huawei.com> References: <20240520233241.229675-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.174.235] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To lhrpeml500001.china.huawei.com (7.191.163.213) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716248073847100003 Content-Type: text/plain; charset="utf-8" KVM vCPU creation is done once during the vCPU realization when Qemu vCPU t= hread is spawned. This is common to all the architectures as of now. Hot-unplug of vCPU results in destruction of the vCPU object in QOM but the corresponding KVM vCPU object in the Host KVM is not destroyed as KVM doesn= 't support vCPU removal. Therefore, its representative KVM vCPU object/context= in Qemu is parked. Refactor architecture common logic so that some APIs could be reused by vCPU Hotplug code of some architectures likes ARM, Loongson etc. Update new/old = APIs with trace events. No functional change is intended here. Signed-off-by: Salil Mehta Reviewed-by: Gavin Shan Tested-by: Vishnu Pajjuri Reviewed-by: Jonathan Cameron Tested-by: Xianglai Li Tested-by: Miguel Luis Reviewed-by: Shaoqin Huang Reviewed-by: Vishnu Pajjuri Reviewed-by: Nicholas Piggin --- accel/kvm/kvm-all.c | 97 ++++++++++++++++++++++++++++-------------- accel/kvm/kvm-cpus.h | 23 ++++++++++ accel/kvm/trace-events | 5 ++- 3 files changed, 92 insertions(+), 33 deletions(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index c0be9f5eed..a8f93078dc 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -340,14 +340,73 @@ err: return ret; } =20 +void kvm_park_vcpu(CPUState *cpu) +{ + struct KVMParkedVcpu *vcpu; + + trace_kvm_park_vcpu(cpu->cpu_index, kvm_arch_vcpu_id(cpu)); + + vcpu =3D g_malloc0(sizeof(*vcpu)); + vcpu->vcpu_id =3D kvm_arch_vcpu_id(cpu); + vcpu->kvm_fd =3D cpu->kvm_fd; + QLIST_INSERT_HEAD(&kvm_state->kvm_parked_vcpus, vcpu, node); +} + +int kvm_unpark_vcpu(KVMState *s, unsigned long vcpu_id) +{ + struct KVMParkedVcpu *cpu; + + QLIST_FOREACH(cpu, &s->kvm_parked_vcpus, node) { + if (cpu->vcpu_id =3D=3D vcpu_id) { + int kvm_fd; + + trace_kvm_unpark_vcpu(vcpu_id); + + QLIST_REMOVE(cpu, node); + kvm_fd =3D cpu->kvm_fd; + g_free(cpu); + return kvm_fd; + } + } + + return -ENOENT; +} + +int kvm_create_vcpu(CPUState *cpu) +{ + unsigned long vcpu_id =3D kvm_arch_vcpu_id(cpu); + KVMState *s =3D kvm_state; + int kvm_fd; + + /* check if the KVM vCPU already exist but is parked */ + kvm_fd =3D kvm_unpark_vcpu(s, vcpu_id); + if (kvm_fd < 0) { + /* vCPU not parked: create a new KVM vCPU */ + kvm_fd =3D kvm_vm_ioctl(s, KVM_CREATE_VCPU, vcpu_id); + if (kvm_fd < 0) { + error_report("KVM_CREATE_VCPU IOCTL failed for vCPU %lu", vcpu= _id); + return kvm_fd; + } + } + + trace_kvm_create_vcpu(cpu->cpu_index, vcpu_id, kvm_fd); + + cpu->kvm_fd =3D kvm_fd; + cpu->kvm_state =3D s; + cpu->vcpu_dirty =3D true; + cpu->dirty_pages =3D 0; + cpu->throttle_us_per_full =3D 0; + + return 0; +} + static int do_kvm_destroy_vcpu(CPUState *cpu) { KVMState *s =3D kvm_state; long mmap_size; - struct KVMParkedVcpu *vcpu =3D NULL; int ret =3D 0; =20 - trace_kvm_destroy_vcpu(); + trace_kvm_destroy_vcpu(cpu->cpu_index, kvm_arch_vcpu_id(cpu)); =20 ret =3D kvm_arch_destroy_vcpu(cpu); if (ret < 0) { @@ -373,10 +432,7 @@ static int do_kvm_destroy_vcpu(CPUState *cpu) } } =20 - vcpu =3D g_malloc0(sizeof(*vcpu)); - vcpu->vcpu_id =3D kvm_arch_vcpu_id(cpu); - vcpu->kvm_fd =3D cpu->kvm_fd; - QLIST_INSERT_HEAD(&kvm_state->kvm_parked_vcpus, vcpu, node); + kvm_park_vcpu(cpu); err: return ret; } @@ -389,24 +445,6 @@ void kvm_destroy_vcpu(CPUState *cpu) } } =20 -static int kvm_get_vcpu(KVMState *s, unsigned long vcpu_id) -{ - struct KVMParkedVcpu *cpu; - - QLIST_FOREACH(cpu, &s->kvm_parked_vcpus, node) { - if (cpu->vcpu_id =3D=3D vcpu_id) { - int kvm_fd; - - QLIST_REMOVE(cpu, node); - kvm_fd =3D cpu->kvm_fd; - g_free(cpu); - return kvm_fd; - } - } - - return kvm_vm_ioctl(s, KVM_CREATE_VCPU, (void *)vcpu_id); -} - int kvm_init_vcpu(CPUState *cpu, Error **errp) { KVMState *s =3D kvm_state; @@ -415,19 +453,14 @@ int kvm_init_vcpu(CPUState *cpu, Error **errp) =20 trace_kvm_init_vcpu(cpu->cpu_index, kvm_arch_vcpu_id(cpu)); =20 - ret =3D kvm_get_vcpu(s, kvm_arch_vcpu_id(cpu)); + ret =3D kvm_create_vcpu(cpu); if (ret < 0) { - error_setg_errno(errp, -ret, "kvm_init_vcpu: kvm_get_vcpu failed (= %lu)", + error_setg_errno(errp, -ret, + "kvm_init_vcpu: kvm_create_vcpu failed (%lu)", kvm_arch_vcpu_id(cpu)); goto err; } =20 - cpu->kvm_fd =3D ret; - cpu->kvm_state =3D s; - cpu->vcpu_dirty =3D true; - cpu->dirty_pages =3D 0; - cpu->throttle_us_per_full =3D 0; - mmap_size =3D kvm_ioctl(s, KVM_GET_VCPU_MMAP_SIZE, 0); if (mmap_size < 0) { ret =3D mmap_size; diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h index ca40add32c..2e6bb38b5d 100644 --- a/accel/kvm/kvm-cpus.h +++ b/accel/kvm/kvm-cpus.h @@ -22,5 +22,28 @@ bool kvm_supports_guest_debug(void); int kvm_insert_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len); int kvm_remove_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len); void kvm_remove_all_breakpoints(CPUState *cpu); +/** + * kvm_create_vcpu - Gets a parked KVM vCPU or creates a KVM vCPU + * @cpu: QOM CPUState object for which KVM vCPU has to be fetched/created. + * + * @returns: 0 when success, errno (<0) when failed. + */ +int kvm_create_vcpu(CPUState *cpu); =20 +/** + * kvm_park_vcpu - Park QEMU KVM vCPU context + * @cpu: QOM CPUState object for which QEMU KVM vCPU context has to be par= ked. + * + * @returns: none + */ +void kvm_park_vcpu(CPUState *cpu); + +/** + * kvm_unpark_vcpu - unpark QEMU KVM vCPU context + * @s: KVM State + * @cpu: Architecture vCPU ID of the parked vCPU + * + * @returns: KVM fd + */ +int kvm_unpark_vcpu(KVMState *s, unsigned long vcpu_id); #endif /* KVM_CPUS_H */ diff --git a/accel/kvm/trace-events b/accel/kvm/trace-events index 681ccb667d..bd43a0ef26 100644 --- a/accel/kvm/trace-events +++ b/accel/kvm/trace-events @@ -9,6 +9,10 @@ kvm_device_ioctl(int fd, int type, void *arg) "dev fd %d, = type 0x%x, arg %p" kvm_failed_reg_get(uint64_t id, const char *msg) "Warning: Unable to retri= eve ONEREG %" PRIu64 " from KVM: %s" kvm_failed_reg_set(uint64_t id, const char *msg) "Warning: Unable to set O= NEREG %" PRIu64 " to KVM: %s" kvm_init_vcpu(int cpu_index, unsigned long arch_cpu_id) "index: %d id: %lu" +kvm_create_vcpu(int cpu_index, unsigned long arch_cpu_id, int kvm_fd) "ind= ex: %d, id: %lu, kvm fd: %d" +kvm_destroy_vcpu(int cpu_index, unsigned long arch_cpu_id) "index: %d id: = %lu" +kvm_park_vcpu(int cpu_index, unsigned long arch_cpu_id) "index: %d id: %lu" +kvm_unpark_vcpu(unsigned long arch_cpu_id) "id: %lu" kvm_irqchip_commit_routes(void) "" kvm_irqchip_add_msi_route(char *name, int vector, int virq) "dev %s vector= %d virq %d" kvm_irqchip_update_msi_route(int virq) "Updating MSI route virq=3D%d" @@ -25,7 +29,6 @@ kvm_dirty_ring_reaper(const char *s) "%s" kvm_dirty_ring_reap(uint64_t count, int64_t t) "reaped %"PRIu64" pages (to= ok %"PRIi64" us)" kvm_dirty_ring_reaper_kick(const char *reason) "%s" kvm_dirty_ring_flush(int finished) "%d" -kvm_destroy_vcpu(void) "" kvm_failed_get_vcpu_mmap_size(void) "" kvm_cpu_exec(void) "" kvm_interrupt_exit_request(void) "" --=20 2.34.1 From nobody Mon Nov 25 08:18:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 21 May 2024 07:30:38 +0800 (CST) Received: from lhrpeml500001.china.huawei.com (unknown [7.191.163.213]) by mail.maildlp.com (Postfix) with ESMTPS id BCD7B140B35; Tue, 21 May 2024 07:34:13 +0800 (CST) Received: from 00293818-MRGF.china.huawei.com (10.126.174.235) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 21 May 2024 00:33:51 +0100 To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Jonathan Cameron , Shaoqin Huang Subject: [PATCH V10 2/8] hw/acpi: Move CPU ctrl-dev MMIO region len macro to common header file Date: Tue, 21 May 2024 00:32:35 +0100 Message-ID: <20240520233241.229675-3-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240520233241.229675-1-salil.mehta@huawei.com> References: <20240520233241.229675-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.174.235] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To lhrpeml500001.china.huawei.com (7.191.163.213) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716248111939100007 CPU ctrl-dev MMIO region length could be used in ACPI GED and various other architecture specific places. Move ACPI_CPU_HOTPLUG_REG_LEN macro to more appropriate common header file. Signed-off-by: Salil Mehta Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Jonathan Cameron Reviewed-by: Gavin Shan Reviewed-by: David Hildenbrand Reviewed-by: Shaoqin Huang Tested-by: Vishnu Pajjuri Tested-by: Xianglai Li Tested-by: Miguel Luis --- hw/acpi/cpu.c | 2 +- include/hw/acpi/cpu_hotplug.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 2d81c1e790..69aaa563db 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -1,13 +1,13 @@ #include "qemu/osdep.h" #include "migration/vmstate.h" #include "hw/acpi/cpu.h" +#include "hw/acpi/cpu_hotplug.h" #include "hw/core/cpu.h" #include "qapi/error.h" #include "qapi/qapi-events-acpi.h" #include "trace.h" #include "sysemu/numa.h" =20 -#define ACPI_CPU_HOTPLUG_REG_LEN 12 #define ACPI_CPU_SELECTOR_OFFSET_WR 0 #define ACPI_CPU_FLAGS_OFFSET_RW 4 #define ACPI_CPU_CMD_OFFSET_WR 5 diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h index 3b932abbbb..48b291e45e 100644 --- a/include/hw/acpi/cpu_hotplug.h +++ b/include/hw/acpi/cpu_hotplug.h @@ -19,6 +19,8 @@ #include "hw/hotplug.h" #include "hw/acpi/cpu.h" =20 +#define ACPI_CPU_HOTPLUG_REG_LEN 12 + typedef struct AcpiCpuHotplug { Object *device; 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Tue, 21 May 2024 07:33:48 +0800 (CST) Received: from lhrpeml500001.china.huawei.com (unknown [7.191.163.213]) by mail.maildlp.com (Postfix) with ESMTPS id 74A631400D4; Tue, 21 May 2024 07:34:36 +0800 (CST) Received: from 00293818-MRGF.china.huawei.com (10.126.174.235) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 21 May 2024 00:34:14 +0100 To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Jonathan Cameron , Shaoqin Huang Subject: [PATCH V10 3/8] hw/acpi: Update ACPI GED framework to support vCPU Hotplug Date: Tue, 21 May 2024 00:32:36 +0100 Message-ID: <20240520233241.229675-4-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240520233241.229675-1-salil.mehta@huawei.com> References: <20240520233241.229675-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.174.235] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To lhrpeml500001.china.huawei.com (7.191.163.213) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716248109979100003 Content-Type: text/plain; charset="utf-8" ACPI GED (as described in the ACPI 6.4 spec) uses an interrupt listed in the _CRS object of GED to intimate OSPM about an event. Later then demultiplexe= s the notified event by evaluating ACPI _EVT method to know the type of event. Use ACPI GED to also notify the guest kernel about any CPU hot(un)plug events. ACPI CPU hotplug related initialization should only happen if ACPI_CPU_HOTP= LUG support has been enabled for particular architecture. Add cpu_hotplug_hw_in= it() stub to avoid compilation break. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta Reviewed-by: Jonathan Cameron Reviewed-by: Gavin Shan Reviewed-by: David Hildenbrand Reviewed-by: Shaoqin Huang Tested-by: Vishnu Pajjuri Tested-by: Xianglai Li Tested-by: Miguel Luis Reviewed-by: Vishnu Pajjuri --- hw/acpi/acpi-cpu-hotplug-stub.c | 6 ++++++ hw/acpi/cpu.c | 6 +++++- hw/acpi/generic_event_device.c | 17 +++++++++++++++++ include/hw/acpi/generic_event_device.h | 4 ++++ 4 files changed, 32 insertions(+), 1 deletion(-) diff --git a/hw/acpi/acpi-cpu-hotplug-stub.c b/hw/acpi/acpi-cpu-hotplug-stu= b.c index 3fc4b14c26..c6c61bb9cd 100644 --- a/hw/acpi/acpi-cpu-hotplug-stub.c +++ b/hw/acpi/acpi-cpu-hotplug-stub.c @@ -19,6 +19,12 @@ void legacy_acpi_cpu_hotplug_init(MemoryRegion *parent, = Object *owner, return; } =20 +void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner, + CPUHotplugState *state, hwaddr base_addr) +{ + return; +} + void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list) { return; diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 69aaa563db..473b37ba88 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -221,7 +221,11 @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *own= er, const CPUArchIdList *id_list; int i; =20 - assert(mc->possible_cpu_arch_ids); + /* hotplug might not be available for all types like x86/microvm etc. = */ + if (!mc->possible_cpu_arch_ids) { + return; + } + id_list =3D mc->possible_cpu_arch_ids(machine); state->dev_count =3D id_list->len; state->devs =3D g_new0(typeof(*state->devs), state->dev_count); diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 2d6e91b124..54d3b4bf9d 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -12,6 +12,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/acpi/acpi.h" +#include "hw/acpi/cpu.h" #include "hw/acpi/generic_event_device.h" #include "hw/irq.h" #include "hw/mem/pc-dimm.h" @@ -25,6 +26,7 @@ static const uint32_t ged_supported_events[] =3D { ACPI_GED_MEM_HOTPLUG_EVT, ACPI_GED_PWR_DOWN_EVT, ACPI_GED_NVDIMM_HOTPLUG_EVT, + ACPI_GED_CPU_HOTPLUG_EVT, }; =20 /* @@ -234,6 +236,8 @@ static void acpi_ged_device_plug_cb(HotplugHandler *hot= plug_dev, } else { acpi_memory_plug_cb(hotplug_dev, &s->memhp_state, dev, errp); } + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { + acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); } else { error_setg(errp, "virt: device plug request for unsupported device" " type: %s", object_get_typename(OBJECT(dev))); @@ -248,6 +252,8 @@ static void acpi_ged_unplug_request_cb(HotplugHandler *= hotplug_dev, if ((object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && !(object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)))) { acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev, e= rrp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { + acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp= ); } else { error_setg(errp, "acpi: device unplug request for unsupported devi= ce" " type: %s", object_get_typename(OBJECT(dev))); @@ -261,6 +267,8 @@ static void acpi_ged_unplug_cb(HotplugHandler *hotplug_= dev, =20 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { acpi_memory_unplug_cb(&s->memhp_state, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { + acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); } else { error_setg(errp, "acpi: device unplug for unsupported device" " type: %s", object_get_typename(OBJECT(dev))); @@ -272,6 +280,7 @@ static void acpi_ged_ospm_status(AcpiDeviceIf *adev, AC= PIOSTInfoList ***list) AcpiGedState *s =3D ACPI_GED(adev); =20 acpi_memory_ospm_status(&s->memhp_state, list); + acpi_cpu_ospm_status(&s->cpuhp_state, list); } =20 static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev) @@ -286,6 +295,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, Acp= iEventStatusBits ev) sel =3D ACPI_GED_PWR_DOWN_EVT; } else if (ev & ACPI_NVDIMM_HOTPLUG_STATUS) { sel =3D ACPI_GED_NVDIMM_HOTPLUG_EVT; + } else if (ev & ACPI_CPU_HOTPLUG_STATUS) { + sel =3D ACPI_GED_CPU_HOTPLUG_EVT; } else { /* Unknown event. Return without generating interrupt. */ warn_report("GED: Unsupported event %d. No irq injected", ev); @@ -400,6 +411,12 @@ static void acpi_ged_initfn(Object *obj) memory_region_init_io(&ged_st->regs, obj, &ged_regs_ops, ged_st, TYPE_ACPI_GED "-regs", ACPI_GED_REG_COUNT); sysbus_init_mmio(sbd, &ged_st->regs); + + memory_region_init(&s->container_cpuhp, OBJECT(dev), "cpuhp container", + ACPI_CPU_HOTPLUG_REG_LEN); + sysbus_init_mmio(sbd, &s->container_cpuhp); + cpu_hotplug_hw_init(&s->container_cpuhp, OBJECT(dev), + &s->cpuhp_state, 0); } =20 static void acpi_ged_class_init(ObjectClass *class, void *data) diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/gener= ic_event_device.h index ba84ce0214..90fc41cbb8 100644 --- a/include/hw/acpi/generic_event_device.h +++ b/include/hw/acpi/generic_event_device.h @@ -60,6 +60,7 @@ #define HW_ACPI_GENERIC_EVENT_DEVICE_H =20 #include "hw/sysbus.h" +#include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/ghes.h" #include "qom/object.h" @@ -95,6 +96,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED) #define ACPI_GED_MEM_HOTPLUG_EVT 0x1 #define ACPI_GED_PWR_DOWN_EVT 0x2 #define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4 +#define ACPI_GED_CPU_HOTPLUG_EVT 0x8 =20 typedef struct GEDState { MemoryRegion evt; @@ -106,6 +108,8 @@ struct AcpiGedState { SysBusDevice parent_obj; MemHotplugState memhp_state; MemoryRegion container_memhp; + CPUHotplugState cpuhp_state; + MemoryRegion container_cpuhp; GEDState ged_state; uint32_t ged_event_bitmap; qemu_irq irq; --=20 2.34.1 From nobody Mon Nov 25 08:18:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1716248125; cv=none; d=zohomail.com; s=zohoarc; b=IWMAPsus6SAu31f5NPHXVnv+6T4VxT5jFDdEcyanR9wHV/l79SfkGoxC4pDooF7O8CLmf+uUtaWTWCSUNaCxqSXbcTc0sXYt1wgr6X85zunuwSIg+GMU2QQDuEv7HlkITtz3dRJX814cvwESX34dtIKewoGgsjMoLG8EGZ8nHyk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716248125; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Mon, 20 May 2024 19:35:06 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Vjv2m41Wyz6K6jV; Tue, 21 May 2024 07:31:12 +0800 (CST) Received: from lhrpeml500001.china.huawei.com (unknown [7.191.163.213]) by mail.maildlp.com (Postfix) with ESMTPS id 25A5F1400D4; Tue, 21 May 2024 07:34:59 +0800 (CST) Received: from 00293818-MRGF.china.huawei.com (10.126.174.235) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 21 May 2024 00:34:36 +0100 To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Jonathan Cameron , Shaoqin Huang Subject: [PATCH V10 4/8] hw/acpi: Update GED _EVT method AML with CPU scan Date: Tue, 21 May 2024 00:32:37 +0100 Message-ID: <20240520233241.229675-5-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240520233241.229675-1-salil.mehta@huawei.com> References: <20240520233241.229675-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.174.235] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To lhrpeml500001.china.huawei.com (7.191.163.213) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716248128079100003 Content-Type: text/plain; charset="utf-8" OSPM evaluates _EVT method to map the event. The CPU hotplug event eventual= ly results in start of the CPU scan. Scan figures out the CPU and the kind of event(plug/unplug) and notifies it back to the guest. Update the GED AML _E= VT method with the call to \\_SB.CPUS.CSCN Also, macro CPU_SCAN_METHOD might be referred in other places like during G= ED intialization so it makes sense to have its definition placed in some common header file like cpu_hotplug.h. But doing this can cause compilation break because of the conflicting macro definitions present in cpu.c and cpu_hotpl= ug.c and because both these files get compiled due to historic reasons of x86 wo= rld i.e. decision to use legacy(GPE.2)/modern(GED) CPU hotplug interface happens during runtime [1]. To mitigate above, for now, declare a new common macro ACPI_CPU_SCAN_METHOD for CPU scan method instead. (This needs a separate discussion later on for clean-up) Reference: [1] https://lore.kernel.org/qemu-devel/1463496205-251412-24-git-send-email-= imammedo@redhat.com/ Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta Reviewed-by: Jonathan Cameron Reviewed-by: Gavin Shan Tested-by: Vishnu Pajjuri Tested-by: Xianglai Li Tested-by: Miguel Luis Reviewed-by: Shaoqin Huang --- hw/acpi/cpu.c | 2 +- hw/acpi/generic_event_device.c | 4 ++++ include/hw/acpi/cpu_hotplug.h | 2 ++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 473b37ba88..af2b6655d2 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -327,7 +327,7 @@ const VMStateDescription vmstate_cpu_hotplug =3D { #define CPUHP_RES_DEVICE "PRES" #define CPU_LOCK "CPLK" #define CPU_STS_METHOD "CSTA" -#define CPU_SCAN_METHOD "CSCN" +#define CPU_SCAN_METHOD ACPI_CPU_SCAN_METHOD #define CPU_NOTIFY_METHOD "CTFY" #define CPU_EJECT_METHOD "CEJ0" #define CPU_OST_METHOD "COST" diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 54d3b4bf9d..63226b0040 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -109,6 +109,10 @@ void build_ged_aml(Aml *table, const char *name, Hotpl= ugHandler *hotplug_dev, aml_append(if_ctx, aml_call0(MEMORY_DEVICES_CONTAINER "." MEMORY_SLOT_SCAN_METHOD)); break; + case ACPI_GED_CPU_HOTPLUG_EVT: + aml_append(if_ctx, aml_call0(ACPI_CPU_CONTAINER "." + ACPI_CPU_SCAN_METHOD)); + break; case ACPI_GED_PWR_DOWN_EVT: aml_append(if_ctx, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h index 48b291e45e..ef631750b4 100644 --- a/include/hw/acpi/cpu_hotplug.h +++ b/include/hw/acpi/cpu_hotplug.h @@ -20,6 +20,8 @@ #include "hw/acpi/cpu.h" =20 #define ACPI_CPU_HOTPLUG_REG_LEN 12 +#define ACPI_CPU_SCAN_METHOD "CSCN" +#define ACPI_CPU_CONTAINER "\\_SB.CPUS" =20 typedef struct AcpiCpuHotplug { Object *device; --=20 2.34.1 From nobody Mon Nov 25 08:18:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; 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Tue, 21 May 2024 07:35:22 +0800 (CST) Received: from 00293818-MRGF.china.huawei.com (10.126.174.235) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 21 May 2024 00:34:59 +0100 To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Jonathan Cameron , Shaoqin Huang Subject: [PATCH V10 5/8] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Date: Tue, 21 May 2024 00:32:38 +0100 Message-ID: <20240520233241.229675-6-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240520233241.229675-1-salil.mehta@huawei.com> References: <20240520233241.229675-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.174.235] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To lhrpeml500001.china.huawei.com (7.191.163.213) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716248140059100001 Content-Type: text/plain; charset="utf-8" CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is IO p= ort based and existing CPUs AML code assumes _CRS objects would evaluate to a s= ystem resource which describes IO Port address. But on ARM arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence _CRS object sh= ould evaluate to system resource which describes memory-mapped base address. Upd= ate build CPUs AML function to accept both IO/MEMORY region spaces and accordin= gly update the _CRS object. On x86, CPU Hotplug uses Generic ACPI GPE Block Bit 2 (GPE.2) event handler= to notify OSPM about any CPU hot(un)plug events. Latest CPU Hotplug is based on ACPI Generic Event Device framework and uses ACPI GED device for the same. = Not all architectures support GPE based CPU Hotplug event handler. Hence, make = AML for GPE.2 event handler conditional. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta Reviewed-by: Gavin Shan Tested-by: Vishnu Pajjuri Reviewed-by: Jonathan Cameron Tested-by: Xianglai Li Tested-by: Miguel Luis Reviewed-by: Shaoqin Huang --- hw/acpi/cpu.c | 23 ++++++++++++++++------- hw/i386/acpi-build.c | 3 ++- include/hw/acpi/cpu.h | 5 +++-- 3 files changed, 21 insertions(+), 10 deletions(-) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index af2b6655d2..4c63514b16 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -343,9 +343,10 @@ const VMStateDescription vmstate_cpu_hotplug =3D { #define CPU_FW_EJECT_EVENT "CEJF" =20 void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures = opts, - build_madt_cpu_fn build_madt_cpu, hwaddr io_base, + build_madt_cpu_fn build_madt_cpu, hwaddr base_addr, const char *res_root, - const char *event_handler_method) + const char *event_handler_method, + AmlRegionSpace rs) { Aml *ifctx; Aml *field; @@ -370,13 +371,19 @@ void build_cpus_aml(Aml *table, MachineState *machine= , CPUHotplugFeatures opts, aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0)); =20 crs =3D aml_resource_template(); - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1, + if (rs =3D=3D AML_SYSTEM_IO) { + aml_append(crs, aml_io(AML_DECODE16, base_addr, base_addr, 1, ACPI_CPU_HOTPLUG_REG_LEN)); + } else { + aml_append(crs, aml_memory32_fixed(base_addr, + ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE)); + } + aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs)); =20 /* declare CPU hotplug MMIO region with related access fields */ aml_append(cpu_ctrl_dev, - aml_operation_region("PRST", AML_SYSTEM_IO, aml_int(io_base), + aml_operation_region("PRST", rs, aml_int(base_addr), ACPI_CPU_HOTPLUG_REG_LEN)); =20 field =3D aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, @@ -700,9 +707,11 @@ void build_cpus_aml(Aml *table, MachineState *machine,= CPUHotplugFeatures opts, aml_append(sb_scope, cpus_dev); aml_append(table, sb_scope); =20 - method =3D aml_method(event_handler_method, 0, AML_NOTSERIALIZED); - aml_append(method, aml_call0("\\_SB.CPUS." CPU_SCAN_METHOD)); - aml_append(table, method); + if (event_handler_method) { + method =3D aml_method(event_handler_method, 0, AML_NOTSERIALIZED); + aml_append(method, aml_call0("\\_SB.CPUS." CPU_SCAN_METHOD)); + aml_append(table, method); + } =20 g_free(cphp_res_path); } diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 53f804ac16..b73b136605 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1537,7 +1537,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, .fw_unplugs_cpu =3D pm->smi_on_cpu_unplug, }; build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry, - pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02"); + pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02", + AML_SYSTEM_IO); } =20 if (pcms->memhp_io_base && nr_mem) { diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index e6e1a9ef59..48cded697c 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -61,9 +61,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const CPUArch= IdList *apic_ids, GArray *entry, bool force_enabled); =20 void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures = opts, - build_madt_cpu_fn build_madt_cpu, hwaddr io_base, + build_madt_cpu_fn build_madt_cpu, hwaddr base_addr, const char *res_root, - const char *event_handler_method); + const char *event_handler_method, + AmlRegionSpace rs); =20 void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list= ); =20 --=20 2.34.1 From nobody Mon Nov 25 08:18:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1716248164; cv=none; d=zohomail.com; s=zohoarc; b=bvPgXTne8ZB0VjOulpLWB/6MLG9tHovq2g6sQCEbtjtDtzMz1GLNxMVt9P9bcXlqn1rNaDU9K8AdZ5L0NazC1F5xgBZHqvtJq+lm8wv+lSzqyyrjxPm31N6cNErnxauXB/vTGGUhHwA1TDuFwG7a2QwR9YaOezoaknYcXRpEiCU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716248164; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Mon, 20 May 2024 19:35:48 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Vjv744rVsz6J7L4; Tue, 21 May 2024 07:34:56 +0800 (CST) Received: from lhrpeml500001.china.huawei.com (unknown [7.191.163.213]) by mail.maildlp.com (Postfix) with ESMTPS id 4F9F3140516; Tue, 21 May 2024 07:35:44 +0800 (CST) Received: from 00293818-MRGF.china.huawei.com (10.126.174.235) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 21 May 2024 00:35:22 +0100 To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Shaoqin Huang Subject: [PATCH V10 6/8] physmem: Add helper function to destroy CPU AddressSpace Date: Tue, 21 May 2024 00:32:39 +0100 Message-ID: <20240520233241.229675-7-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240520233241.229675-1-salil.mehta@huawei.com> References: <20240520233241.229675-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.174.235] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To lhrpeml500001.china.huawei.com (7.191.163.213) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716248166158100003 Content-Type: text/plain; charset="utf-8" Virtual CPU Hot-unplug leads to unrealization of a CPU object. This also involves destruction of the CPU AddressSpace. Add common function to help destroy the CPU AddressSpace. Signed-off-by: Salil Mehta Tested-by: Vishnu Pajjuri Reviewed-by: Gavin Shan Tested-by: Xianglai Li Tested-by: Miguel Luis Reviewed-by: Shaoqin Huang --- include/exec/cpu-common.h | 8 ++++++++ include/hw/core/cpu.h | 1 + system/physmem.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 815342d043..240ee04369 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -129,6 +129,14 @@ size_t qemu_ram_pagesize_largest(void); */ void cpu_address_space_init(CPUState *cpu, int asidx, const char *prefix, MemoryRegion *mr); +/** + * cpu_address_space_destroy: + * @cpu: CPU for which address space needs to be destroyed + * @asidx: integer index of this address space + * + * Note that with KVM only one address space is supported. + */ +void cpu_address_space_destroy(CPUState *cpu, int asidx); =20 void cpu_physical_memory_rw(hwaddr addr, void *buf, hwaddr len, bool is_write); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index bb398e8237..60b160d0b4 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -486,6 +486,7 @@ struct CPUState { QSIMPLEQ_HEAD(, qemu_work_item) work_list; =20 struct CPUAddressSpace *cpu_ases; + int cpu_ases_count; int num_ases; AddressSpace *as; MemoryRegion *memory; diff --git a/system/physmem.c b/system/physmem.c index 342b7a8fd4..146f17826a 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -763,6 +763,7 @@ void cpu_address_space_init(CPUState *cpu, int asidx, =20 if (!cpu->cpu_ases) { cpu->cpu_ases =3D g_new0(CPUAddressSpace, cpu->num_ases); + cpu->cpu_ases_count =3D cpu->num_ases; } =20 newas =3D &cpu->cpu_ases[asidx]; @@ -776,6 +777,34 @@ void cpu_address_space_init(CPUState *cpu, int asidx, } } =20 +void cpu_address_space_destroy(CPUState *cpu, int asidx) +{ + CPUAddressSpace *cpuas; + + assert(cpu->cpu_ases); + assert(asidx >=3D 0 && asidx < cpu->num_ases); + /* KVM cannot currently support multiple address spaces. */ + assert(asidx =3D=3D 0 || !kvm_enabled()); + + cpuas =3D &cpu->cpu_ases[asidx]; + if (tcg_enabled()) { + memory_listener_unregister(&cpuas->tcg_as_listener); + } + + address_space_destroy(cpuas->as); + g_free_rcu(cpuas->as, rcu); + + if (asidx =3D=3D 0) { + /* reset the convenience alias for address space 0 */ + cpu->as =3D NULL; + } + + if (--cpu->cpu_ases_count =3D=3D 0) { + g_free(cpu->cpu_ases); + cpu->cpu_ases =3D NULL; + } +} + AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx) { /* Return the AddressSpace corresponding to the specified index */ --=20 2.34.1 From nobody Mon Nov 25 08:18:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1716248175; cv=none; d=zohomail.com; s=zohoarc; b=VtsZyWzl/+QvvOWDIHzDeJ1yC1E0YdaXse/bbkIJogyy5X67E7j4LRjkjgWXwlrZrTayz3QQUHCcCGUZrf1y3joc7WIK5EGjiAjdajM5uob3sFTUzizSLpjXWksBE4ms3/FE0t6+GA3FreDVKdY4rfWtWOLX77wh/cMXBcdpT24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Tue, 21 May 2024 00:35:44 +0100 To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Shaoqin Huang Subject: [PATCH V10 7/8] gdbstub: Add helper function to unregister GDB register space Date: Tue, 21 May 2024 00:32:40 +0100 Message-ID: <20240520233241.229675-8-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240520233241.229675-1-salil.mehta@huawei.com> References: <20240520233241.229675-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.174.235] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To lhrpeml500001.china.huawei.com (7.191.163.213) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716248176197100003 Content-Type: text/plain; charset="utf-8" Add common function to help unregister the GDB register space. This shall be done in context to the CPU unrealization. Signed-off-by: Salil Mehta Tested-by: Vishnu Pajjuri Reviewed-by: Gavin Shan Tested-by: Xianglai Li Tested-by: Miguel Luis Reviewed-by: Shaoqin Huang Reviewed-by: Vishnu Pajjuri --- gdbstub/gdbstub.c | 13 +++++++++++++ hw/core/cpu-common.c | 1 - include/exec/gdbstub.h | 6 ++++++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index b3574997ea..1949b09240 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -617,6 +617,19 @@ void gdb_register_coprocessor(CPUState *cpu, } } =20 +void gdb_unregister_coprocessor_all(CPUState *cpu) +{ + /* + * Safe to nuke everything. GDBRegisterState::xml is static const char= so + * it won't be freed + */ + g_array_free(cpu->gdb_regs, true); + + cpu->gdb_regs =3D NULL; + cpu->gdb_num_regs =3D 0; + cpu->gdb_num_g_regs =3D 0; +} + static void gdb_process_breakpoint_remove_all(GDBProcess *p) { CPUState *cpu =3D gdb_get_first_cpu_in_process(p); diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 0f0a247f56..e5140b4bc1 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -274,7 +274,6 @@ static void cpu_common_finalize(Object *obj) { CPUState *cpu =3D CPU(obj); =20 - g_array_free(cpu->gdb_regs, TRUE); qemu_lockcnt_destroy(&cpu->in_ioctl_lock); qemu_mutex_destroy(&cpu->work_mutex); } diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index eb14b91139..249d4d4bc8 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -49,6 +49,12 @@ void gdb_register_coprocessor(CPUState *cpu, gdb_get_reg_cb get_reg, gdb_set_reg_cb set_r= eg, const GDBFeature *feature, int g_pos); =20 +/** + * gdb_unregister_coprocessor_all() - unregisters supplemental set of regi= sters + * @cpu - the CPU associated with registers + */ +void gdb_unregister_coprocessor_all(CPUState *cpu); + /** * gdbserver_start: start the gdb server * @port_or_device: connection spec for gdb --=20 2.34.1 From nobody Mon Nov 25 08:18:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1716248228; cv=none; d=zohomail.com; s=zohoarc; b=jJXIxx27tcRjcZbI3l3YmkpALeM0JugwyKmO19IOgBO6RWcA9S4MCnyL8iVzAqWkr49TolX/rsKNH7UbkcSj04SBSjs/QbK+5m7GmpYF8F01lLM7rtCMFzg71kn0tcNUVqJ3p1VAddE0cyl+lywjED5oLC9Gzk/PJGIsbN98ERw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716248228; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Mon, 20 May 2024 19:36:31 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Vjv7w3Kg4z6J682; Tue, 21 May 2024 07:35:40 +0800 (CST) Received: from lhrpeml500001.china.huawei.com (unknown [7.191.163.213]) by mail.maildlp.com (Postfix) with ESMTPS id 1D09E140516; Tue, 21 May 2024 07:36:28 +0800 (CST) Received: from 00293818-MRGF.china.huawei.com (10.126.174.235) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 21 May 2024 00:36:06 +0100 To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH V10 8/8] docs/specs/acpi_hw_reduced_hotplug: Add the CPU Hotplug Event Bit Date: Tue, 21 May 2024 00:32:41 +0100 Message-ID: <20240520233241.229675-9-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240520233241.229675-1-salil.mehta@huawei.com> References: <20240520233241.229675-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.174.235] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To lhrpeml500001.china.huawei.com (7.191.163.213) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716248230367100003 Content-Type: text/plain; charset="utf-8" GED interface is used by many hotplug events like memory hotplug, NVDIMM ho= tplug and non-hotplug events like system power down event. Each of these can be selected using a bit in the 32 bit GED IO interface. A bit has been reserve= d for the CPU hotplug event. Signed-off-by: Salil Mehta Reviewed-by: Gavin Shan --- docs/specs/acpi_hw_reduced_hotplug.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/specs/acpi_hw_reduced_hotplug.rst b/docs/specs/acpi_hw_re= duced_hotplug.rst index 0bd3f9399f..3acd6fcd8b 100644 --- a/docs/specs/acpi_hw_reduced_hotplug.rst +++ b/docs/specs/acpi_hw_reduced_hotplug.rst @@ -64,7 +64,8 @@ GED IO interface (4 byte access) 0: Memory hotplug event 1: System power down event 2: NVDIMM hotplug event - 3-31: Reserved + 3: CPU hotplug event + 4-31: Reserved =20 **write_access:** =20 --=20 2.34.1