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Thu, 16 May 2024 05:34:09 -0700 (PDT) From: Jerry Zhang Jian To: alistair.francis@wdc.com, palmer@dabbelt.com, frank.chang@sifive.com, max.chou@sifive.com, paul.walmsley@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Jerry Zhang Jian Subject: [PATCH] target/riscv: zvbb implies zvkb Date: Thu, 16 May 2024 20:33:36 +0800 Message-ID: <20240516123336.63534-1-jerry.zhangjian@sifive.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=jerry.zhangjian@sifive.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1715862922889100003 Content-Type: text/plain; charset="utf-8" - According to RISC-V crypto spec, Zvkb extension is a proper subset of the= Zvbb extension. - Reference: https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e= 0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=3D1#L10 Signed-off-by: Jerry Zhang Jian Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/tcg/tcg-cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 40054a391a..f1a1306ab2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -658,6 +658,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); } =20 + if (cpu->cfg.ext_zvbb) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); + } + /* * In principle Zve*x would also suffice here, were they supported * in qemu --=20 2.42.0