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b=e0ZNFl4+kkfE0VAjYQR11Qk1hS3r9gs0KYYB7dSJ6YxQYf/q4XTADsCgYRagEEWJvvt9 F2yR3pr0b+9VRr3bM35UyzOoZD8+3HurQZ3A6NMzyb0Ef5+7Pjr1AkNiIi413olJW0Vr 8MoMaIJvcSlneKN9spzRogDjk/zwNKP7yX1ylj6+VTZLP4kRMs0Il97YBm9e6jsqDZ20 MwviSkbQsbom/a1dPSLGHgF6d9BPD3Kq4pPdh+1hA6o84H3PGKX1x0+Qwuo+POjX8DY2 11+C7Z8UTiW77L0/kouyrjHWE1v5685QgbNGXmtVaRfGGTWSQQAP2v1KBZ/fZWVovKKy vA== From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com, chalapathi.v@linux.ibm.com, saif.abrar@linux.vnet.ibm.com, dantan@us.ibm.com, milesg@linux.vnet.ibm.com Subject: [PATCH v3 4/5] hw/ppc: SPI controller wiring to P10 chip Date: Wed, 15 May 2024 12:41:48 -0500 Message-Id: <20240515174149.17713-5-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240515174149.17713-1-chalapathi.v@linux.ibm.com> References: <20240515174149.17713-1-chalapathi.v@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: LSVk2wWVaXNYga3QCqVSXnmRWnCX8eCQ X-Proofpoint-GUID: tr2dOtYwDX5omusT-wvcszu2dMdQl5eC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-15_10,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=736 spamscore=0 mlxscore=0 adultscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405150125 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=chalapathi.v@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1715795054496100004 Content-Type: text/plain; charset="utf-8" In this commit, create SPI controller on p10 chip and connect cs irq. The QOM tree of spi controller and seeprom are. /machine (powernv10-machine) /chip[0] (power10_v2.0-pnv-chip) /pib_spic[2] (pnv-spi-controller) /pnv-spi-bus.2 (SSI) /xscom-spi-controller-regs[0] (memory-region) /machine (powernv10-machine) /peripheral-anon (container) /device[0] (25csm04) /WP#[0] (irq) /ssi-gpio-cs[0] (irq) (qemu) qom-get /machine/peripheral-anon /device[76] "parent_bus" "/machine/chip[0]/pib_spic[2]/pnv-spi-bus.2" Signed-off-by: Chalapathi V Reviewed-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv_chip.h | 3 +++ hw/ppc/pnv.c | 21 ++++++++++++++++++++- hw/ppc/pnv_spi_controller.c | 8 ++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 8589f3291e..d464858f79 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -6,6 +6,7 @@ #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_homer.h" #include "hw/ppc/pnv_n1_chiplet.h" +#include "hw/ssi/pnv_spi.h" #include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_occ.h" #include "hw/ppc/pnv_psi.h" @@ -118,6 +119,8 @@ struct Pnv10Chip { PnvSBE sbe; PnvHomer homer; PnvN1Chiplet n1_chiplet; +#define PNV10_CHIP_MAX_PIB_SPIC 6 + PnvSpiController pib_spic[PNV10_CHIP_MAX_PIB_SPIC]; =20 uint32_t nr_quads; PnvQuad *quads; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 6e3a5ccdec..6850592a85 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1829,6 +1829,11 @@ static void pnv_chip_power10_instance_init(Object *o= bj) for (i =3D 0; i < pcc->i2c_num_engines; i++) { object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I= 2C); } + + for (i =3D 0; i < PNV10_CHIP_MAX_PIB_SPIC ; i++) { + object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i], + TYPE_PNV_SPI_CONTROLLER); + } } =20 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) @@ -2043,7 +2048,21 @@ static void pnv_chip_power10_realize(DeviceState *de= v, Error **errp) qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_SBE_I2C)); } - + /* PIB SPI Controller */ + for (i =3D 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { + object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num", + i, &error_fatal); + /* pib_spic[2] connected to 25csm04 which implements 1 byte transf= er */ + object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_le= n", + (i =3D=3D 2) ? 1 : 4, &error_fatal); + if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT + (&chip10->pib_spic[i])), errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE + + i * PNV10_XSCOM_PIB_SPIC_SIZE, + &chip10->pib_spic[i].xscom_spic_regs); + } } =20 static void pnv_rainier_i2c_init(PnvMachineState *pnv) diff --git a/hw/ppc/pnv_spi_controller.c b/hw/ppc/pnv_spi_controller.c index e87f583074..3d47e932de 100644 --- a/hw/ppc/pnv_spi_controller.c +++ b/hw/ppc/pnv_spi_controller.c @@ -1067,9 +1067,17 @@ static void operation_sequencer(PnvSpiController *s) static void do_reset(DeviceState *dev) { PnvSpiController *s =3D PNV_SPICONTROLLER(dev); + DeviceState *ssi_dev; =20 trace_pnv_spi_reset(); =20 + /* Connect cs irq */ + ssi_dev =3D ssi_get_cs(s->ssi_bus, 0); + if (ssi_dev) { + qemu_irq cs_line =3D qdev_get_gpio_in_named(ssi_dev, SSI_GPIO_CS, = 0); + qdev_connect_gpio_out_named(DEVICE(s), "cs", 0, cs_line); + } + /* Reset all N1 and N2 counters, and other constants */ s->N2_bits =3D 0; s->N2_bytes =3D 0; --=20 2.39.3