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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f4d2af2bafsm10389060b3a.162.2024.05.15.00.48.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 00:48:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1715759310; x=1716364110; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=puBYhI34uigvIMwKdPxu7OXATwqoJShcDnpckyqDkpk=; b=PxbDRFCGsqCTb7064Xn1x2Misu84yrPKKqC9bjv9jXxx48IJzwdgnW9KeF34hCnBV5 74TYzjIzucD6OTKcupD2dH+32z6O0lkX7OehqQJr+11V+BoGOydexC+mCyZrjFHS5uoT o0z0iE0AXsrVuqXE8nzgbwzUgzLfqtEy8PM4ASb/rK7N4+9DA4Uhh2TRl4lzcIOl5v01 1SY3Hmp8/8KiKgQhxNKUAoYwOCI6Z2bvN93lxLnkInuxGJafkmV6qihDXZd01Ju6Fh35 AJvOmyqBxt0HpQupiwJLkr2NYBZGo9pyclIFHRUtG1Vsu4Kd8mbq5Dgf7IAljTnlon8n rmTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715759310; x=1716364110; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=puBYhI34uigvIMwKdPxu7OXATwqoJShcDnpckyqDkpk=; b=XLv2eEGJHTdgW3MEki6ssMwE2YMkKJ+ZJjvEt7rGM3gAmJUwEG9di5RDMf4/cfLpU0 PDlaL4GIZEkmmB4ioZg0Io8urpJTxsuCR5cd+SuePkuf3uIS4EJxOCrS0bIga/kF3yrD VYwh3OKE6b7vfNA9PzSo3GkM7+5BE9tSHS98jrg4ifKANjVraLVRVonVIUPpjkxAnrLl SUwNSJbsRizoPMzg6kUlYUMhrWRtw3GrXPdIgYOG038P0TdzD+TH73SBgCgf+dXKrb10 I2YnGLH/rXtc8RboYdHXzRrF9J4pHWlhlAayMWtN6oG/6EcI3Isd2h31M30Kd237o+iG A7rg== X-Gm-Message-State: AOJu0YxLeTvBKaVr/HuLXfCkTjUWDWq18icyFeoFiMndq4+6oO30nx+J IjRPuZ0E/K1W3t2QfBkWiEHe+RVXjGF2sB6pDATYSxyUTseauspGSg6Zj4TeCoKBPIVHYsF7tL5 5KOmoUV3izKhp5U6m2L6UzUbNCrgXVlhCVVAAUL6pEyYSf8ke2aKxcRnyXsi4sbgrCiBEhICpkz VKPOkgC8obMX3re4Ca8ztPqBw1FLmN3sQwvF4= X-Google-Smtp-Source: AGHT+IEAke5BLdsYSlbnHg+sx6yNTpK5RUV1Z0Qtu6pfRwYRjeeuQyo/dCuuB7wXEnDKlIoE1giFCw== X-Received: by 2002:a05:6a00:3d49:b0:6f3:e9bc:cc3d with SMTP id d2e1a72fcca58-6f4c90905a1mr27161537b3a.3.1715759310189; Wed, 15 May 2024 00:48:30 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: "Fea.Wang" , Frank Chang , LIU Zhiwei , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH 5/5] target/riscv: Reserve exception codes for sw-check and hw-err Date: Wed, 15 May 2024 15:53:36 +0800 Message-Id: <20240515075340.2675136-6-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515075340.2675136-1-fea.wang@sifive.com> References: <20240515075340.2675136-1-fea.wang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=fea.wang@sifive.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1715759345349100015 Content-Type: text/plain; charset="utf-8" Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f888025c59..f037f727d9 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -673,6 +673,8 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT =3D 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT =3D 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT =3D 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_SW_CHECK =3D 0x12, /* since: priv-1.13.0 */ + RISCV_EXCP_HW_ERR =3D 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT =3D 0x14, RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT =3D 0x15, RISCV_EXCP_VIRT_INSTRUCTION_FAULT =3D 0x16, --=20 2.34.1