From nobody Mon Nov 25 09:54:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1715746053369166.47202031718484; Tue, 14 May 2024 21:07:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s75ub-0000bf-2C; Wed, 15 May 2024 00:06:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s75uM-0000ao-QX for qemu-devel@nongnu.org; Wed, 15 May 2024 00:06:31 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s75uJ-0003ha-6B for qemu-devel@nongnu.org; Wed, 15 May 2024 00:06:26 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxV+m0NERmZ+oMAA--.18743S3; Wed, 15 May 2024 12:06:12 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Dxc1azNERm_nMfAA--.38878S2; Wed, 15 May 2024 12:06:12 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, zhaotianrui@loongson.cn, richard.henderson@linaro.org, philmd@linaro.org, peter.maydell@linaro.org Subject: [RFC PATCH v2] target/loongarch/kvm: Add pmu support Date: Wed, 15 May 2024 12:06:11 +0800 Message-Id: <20240515040611.998507-1-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Dxc1azNERm_nMfAA--.38878S2 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1715746056054100001 Content-Type: text/plain; charset="utf-8" This patch adds PMU support, We just sets some cpucfg6 default value to PMU config on kvm mode, and then check the PMU config with kvm ioctl KVM_GET_DEVICE_ATTR. e.g '... -cpu max,pmu=3Don' (enable PMU)' '... -cpu max,pmu=3Doff' (disable PMU)' Signed-off-by: Song Gao --- v2: - Drop the property 'pmnum'. - Link to v1: https://patchew.org/QEMU/20240514094630.988617-1-gaosong@loo= ngson.cn/ This patch adds the 'RFC' heading because it requires the kernel to merge into patch[1] first [1]: https://lore.kernel.org/all/20240507120140.3119714-1-gaosong@loongson.= cn/ target/loongarch/cpu.c | 27 ++++++++++++++ target/loongarch/kvm/kvm.c | 53 ++++++++++++++++++++++++++- target/loongarch/loongarch-qmp-cmds.c | 2 +- 3 files changed, 80 insertions(+), 2 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index a0cad53676..fde0d2a816 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -421,6 +421,14 @@ static void loongarch_la464_initfn(Object *obj) data =3D FIELD_DP32(data, CPUCFG5, CC_DIV, 1); env->cpucfg[5] =3D data; =20 + if (kvm_enabled()) { + data =3D 0; + data =3D FIELD_DP32(data, CPUCFG6, PMP, 1); + data =3D FIELD_DP32(data, CPUCFG6, PMNUM, 3); + data =3D FIELD_DP32(data, CPUCFG6, PMBITS, 63); + env->cpucfg[6] =3D data; + } + data =3D 0; data =3D FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); data =3D FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); @@ -643,6 +651,20 @@ static void loongarch_set_lasx(Object *obj, bool value= , Error **errp) } } =20 +static bool loongarch_get_pmu(Object *obj, Error **errp) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + + return !!(FIELD_EX32(cpu->env.cpucfg[6], CPUCFG6, PMP)); +} + +static void loongarch_set_pmu(Object *obj, bool value, Error **errp) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + + cpu->env.cpucfg[6] =3D FIELD_DP32(cpu->env.cpucfg[6], CPUCFG6, PMP, va= lue); +} + void loongarch_cpu_post_init(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); @@ -655,6 +677,11 @@ void loongarch_cpu_post_init(Object *obj) object_property_add_bool(obj, "lasx", loongarch_get_lasx, loongarch_set_lasx); } + + if (kvm_enabled()) { + object_property_add_bool(obj, "pmu", loongarch_get_pmu, + loongarch_set_pmu); + } } =20 static void loongarch_cpu_init(Object *obj) diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index bc75552d0f..3e46203b15 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -556,6 +556,51 @@ static int kvm_check_cpucfg2(CPUState *cs) return ret; } =20 +static int kvm_check_cpucfg6(CPUState *cs) +{ + int ret; + uint64_t val; + struct kvm_device_attr attr =3D { + .group =3D KVM_LOONGARCH_VCPU_CPUCFG, + .attr =3D 6, + .addr =3D (uint64_t)&val, + }; + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPULoongArchState *env =3D &cpu->env; + + ret =3D kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr); + if (!ret) { + kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr); + + if (FIELD_EX32(env->cpucfg[6], CPUCFG6, PMP)) { + /* Check PMP */ + if (!FIELD_EX32(val, CPUCFG6, PMP)) { + error_report("'pmu' feature not supported by KVM on this = host" + " Please disable 'pmu' with " + "'... -cpu XXX,pmu=3Doff ...'\n"); + exit(EXIT_FAILURE); + } + /* Check PMNUM */ + int guest_pmnum =3D FIELD_EX32(env->cpucfg[6], CPUCFG6, PMNUM= ); + int host_pmnum =3D FIELD_EX32(val, CPUCFG6, PMNUM); + if (guest_pmnum > host_pmnum){ + error_report("The guest pmnum %d larger than KVM support = %d\n", + guest_pmnum, host_pmnum); + exit(EXIT_FAILURE); + } + /* Check PMBITS */ + int guest_pmbits =3D FIELD_EX32(env->cpucfg[6], CPUCFG6, PMBI= TS); + int host_pmbits =3D FIELD_EX32(val, CPUCFG6, PMBITS); + if (guest_pmbits !=3D host_pmbits) { + exit_report("The host not support PMBITS %d\n", guest_pmb= its); + exit(EXIT_FAILURE); + } + } + } + + return ret; +} + static int kvm_loongarch_put_cpucfg(CPUState *cs) { int i, ret =3D 0; @@ -568,7 +613,13 @@ static int kvm_loongarch_put_cpucfg(CPUState *cs) if (ret) { return ret; } - } + } + if (i =3D=3D 6) { + ret =3D kvm_check_cpucfg6(cs); + if (ret) { + return ret; + } + } val =3D env->cpucfg[i]; ret =3D kvm_set_one_reg(cs, KVM_IOC_CPUCFG(i), &val); if (ret < 0) { diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loong= arch-qmp-cmds.c index 8721a5eb13..7e1a6fd734 100644 --- a/target/loongarch/loongarch-qmp-cmds.c +++ b/target/loongarch/loongarch-qmp-cmds.c @@ -40,7 +40,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **= errp) } =20 static const char *cpu_model_advertised_features[] =3D { - "lsx", "lasx", NULL + "lsx", "lasx", "pmu", NULL }; =20 CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType= type, --=20 2.25.1