From nobody Mon Nov 25 12:39:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1715677730624602.3038923092932; Tue, 14 May 2024 02:08:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6o8p-0007lj-SF; Tue, 14 May 2024 05:08:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6o8l-0007kr-Uj for qemu-devel@nongnu.org; Tue, 14 May 2024 05:08:08 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6o8j-0001Kn-4r for qemu-devel@nongnu.org; Tue, 14 May 2024 05:08:07 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8BxN+ntKUNm1p4MAA--.18551S3; Tue, 14 May 2024 17:07:57 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bx0VXsKUNmNUAeAA--.37396S3; Tue, 14 May 2024 17:07:57 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org Subject: [PATCH v2 1/2] hw/intc/loongarch_extioi: Add extioi virt extension definition Date: Tue, 14 May 2024 17:07:55 +0800 Message-Id: <20240514090756.988096-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20240514090756.988096-1-gaosong@loongson.cn> References: <20240514090756.988096-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Bx0VXsKUNmNUAeAA--.37396S3 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1715677733128100005 Content-Type: text/plain; charset="utf-8" On LoongArch, IRQs can be routed to four vcpus with hardware extioi. This patch adds the extioi virt extension definition so that the IRQ can route to 256 vcpus. Signed-off-by: Song Gao --- include/hw/intc/loongarch_extioi.h | 21 +++++++ hw/intc/loongarch_extioi.c | 92 ++++++++++++++++++++++++++++-- 2 files changed, 109 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch= _extioi.h index 410c6e1121..d4646fab9f 100644 --- a/include/hw/intc/loongarch_extioi.h +++ b/include/hw/intc/loongarch_extioi.h @@ -41,6 +41,24 @@ #define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET) #define EXTIOI_SIZE 0x800 =20 +#define EXTIOI_VIRT_BASE (0x40000000) +#define EXTIOI_VIRT_SIZE (0x1000) +#define EXTIOI_VIRT_FEATURES (0x0) +#define EXTIOI_HAS_VIRT_EXTENSION (0) +#define EXTIOI_HAS_ENABLE_OPTION (1) +#define EXTIOI_HAS_INT_ENCODE (2) +#define EXTIOI_HAS_CPU_ENCODE (3) +#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \ + | BIT(EXTIOI_HAS_ENABLE_OPTION) \ + | BIT(EXTIOI_HAS_INT_ENCODE) \ + | BIT(EXTIOI_HAS_CPU_ENCODE)) +#define EXTIOI_VIRT_CONFIG (0x4) +#define EXTIOI_ENABLE (1) +#define EXTIOI_ENABLE_INT_ENCODE (2) +#define EXTIOI_ENABLE_CPU_ENCODE (3) +#define EXTIOI_VIRT_COREMAP_START (0x40) +#define EXTIOI_VIRT_COREMAP_END (0x240) + typedef struct ExtIOICore { uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT]; DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS); @@ -52,6 +70,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXT= IOI) struct LoongArchExtIOI { SysBusDevice parent_obj; uint32_t num_cpu; + uint32_t features; + uint32_t status; /* hardware state */ uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2]; uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT]; @@ -65,5 +85,6 @@ struct LoongArchExtIOI { qemu_irq irq[EXTIOI_IRQS]; ExtIOICore *cpu; MemoryRegion extioi_system_mem; + MemoryRegion virt_extend; }; #endif /* LOONGARCH_EXTIOI_H */ diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c index 0b358548eb..89afdb1c3c 100644 --- a/hw/intc/loongarch_extioi.c +++ b/hw/intc/loongarch_extioi.c @@ -143,10 +143,13 @@ static inline void extioi_update_sw_coremap(LoongArch= ExtIOI *s, int irq, =20 for (i =3D 0; i < 4; i++) { cpu =3D val & 0xff; - cpu =3D ctz32(cpu); - cpu =3D (cpu >=3D 4) ? 0 : cpu; val =3D val >> 8; =20 + if (!(s->status & BIT(EXTIOI_ENABLE_CPU_ENCODE))) { + cpu =3D ctz32(cpu); + cpu =3D (cpu >=3D 4) ? 0 : cpu; + } + if (s->sw_coremap[irq + i] =3D=3D cpu) { continue; } @@ -265,6 +268,61 @@ static const MemoryRegionOps extioi_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static MemTxResult extioi_virt_readw(void *opaque, hwaddr addr, uint64_t *= data, + unsigned size, MemTxAttrs attrs) +{ + LoongArchExtIOI *s =3D LOONGARCH_EXTIOI(opaque); + + switch (addr) { + case EXTIOI_VIRT_FEATURES: + *data =3D s->features; + break; + case EXTIOI_VIRT_CONFIG: + *data =3D s->status; + break; + default: + break; + } + + return MEMTX_OK; +} + +static MemTxResult extioi_virt_writew(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + LoongArchExtIOI *s =3D LOONGARCH_EXTIOI(opaque); + + switch (addr) { + case EXTIOI_VIRT_FEATURES: + return MEMTX_ACCESS_ERROR; + + case EXTIOI_VIRT_CONFIG: + /* + * extioi features can only be set at disabled status + */ + if ((s->status & BIT(EXTIOI_ENABLE)) && val) { + return MEMTX_ACCESS_ERROR; + } + + s->status =3D val & s->features; + break; + default: + break; + } + return MEMTX_OK; +} + +static const MemoryRegionOps extioi_virt_ops =3D { + .read_with_attrs =3D extioi_virt_readw, + .write_with_attrs =3D extioi_virt_writew, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + static void loongarch_extioi_realize(DeviceState *dev, Error **errp) { LoongArchExtIOI *s =3D LOONGARCH_EXTIOI(dev); @@ -284,6 +342,16 @@ static void loongarch_extioi_realize(DeviceState *dev,= Error **errp) memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_ops, s, "extioi_system_mem", 0x900); sysbus_init_mmio(sbd, &s->extioi_system_mem); + + if (s->features & BIT(EXTIOI_HAS_VIRT_EXTENSION)) { + memory_region_init_io(&s->virt_extend, OBJECT(s), &extioi_virt_ops, + s, "extioi_virt", EXTIOI_VIRT_SIZE); + sysbus_init_mmio(sbd, &s->virt_extend); + s->features |=3D EXTIOI_VIRT_HAS_FEATURES; + } else { + s->status |=3D BIT(EXTIOI_ENABLE); + } + s->cpu =3D g_new0(ExtIOICore, s->num_cpu); if (s->cpu =3D=3D NULL) { error_setg(errp, "Memory allocation for ExtIOICore faile"); @@ -304,6 +372,16 @@ static void loongarch_extioi_finalize(Object *obj) g_free(s->cpu); } =20 +static void loongarch_extioi_reset(DeviceState *d) +{ + LoongArchExtIOI *s =3D LOONGARCH_EXTIOI(d); + + /* use legacy interrupt routing method by default */ + if (s->features & BIT(EXTIOI_HAS_VIRT_EXTENSION)) { + s->status =3D 0; + } +} + static int vmstate_extioi_post_load(void *opaque, int version_id) { LoongArchExtIOI *s =3D LOONGARCH_EXTIOI(opaque); @@ -333,8 +411,8 @@ static const VMStateDescription vmstate_extioi_core =3D= { =20 static const VMStateDescription vmstate_loongarch_extioi =3D { .name =3D TYPE_LOONGARCH_EXTIOI, - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .post_load =3D vmstate_extioi_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_CO= UNT), @@ -347,12 +425,17 @@ static const VMStateDescription vmstate_loongarch_ext= ioi =3D { =20 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu, vmstate_extioi_core, ExtIOICore), + + VMSTATE_UINT32(features, LoongArchExtIOI), + VMSTATE_UINT32(status, LoongArchExtIOI), VMSTATE_END_OF_LIST() } }; =20 static Property extioi_properties[] =3D { DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1), + DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOI, featu= res, + EXTIOI_HAS_VIRT_EXTENSION, 0), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -361,6 +444,7 @@ static void loongarch_extioi_class_init(ObjectClass *kl= ass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D loongarch_extioi_realize; + dc->reset =3D loongarch_extioi_reset; device_class_set_props(dc, extioi_properties); dc->vmsd =3D &vmstate_loongarch_extioi; } --=20 2.25.1