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Sun, 12 May 2024 12:20:23 +0200 (CEST) Received: from zproxy1.enst.fr ([IPv6:::1]) by localhost (zproxy1.enst.fr [IPv6:::1]) (amavis, port 10032) with ESMTP id gXQMykHXqdho; Sun, 12 May 2024 12:20:23 +0200 (CEST) Received: from localhost (localhost [IPv6:::1]) by zproxy1.enst.fr (Postfix) with ESMTP id 6ACE5C056A; Sun, 12 May 2024 12:20:23 +0200 (CEST) Received: from zproxy1.enst.fr ([IPv6:::1]) by localhost (zproxy1.enst.fr [IPv6:::1]) (amavis, port 10026) with ESMTP id TcoAfFZy0J72; Sun, 12 May 2024 12:20:23 +0200 (CEST) Received: from inesv-Inspiron-3501.enst.fr (unknown [IPv6:2a04:8ec0:0:124::190c]) by zproxy1.enst.fr (Postfix) with ESMTPSA id B5A14C05C1; Sun, 12 May 2024 12:20:21 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.10.3 zproxy1.enst.fr 6ACE5C056A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telecom-paris.fr; s=A35C7578-1106-11E5-A17F-C303FDDA8F2E; t=1715509223; bh=oWGP6GZO0jOOBWiuu/NNsXQkGkqWrfm8ixMDn68Enbc=; h=From:To:Date:Message-ID:MIME-Version; b=zLuZ+Ip57rCxuGTCWXEojG23D4HEUYysrHIMBgev6Hb9Swz4P1D6Ymh511Y3H4Ctt hUUGb3rAVW8uM2rEqslWXCCkRfwe0xn5TfaBvh1En0rpmFnQBxbs7/Ftdcy5kn+fNr wTj1cOnMaoJBPPF8SF76pofulxnVWcOs3A3qIPh0= X-Virus-Scanned: amavis at enst.fr From: =?UTF-8?q?In=C3=A8s=20Varhol?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Arnaud Minier , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?In=C3=A8s=20Varhol?= Subject: [PATCH 2/3] hw/misc: In STM32L4x5 EXTI, handle direct line interrupts Date: Sun, 12 May 2024 12:19:41 +0200 Message-ID: <20240512102013.211127-3-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240512102013.211127-1-ines.varhol@telecom-paris.fr> References: <20240512102013.211127-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=137.194.2.220; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy1.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1715509317692100003 Content-Type: text/plain; charset="utf-8" The previous implementation for EXTI interrupts only handled "configurable" interrupts, like those originating from STM32L4x5 SYSCFG (the only device currently connected to the EXTI up until now). In order to connect STM32L4x5 USART to the EXTI, this commit adds handling for direct interrupts (interrupts without configurable edge), as well as a comment that will be useful to connect other devices to the EXTI. Signed-off-by: In=C3=A8s Varhol --- hw/misc/stm32l4x5_exti.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c index eebefc6cd3..1817bbdad2 100644 --- a/hw/misc/stm32l4x5_exti.c +++ b/hw/misc/stm32l4x5_exti.c @@ -106,6 +106,27 @@ static void stm32l4x5_exti_set_irq(void *opaque, int i= rq, int level) return; } =20 + /* In case of a direct line interrupt */ + if (extract32(exti_romask[bank], irq, 1)) { + if (level) { + qemu_irq_raise(s->irq[oirq]); + } else { + qemu_irq_lower(s->irq[oirq]); + } + return; + } + + /* + * In case of a configurable interrupt + * + * Note that while the real EXTI uses edge detection to tell + * apart a line rising (the level changes from 0 to 1) and a line + * staying high (the level was 1 and is set to 1), the current + * implementation relies on the fact that this handler will only + * be called when there's a level change. That means that the + * devices creating a configurable interrupt (like STM32L4x5 GPIO) + * have to set their IRQs only on a change. + */ if (((1 << irq) & s->rtsr[bank]) && level) { /* Rising Edge */ s->pr[bank] |=3D 1 << irq; @@ -116,7 +137,7 @@ static void stm32l4x5_exti_set_irq(void *opaque, int ir= q, int level) qemu_irq_pulse(s->irq[oirq]); } /* - * In the following situations : + * In the following situations (for configurable interrupts) : * - falling edge but rising trigger selected * - rising edge but falling trigger selected * - no trigger selected --=20 2.43.2