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Sun, 12 May 2024 12:20:22 +0200 (CEST) Received: from zproxy1.enst.fr ([IPv6:::1]) by localhost (zproxy1.enst.fr [IPv6:::1]) (amavis, port 10032) with ESMTP id Lg59lpfSxPJC; Sun, 12 May 2024 12:20:21 +0200 (CEST) Received: from localhost (localhost [IPv6:::1]) by zproxy1.enst.fr (Postfix) with ESMTP id A0337C056A; Sun, 12 May 2024 12:20:21 +0200 (CEST) Received: from zproxy1.enst.fr ([IPv6:::1]) by localhost (zproxy1.enst.fr [IPv6:::1]) (amavis, port 10026) with ESMTP id VM7xPjZhPqjF; Sun, 12 May 2024 12:20:21 +0200 (CEST) Received: from inesv-Inspiron-3501.enst.fr (unknown [IPv6:2a04:8ec0:0:124::190c]) by zproxy1.enst.fr (Postfix) with ESMTPSA id 6E057C05B2; Sun, 12 May 2024 12:20:20 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.10.3 zproxy1.enst.fr A0337C056A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telecom-paris.fr; s=A35C7578-1106-11E5-A17F-C303FDDA8F2E; t=1715509221; bh=qiG46x/VOVkiEpvcA+8VprXyXNI6r0F6dCCONYL27mo=; h=From:To:Date:Message-ID:MIME-Version; b=w7FlTDEcbrLoYZ4L1JsHJf62SkTcLInq6wwRyAj3DUJD7ttvYU1fjjLMfleB0x3y3 V8JN/fRZJx6xx6lQP2DCS8TPekUx8QeubTLkeJyXdawUNmIveJUm65lazehc+HBZDg 0eZpR8IEra/5RFzDv4W5awe3z3okamZt2dakvcwU= X-Virus-Scanned: amavis at enst.fr From: =?UTF-8?q?In=C3=A8s=20Varhol?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Arnaud Minier , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?In=C3=A8s=20Varhol?= Subject: [PATCH 1/3] hw/misc: In STM32L4x5 EXTI, consolidate 2 constants Date: Sun, 12 May 2024 12:19:40 +0200 Message-ID: <20240512102013.211127-2-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240512102013.211127-1-ines.varhol@telecom-paris.fr> References: <20240512102013.211127-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:660:330f:2::dc; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy1.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1715509308489100001 Content-Type: text/plain; charset="utf-8" Up until now, the EXTI implementation had 16 inbound GPIOs connected to the 16 outbound GPIOs of STM32L4x5 SYSCFG. The EXTI actually handles 40 lines (namely 5 from STM32L4x5 USART devices which are already implemented in QEMU). In order to connect USART devices to EXTI, this commit consolidates constants `EXTI_NUM_INTERRUPT_OUT_LINES` (40) and `EXTI_NUM_GPIO_EVENT_IN_LINES` (16) into `EXTI_NUM_LINES` (40). Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell --- include/hw/misc/stm32l4x5_exti.h | 4 ++-- hw/misc/stm32l4x5_exti.c | 6 ++---- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/include/hw/misc/stm32l4x5_exti.h b/include/hw/misc/stm32l4x5_e= xti.h index be961d2f01..82f75a2417 100644 --- a/include/hw/misc/stm32l4x5_exti.h +++ b/include/hw/misc/stm32l4x5_exti.h @@ -30,7 +30,7 @@ #define TYPE_STM32L4X5_EXTI "stm32l4x5-exti" OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5ExtiState, STM32L4X5_EXTI) =20 -#define EXTI_NUM_INTERRUPT_OUT_LINES 40 +#define EXTI_NUM_LINES 40 #define EXTI_NUM_REGISTER 2 =20 struct Stm32l4x5ExtiState { @@ -45,7 +45,7 @@ struct Stm32l4x5ExtiState { uint32_t swier[EXTI_NUM_REGISTER]; uint32_t pr[EXTI_NUM_REGISTER]; =20 - qemu_irq irq[EXTI_NUM_INTERRUPT_OUT_LINES]; + qemu_irq irq[EXTI_NUM_LINES]; }; =20 #endif diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c index 495a0004ab..eebefc6cd3 100644 --- a/hw/misc/stm32l4x5_exti.c +++ b/hw/misc/stm32l4x5_exti.c @@ -42,7 +42,6 @@ #define EXTI_SWIER2 0x30 #define EXTI_PR2 0x34 =20 -#define EXTI_NUM_GPIO_EVENT_IN_LINES 16 #define EXTI_MAX_IRQ_PER_BANK 32 #define EXTI_IRQS_BANK0 32 #define EXTI_IRQS_BANK1 8 @@ -241,7 +240,7 @@ static void stm32l4x5_exti_init(Object *obj) { Stm32l4x5ExtiState *s =3D STM32L4X5_EXTI(obj); =20 - for (size_t i =3D 0; i < EXTI_NUM_INTERRUPT_OUT_LINES; i++) { + for (size_t i =3D 0; i < EXTI_NUM_LINES; i++) { sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); } =20 @@ -249,8 +248,7 @@ static void stm32l4x5_exti_init(Object *obj) TYPE_STM32L4X5_EXTI, 0x400); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); =20 - qdev_init_gpio_in(DEVICE(obj), stm32l4x5_exti_set_irq, - EXTI_NUM_GPIO_EVENT_IN_LINES); + qdev_init_gpio_in(DEVICE(obj), stm32l4x5_exti_set_irq, EXTI_NUM_LINES); } =20 static const VMStateDescription vmstate_stm32l4x5_exti =3D { --=20 2.43.2 From nobody Mon Nov 25 09:58:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=telecom-paris.fr ARC-Seal: i=1; a=rsa-sha256; t=1715509316; cv=none; d=zohomail.com; s=zohoarc; b=iWg1lNUlsun+VyLyz3pVrpxkV4R/LHzvjm+qJK2MDct6yqleZXLYvVj+mM8QY4qw4LeyqAOmLPtI1bwe8eFSUEW6k4fdibEIVzu6085YEaZM0j81PlE4fn0OGas+VAHyDLSFfobwyMt4lp719R1pkxHZDgb2IXIKbUIvNS2PcBk= ARC-Message-Signature: i=1; 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Sun, 12 May 2024 12:20:23 +0200 (CEST) Received: from inesv-Inspiron-3501.enst.fr (unknown [IPv6:2a04:8ec0:0:124::190c]) by zproxy1.enst.fr (Postfix) with ESMTPSA id B5A14C05C1; Sun, 12 May 2024 12:20:21 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.10.3 zproxy1.enst.fr 6ACE5C056A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telecom-paris.fr; s=A35C7578-1106-11E5-A17F-C303FDDA8F2E; t=1715509223; bh=oWGP6GZO0jOOBWiuu/NNsXQkGkqWrfm8ixMDn68Enbc=; h=From:To:Date:Message-ID:MIME-Version; b=zLuZ+Ip57rCxuGTCWXEojG23D4HEUYysrHIMBgev6Hb9Swz4P1D6Ymh511Y3H4Ctt hUUGb3rAVW8uM2rEqslWXCCkRfwe0xn5TfaBvh1En0rpmFnQBxbs7/Ftdcy5kn+fNr wTj1cOnMaoJBPPF8SF76pofulxnVWcOs3A3qIPh0= X-Virus-Scanned: amavis at enst.fr From: =?UTF-8?q?In=C3=A8s=20Varhol?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Arnaud Minier , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?In=C3=A8s=20Varhol?= Subject: [PATCH 2/3] hw/misc: In STM32L4x5 EXTI, handle direct line interrupts Date: Sun, 12 May 2024 12:19:41 +0200 Message-ID: <20240512102013.211127-3-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240512102013.211127-1-ines.varhol@telecom-paris.fr> References: <20240512102013.211127-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=137.194.2.220; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy1.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1715509317692100003 Content-Type: text/plain; charset="utf-8" The previous implementation for EXTI interrupts only handled "configurable" interrupts, like those originating from STM32L4x5 SYSCFG (the only device currently connected to the EXTI up until now). In order to connect STM32L4x5 USART to the EXTI, this commit adds handling for direct interrupts (interrupts without configurable edge), as well as a comment that will be useful to connect other devices to the EXTI. Signed-off-by: In=C3=A8s Varhol --- hw/misc/stm32l4x5_exti.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c index eebefc6cd3..1817bbdad2 100644 --- a/hw/misc/stm32l4x5_exti.c +++ b/hw/misc/stm32l4x5_exti.c @@ -106,6 +106,27 @@ static void stm32l4x5_exti_set_irq(void *opaque, int i= rq, int level) return; } =20 + /* In case of a direct line interrupt */ + if (extract32(exti_romask[bank], irq, 1)) { + if (level) { + qemu_irq_raise(s->irq[oirq]); + } else { + qemu_irq_lower(s->irq[oirq]); + } + return; + } + + /* + * In case of a configurable interrupt + * + * Note that while the real EXTI uses edge detection to tell + * apart a line rising (the level changes from 0 to 1) and a line + * staying high (the level was 1 and is set to 1), the current + * implementation relies on the fact that this handler will only + * be called when there's a level change. That means that the + * devices creating a configurable interrupt (like STM32L4x5 GPIO) + * have to set their IRQs only on a change. + */ if (((1 << irq) & s->rtsr[bank]) && level) { /* Rising Edge */ s->pr[bank] |=3D 1 << irq; @@ -116,7 +137,7 @@ static void stm32l4x5_exti_set_irq(void *opaque, int ir= q, int level) qemu_irq_pulse(s->irq[oirq]); } /* - * In the following situations : + * In the following situations (for configurable interrupts) : * - falling edge but rising trigger selected * - rising edge but falling trigger selected * - no trigger selected --=20 2.43.2 From nobody Mon Nov 25 09:58:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=telecom-paris.fr ARC-Seal: i=1; a=rsa-sha256; t=1715509307; cv=none; d=zohomail.com; s=zohoarc; b=XrWmkWJue0QPGC2djPlh5sRN+f+URnIuTv+npVZjUvK/HQEthdty5W8mY6XPOs+1W5DZcidc7BmpLWQCOZD0H7FeQhtauKMlgnDT2CK8yqVwCHIbXS/NaWg2v7KZBjQ4eB3MUYpC2r9uO7b7+hY19mMBgamBMaBJ1o8Q1W+1OSE= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:660:330f:2::dc; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy1.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1715509309583100003 Content-Type: text/plain; charset="utf-8" The USART devices were previously connecting their outbound IRQs directly to the CPU because the EXTI wasn't handling direct lines interrupts. Now the USART connects to the EXTI inbound GPIOs, and the EXTI connects its IRQs to the CPU. The existing QTest for the USART (tests/qtest/stm32l4x5_usart-test.c) checks that USART1_IRQ in the CPU is pending when expected so it confirms that the connection through the EXTI still works. Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell --- hw/arm/stm32l4x5_soc.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 38f7a2d5d9..fac83d349c 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -81,6 +81,10 @@ static const int exti_irq[NUM_EXTI_IRQ] =3D { #define RCC_BASE_ADDRESS 0x40021000 #define RCC_IRQ 5 =20 +#define EXTI_USART1_IRQ 26 +#define EXTI_UART4_IRQ 29 +#define EXTI_LPUART1_IRQ 31 + static const int exti_or_gates_out[NUM_EXTI_OR_GATES] =3D { 23, 40, 63, 1, }; @@ -129,10 +133,6 @@ static const hwaddr uart_addr[] =3D { =20 #define LPUART_BASE_ADDRESS 0x40008000 =20 -static const int usart_irq[] =3D { 37, 38, 39 }; -static const int uart_irq[] =3D { 52, 53 }; -#define LPUART_IRQ 70 - static void stm32l4x5_soc_initfn(Object *obj) { Stm32l4x5SocState *s =3D STM32L4X5_SOC(obj); @@ -297,6 +297,7 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) } } =20 + /* Connect SYSCFG to EXTI */ for (unsigned i =3D 0; i < GPIO_NUM_PINS; i++) { qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(DEVICE(&s->exti), i)); @@ -322,15 +323,10 @@ static void stm32l4x5_soc_realize(DeviceState *dev_so= c, Error **errp) return; } sysbus_mmio_map(busdev, 0, usart_addr[i]); - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i= ])); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti), + EXTI_USART1_IRQ + i= )); } =20 - /* - * TODO: Connect the USARTs, UARTs and LPUART to the EXTI once the EXTI - * can handle other gpio-in than the gpios. (e.g. Direct Lines for the - * usarts) - */ - /* UART devices */ for (int i =3D 0; i < STM_NUM_UARTS; i++) { g_autofree char *name =3D g_strdup_printf("uart%d-out", STM_NUM_US= ARTS + i + 1); @@ -343,7 +339,8 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) return; } sysbus_mmio_map(busdev, 0, uart_addr[i]); - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, uart_irq[i]= )); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti), + EXTI_UART4_IRQ + i)= ); } =20 /* LPUART device*/ @@ -356,7 +353,8 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) return; } sysbus_mmio_map(busdev, 0, LPUART_BASE_ADDRESS); - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, LPUART_IRQ)); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti), + EXTI_LPUART1_IRQ)); =20 /* APB1 BUS */ create_unimplemented_device("TIM2", 0x40000000, 0x400); --=20 2.43.2