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[220.245.239.57]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6340a632725sm2691453a12.12.2024.05.10.07.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 07:15:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715350502; x=1715955302; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GTzB3Nu4NJmXxIc5C6AQnfnpgpXf5szLqDm+8G74C3g=; b=TM/x6J/NJ15oD2gdYCTGrfbBXQ8mOdLv8elagZnsKIxudVyHpxdJQ+LPuQrq8mKiXJ 7j7E8ibTcZEMGGK3ojkeGJLVYLpKawUTxT3Cgi7GD4ZBJYXJUXh+ootkRuaXBopnAzOw G9WuFgTU/EEl0NgnPPnfIECVbSAdyXDwp8ws8Tf++p4cB7zZfx7BTDo+TG4tlBDTbbPh JPHARaEqPEkrmCgod8Z34OW9UPa2kN6/SYft/x/khjr0KtKFMxWKvrvq0OvK4hc1Y8+i hW8Hpbg5IC2c3qREhXpVOQTmE3wbE1ZX9hzHEeVx+GuikSmflHY4VfJnrrjEWL5fTdmt bBzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715350502; x=1715955302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GTzB3Nu4NJmXxIc5C6AQnfnpgpXf5szLqDm+8G74C3g=; b=qTHVXBnTh3ePeHFJLraNL6VbXBjnMKDvYzoMZk3Us8xdR7WQlYue66iMegwZRYMh07 AdR7Wse4QDrt1Xi1F3vgqXbdOW8SdtTuMGOQj5qnaMpPIvoMDJAJ/u0PdIMPvXVQFQ5z 8o7CTa7/evKhwphHOcLlxuQZRjkeVvI1dfdtZdeo9chTY3BzACCJClFKp1BmdyYfS5tH b9Dq12aRrl7yAXjp2x8UsVYJmU4xW89GNKBZhz+QinEtXeEcSVkOlm5CNnI/GUIVP+f5 yR7rCa5J2LBOnqtP91xaxvnlj3NRQc4yzJFXFydJOCYJUj/okk0RrbJBqZphgOpFef8B wg5Q== X-Forwarded-Encrypted: i=1; AJvYcCVV73XdmpO+jRXURq64vFxrQ9UT9Mdy4Ehpv+HZCKAJd1Pr97NzBlnmhT1ZdNwI1LcKODNuDqLGmzbiMrxv3J5yKDB2lN0= X-Gm-Message-State: AOJu0YzakrRUH18u/oc5RHdgWYfj5LXUlLRZIO9H5FoHt5A3IgfG9aLd GFKWGrWu86iCMeIDlb8Fmpy2vRQQ3b9lf1mFzsKtgd5SF5PxkxoOgfLcxw== X-Google-Smtp-Source: AGHT+IGTjersqX+7QkEI+vDV5zYAOuFmZXkyh3sIGzLlleIssjSApLI0CoodGBfv5Vf5CFUKoTxzxg== X-Received: by 2002:a05:6e02:160a:b0:36c:5882:511a with SMTP id e9e14a558f8ab-36cc14f8853mr33137275ab.22.1715350502071; Fri, 10 May 2024 07:15:02 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= Subject: [PATCH v2 2/2] ppc/pnv: Implement ADU access to LPC space Date: Sat, 11 May 2024 00:14:45 +1000 Message-ID: <20240510141446.108360-3-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240510141446.108360-1-npiggin@gmail.com> References: <20240510141446.108360-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12b; envelope-from=npiggin@gmail.com; helo=mail-il1-x12b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1715350541346100003 Content-Type: text/plain; charset="utf-8" One of the functions of the ADU is indirect memory access engines that send and receive data via ADU registers. This implements the ADU LPC memory access functionality sufficiently for IBM proprietary firmware to access the UART and print characters to the serial port as it does on real hardware. This requires a linkage between adu and lpc, which allows adu to perform memory access in the lpc space. Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv_adu.h | 7 +++ include/hw/ppc/pnv_lpc.h | 5 +++ hw/ppc/pnv.c | 4 ++ hw/ppc/pnv_adu.c | 95 ++++++++++++++++++++++++++++++++++++++++ hw/ppc/pnv_lpc.c | 12 ++--- 5 files changed, 117 insertions(+), 6 deletions(-) diff --git a/include/hw/ppc/pnv_adu.h b/include/hw/ppc/pnv_adu.h index b5f308627b..f9dbd8c8b3 100644 --- a/include/hw/ppc/pnv_adu.h +++ b/include/hw/ppc/pnv_adu.h @@ -10,6 +10,7 @@ #define PPC_PNV_ADU_H =20 #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_lpc.h" #include "hw/qdev-core.h" =20 #define TYPE_PNV_ADU "pnv-adu" @@ -19,6 +20,12 @@ OBJECT_DECLARE_TYPE(PnvADU, PnvADUClass, PNV_ADU) struct PnvADU { DeviceState xd; =20 + /* LPCMC (LPC Master Controller) access engine */ + PnvLpcController *lpc; + uint64_t lpc_base_reg; + uint64_t lpc_cmd_reg; + uint64_t lpc_data_reg; + MemoryRegion xscom_regs; }; =20 diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 5d22c45570..d99407f856 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -94,6 +94,11 @@ struct PnvLpcClass { DeviceRealize parent_realize; }; =20 +bool pnv_lpc_opb_read(PnvLpcController *lpc, uint32_t addr, + uint8_t *data, int sz); +bool pnv_lpc_opb_write(PnvLpcController *lpc, uint32_t addr, + uint8_t *data, int sz); + ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **e= rrp); int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr, uint64_t lpcm_size); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 5869aac89a..eb9dbc62dd 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1642,6 +1642,8 @@ static void pnv_chip_power9_realize(DeviceState *dev,= Error **errp) } =20 /* ADU */ + object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lp= c), + &error_abort); if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { return; } @@ -1908,6 +1910,8 @@ static void pnv_chip_power10_realize(DeviceState *dev= , Error **errp) } =20 /* ADU */ + object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->= lpc), + &error_abort); if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { return; } diff --git a/hw/ppc/pnv_adu.c b/hw/ppc/pnv_adu.c index 8279bc8b26..81b7d6e526 100644 --- a/hw/ppc/pnv_adu.c +++ b/hw/ppc/pnv_adu.c @@ -21,11 +21,18 @@ #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_adu.h" #include "hw/ppc/pnv_chip.h" +#include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_xscom.h" #include "trace.h" =20 +#define ADU_LPC_BASE_REG 0x40 +#define ADU_LPC_CMD_REG 0x41 +#define ADU_LPC_DATA_REG 0x42 +#define ADU_LPC_STATUS_REG 0x43 + static uint64_t pnv_adu_xscom_read(void *opaque, hwaddr addr, unsigned wid= th) { + PnvADU *adu =3D PNV_ADU(opaque); uint32_t offset =3D addr >> 3; uint64_t val =3D 0; =20 @@ -34,6 +41,24 @@ static uint64_t pnv_adu_xscom_read(void *opaque, hwaddr = addr, unsigned width) case 0x12: /* log register */ case 0x13: /* error register */ break; + case ADU_LPC_BASE_REG: + /* + * LPC Address Map in Pervasive ADU Workbook + * + * return PNV10_LPCM_BASE(chip) & PPC_BITMASK(8, 31); + * XXX: implement as class property, or get from LPC? + */ + qemu_log_mask(LOG_UNIMP, "ADU: LPC_BASE_REG is not implemented\n"); + break; + case ADU_LPC_CMD_REG: + val =3D adu->lpc_cmd_reg; + break; + case ADU_LPC_DATA_REG: + val =3D adu->lpc_data_reg; + break; + case ADU_LPC_STATUS_REG: + val =3D PPC_BIT(0); /* ack / done */ + break; =20 default: qemu_log_mask(LOG_UNIMP, "ADU Unimplemented read register: Ox%08x\= n", @@ -45,9 +70,30 @@ static uint64_t pnv_adu_xscom_read(void *opaque, hwaddr = addr, unsigned width) return val; } =20 +static bool lpc_cmd_read(PnvADU *adu) +{ + return !!(adu->lpc_cmd_reg & PPC_BIT(0)); +} + +static bool lpc_cmd_write(PnvADU *adu) +{ + return !lpc_cmd_read(adu); +} + +static uint32_t lpc_cmd_addr(PnvADU *adu) +{ + return (adu->lpc_cmd_reg & PPC_BITMASK(32, 63)) >> PPC_BIT_NR(63); +} + +static uint32_t lpc_cmd_size(PnvADU *adu) +{ + return (adu->lpc_cmd_reg & PPC_BITMASK(5, 11)) >> PPC_BIT_NR(11); +} + static void pnv_adu_xscom_write(void *opaque, hwaddr addr, uint64_t val, unsigned width) { + PnvADU *adu =3D PNV_ADU(opaque); uint32_t offset =3D addr >> 3; =20 trace_pnv_adu_xscom_write(addr, val); @@ -58,6 +104,47 @@ static void pnv_adu_xscom_write(void *opaque, hwaddr ad= dr, uint64_t val, case 0x13: /* error register */ break; =20 + case ADU_LPC_BASE_REG: + qemu_log_mask(LOG_UNIMP, + "ADU: Changing LPC_BASE_REG is not implemented\n"); + break; + + case ADU_LPC_CMD_REG: + adu->lpc_cmd_reg =3D val; + if (lpc_cmd_read(adu)) { + uint32_t lpc_addr =3D lpc_cmd_addr(adu); + uint32_t lpc_size =3D lpc_cmd_size(adu); + uint64_t data =3D 0; + + pnv_lpc_opb_read(adu->lpc, lpc_addr, (void *)&data, lpc_size); + + /* + * ADU access is performed within 8-byte aligned sectors. Smal= ler + * access sizes don't get formatted to the least significant b= yte, + * but rather appear in the data reg at the same offset as the + * address in memory. This shifts them into that position. + */ + adu->lpc_data_reg =3D be64_to_cpu(data) >> ((lpc_addr & 7) * 8= ); + } + break; + + case ADU_LPC_DATA_REG: + adu->lpc_data_reg =3D val; + if (lpc_cmd_write(adu)) { + uint32_t lpc_addr =3D lpc_cmd_addr(adu); + uint32_t lpc_size =3D lpc_cmd_size(adu); + uint64_t data; + + data =3D cpu_to_be64(val) >> ((lpc_addr & 7) * 8); /* See abov= e */ + pnv_lpc_opb_write(adu->lpc, lpc_addr, (void *)&data, lpc_size); + } + break; + + case ADU_LPC_STATUS_REG: + qemu_log_mask(LOG_UNIMP, + "ADU: Changing LPC_STATUS_REG is not implemented\n"); + break; + default: qemu_log_mask(LOG_UNIMP, "ADU Unimplemented write register: Ox%08x= \n", offse= t); @@ -78,18 +165,26 @@ static void pnv_adu_realize(DeviceState *dev, Error **= errp) { PnvADU *adu =3D PNV_ADU(dev); =20 + assert(adu->lpc); + /* XScom regions for ADU registers */ pnv_xscom_region_init(&adu->xscom_regs, OBJECT(dev), &pnv_adu_xscom_ops, adu, "xscom-adu", PNV9_XSCOM_ADU_SIZE); } =20 +static Property pnv_adu_properties[] =3D { + DEFINE_PROP_LINK("lpc", PnvADU, lpc, TYPE_PNV_LPC, PnvLpcController *), + DEFINE_PROP_END_OF_LIST(), +}; + static void pnv_adu_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D pnv_adu_realize; dc->desc =3D "PowerNV ADU"; + device_class_set_props(dc, pnv_adu_properties); dc->user_creatable =3D false; } =20 diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index d692858bee..e5e9727563 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -235,16 +235,16 @@ int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_off= set, uint64_t lpcm_addr, * TODO: rework to use address_space_stq() and address_space_ldq() * instead. */ -static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data, - int sz) +bool pnv_lpc_opb_read(PnvLpcController *lpc, uint32_t addr, + uint8_t *data, int sz) { /* XXX Handle access size limits and FW read caching here */ return !address_space_read(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, data, sz); } =20 -static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data, - int sz) +bool pnv_lpc_opb_write(PnvLpcController *lpc, uint32_t addr, + uint8_t *data, int sz) { /* XXX Handle access size limits here */ return !address_space_write(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, @@ -276,7 +276,7 @@ static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint= 64_t cmd) } =20 if (cmd & ECCB_CTL_READ) { - success =3D opb_read(lpc, opb_addr, data, sz); + success =3D pnv_lpc_opb_read(lpc, opb_addr, data, sz); if (success) { lpc->eccb_stat_reg =3D ECCB_STAT_OP_DONE | (((uint64_t)data[0]) << 24 | @@ -293,7 +293,7 @@ static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint= 64_t cmd) data[2] =3D lpc->eccb_data_reg >> 8; data[3] =3D lpc->eccb_data_reg; =20 - success =3D opb_write(lpc, opb_addr, data, sz); + success =3D pnv_lpc_opb_write(lpc, opb_addr, data, sz); lpc->eccb_stat_reg =3D ECCB_STAT_OP_DONE; } /* XXX Which error bit (if any) to signal OPB error ? */ --=20 2.43.0