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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240508-loongson3-ipi-v1-4-1a7b67704664@flygoat.com> References: <20240508-loongson3-ipi-v1-0-1a7b67704664@flygoat.com> In-Reply-To: <20240508-loongson3-ipi-v1-0-1a7b67704664@flygoat.com> To: qemu-devel@nongnu.org Cc: Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6535; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=VxxrJORtTvGfo3DCiIMPAxsYETXSZd6msJZevyJnYpo=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjTriucOLLeSWg3a5x55x8Zbx3F7zz6LcyczF+qtmX701 2cNbXHpjlIWBjEOBlkxRZYQAaW+DY0XF1x/kPUHZg4rE8gQBi5OAZjI44+MDA+cFDfxa+8Kf7Ui 5ejSOyfkmuySMy9qGe+cVWi51yzY0IXhr2zqwsDSdZc+eAhlNn/xUVMRSZR7/NPwrJEhfwjb8vt xXAA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=103.168.172.144; envelope-from=jiaxun.yang@flygoat.com; helo=fout1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @flygoat.com) X-ZM-MESSAGEID: 1715173698917100010 The real IPI hardware have dedicated MMIO registers mapped into memory address space for every core. This is not used by LoongArch guest software but it is essential for CPU without IOCSR such as Loongson-3A1000. Implement it with existing infrastructure. Signed-off-by: Jiaxun Yang --- hw/intc/loongson_ipi.c | 81 ++++++++++++++++++++++++++++++++------= ---- include/hw/intc/loongson_ipi.h | 2 ++ 2 files changed, 64 insertions(+), 19 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 93cc50a37a11..c8a25b4eb8e2 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -23,16 +23,14 @@ #endif #include "trace.h" =20 -static MemTxResult loongson_ipi_readl(void *opaque, hwaddr addr, +static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { - IPICore *s; - LoongsonIPI *ipi =3D opaque; + IPICore *s =3D opaque; uint64_t ret =3D 0; int index =3D 0; =20 - s =3D &ipi->cpu[attrs.requester_id]; addr &=3D 0xff; switch (addr) { case CORE_STATUS_OFF: @@ -61,6 +59,21 @@ static MemTxResult loongson_ipi_readl(void *opaque, hwad= dr addr, return MEMTX_OK; } =20 +static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, + uint64_t *data, + unsigned size, MemTxAttrs attrs) +{ + LoongsonIPI *ipi =3D opaque; + IPICore *s; + + if (attrs.requester_id >=3D ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s =3D &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_readl(s, addr, data, size, attrs); +} + static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) { #ifdef TARGET_LOONGARCH64 @@ -174,17 +187,17 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs = attrs) return send_ipi_data(cs, val, addr, attrs); } =20 -static MemTxResult loongson_ipi_writel(void *opaque, hwaddr addr, uint64_t= val, - unsigned size, MemTxAttrs attrs) +static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { - LoongsonIPI *ipi =3D opaque; - IPICore *s; + IPICore *s =3D opaque; + LoongsonIPI *ipi =3D s->ipi; int index =3D 0; uint32_t cpuid; uint8_t vector; CPUState *cs; =20 - s =3D &ipi->cpu[attrs.requester_id]; addr &=3D 0xff; trace_loongson_ipi_write(size, (uint64_t)addr, val); switch (addr) { @@ -215,13 +228,11 @@ static MemTxResult loongson_ipi_writel(void *opaque, = hwaddr addr, uint64_t val, /* IPI status vector */ vector =3D extract8(val, 0, 5); cs =3D ipi_getcpu(cpuid); - if (cs =3D=3D NULL) { + if (cs =3D=3D NULL || cs->cpu_index >=3D ipi->num_cpu) { return MEMTX_DECODE_ERROR; } - - /* override requester_id */ - attrs.requester_id =3D cs->cpu_index; - loongson_ipi_writel(ipi, CORE_SET_OFF, BIT(vector), 4, attrs); + loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + BIT(vector), 4, attrs); break; default: qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); @@ -231,9 +242,34 @@ static MemTxResult loongson_ipi_writel(void *opaque, h= waddr addr, uint64_t val, return MEMTX_OK; } =20 -static const MemoryRegionOps loongson_ipi_ops =3D { - .read_with_attrs =3D loongson_ipi_readl, - .write_with_attrs =3D loongson_ipi_writel, +static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPI *ipi =3D opaque; + IPICore *s; + + if (attrs.requester_id >=3D ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s =3D &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_writel(s, addr, val, size, attrs); +} + +static const MemoryRegionOps loongson_ipi_core_ops =3D { + .read_with_attrs =3D loongson_ipi_core_readl, + .write_with_attrs =3D loongson_ipi_core_writel, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps loongson_ipi_iocsr_ops =3D { + .read_with_attrs =3D loongson_ipi_iocsr_readl, + .write_with_attrs =3D loongson_ipi_iocsr_writel, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, .valid.min_access_size =3D 4, @@ -282,7 +318,7 @@ static void loongson_ipi_realize(DeviceState *dev, Erro= r **errp) return; } =20 - memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), &loongson_ipi_op= s, + memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), &loongson_ipi_io= csr_ops, s, "loongson_ipi_iocsr", 0x48); =20 /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ @@ -297,11 +333,18 @@ static void loongson_ipi_realize(DeviceState *dev, Er= ror **errp) =20 s->cpu =3D g_new0(IPICore, s->num_cpu); if (s->cpu =3D=3D NULL) { - error_setg(errp, "Memory allocation for ExtIOICore faile"); + error_setg(errp, "Memory allocation for IPICore faile"); return; } =20 for (i =3D 0; i < s->num_cpu; i++) { + s->cpu[i].ipi =3D s; + s->cpu[i].ipi_mmio_mem =3D g_new0(MemoryRegion, 1); + g_autofree char *name =3D g_strdup_printf("loongson_ipi_cpu%d_mmio= ", i); + memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), + &loongson_ipi_core_ops, &s->cpu[i], name, 0x= 48); + sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); + qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); } } diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 2c0e8820f5ec..3f795edbf3cd 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -34,6 +34,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI) =20 typedef struct IPICore { + LoongsonIPI *ipi; + MemoryRegion *ipi_mmio_mem; uint32_t status; uint32_t en; uint32_t set; --=20 2.34.1