From nobody Mon Nov 25 14:40:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1715075000; cv=none; d=zohomail.com; s=zohoarc; b=A75a8ToUTJrUXebIHUk6PUC1tK7a/8d/KyHLkgxhdWciTNil5UFzK5FYR9LwlwzKKSXJxj8JnMwHmmsXxARReYDwLMz2f7CQQkJkq82WxfoCqI8vxSVFXtpMVhQlwGjkZQguNy8T0QlZR+yjTDFdTMw+Akqep37i0DIUUwcxt70= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1715075000; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ewN5YfXgUpF8Cx+aqolyklTQ+08U+mpSJMGlBwx0Dlg=; b=f8KC0FMWDCtkt/mK0RZBBeZxRo2DWrVPbX9sXHq9g9Nvi94zJE9G27HkwN8SgNVVWAiqiUMjNcYMBLpMr/JWnKA2x1Drqc84yaN+/3+Ihpj8Sy9vwmFufG5h668rHVDYbn8i8ti+D1gU8Ab/eDZF4yB4jv4PWf2zNi/gZJr/hA8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1715075000649685.8939560732971; Tue, 7 May 2024 02:43:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s4HLX-0004Pb-M6; Tue, 07 May 2024 05:42:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s4HLG-0004Jr-By for qemu-devel@nongnu.org; Tue, 07 May 2024 05:42:35 -0400 Received: from mail-ot1-x32d.google.com ([2607:f8b0:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s4HLE-0007QJ-9Z for qemu-devel@nongnu.org; Tue, 07 May 2024 05:42:34 -0400 Received: by mail-ot1-x32d.google.com with SMTP id 46e09a7af769-6ed3587b93bso1814043a34.1 for ; Tue, 07 May 2024 02:42:31 -0700 (PDT) Received: from mnissler.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id p4-20020a62ab04000000b006f45257d3f7sm6434114pff.45.2024.05.07.02.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 May 2024 02:42:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1715074950; x=1715679750; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ewN5YfXgUpF8Cx+aqolyklTQ+08U+mpSJMGlBwx0Dlg=; b=YvYgW7hFjIXFmikyyyYftrCtGZFE5u+AXqIHvc4eiKu1WQNQ+k1R/Pa01JhdetfKx5 zqWplDi1Onw4kLONIWfmMg5L8XLZoZFtKFjej5l9ddAnr+ckP5dY0g5EfMga+GmDvL2Y 5sabjOlPyilcKL71ACW0/W8urAhpRSGCkKqs3YDGihZkbgfAe0l/GvBxPgY/OLaj9kkz 3OjNDzlbZ2W4b47XT+8XzgBm0n/nYQCYQT7CVrDyf75AUJClTN7jy+LN34kmvsvKcOJ0 NtKvUeNyfp1dLxHKKwdolblGBDh+05lpyNpnVeMA0No8ln4NIqSpgj106DWRmO+GTvbP WklQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715074950; x=1715679750; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ewN5YfXgUpF8Cx+aqolyklTQ+08U+mpSJMGlBwx0Dlg=; b=KPhaQkcBex3rpK9xqSBvU91DsDbhm0n3pOZW5T4hMhNRdMQOXVq57BvwDWyYmW511I EfReqs+hFU+g0HqYk04VCm8+JaxIwsIU/5OoLRiDLd1DL2ntw/PkEX2v5pekaa1XUJi4 EZRM/Abrp7V2LvC6krbbej6w2Fg+4/MLPXR4UHS4fExJaTWLG4/c4xMldtUILTaRuKwu qVRhFl15Ur0kVrlfMtR6rQ/qO7Od5vxe0TomDAcraksUl2GXSOGVs/ivOiARcXRu7sFU 3x53DwUBhpLRbtWA7sKQWlTuUfu8IYcKvOpjqZSQE1wPjXuCvdEQa8EK3u9970UsuTmV Aq4g== X-Forwarded-Encrypted: i=1; AJvYcCVO5mI7IvRTH+O8AayUgj9IZmKeT8knF8MpItpeNzy/x62Uo9XoIXAOcIXsm1XzwsSSegiRyfPcIbv5s3pGrq3/fw0REOo= X-Gm-Message-State: AOJu0Yzu8g1v6/jI5WUrX+RQOFsW/3Ay3UiuM8Rxsysn2T9cUMdJLhb9 8l0kqGrBhax2j+oGwO9K7//a9BthjZT55hwzVrpsuiEdh0O4Uobu7HwsSEqoSqn0rmF3L49XDN7 QAvs= X-Google-Smtp-Source: AGHT+IHYzwVUdNOxjML2aJXwljgWyN/FbRxpDMsUPtArjV4772T89nd8x2l7CEDrrDx40hWBeIbBUA== X-Received: by 2002:a05:6870:40c7:b0:233:56e5:ff99 with SMTP id l7-20020a05687040c700b0023356e5ff99mr13847055oal.23.1715074950498; Tue, 07 May 2024 02:42:30 -0700 (PDT) From: Mattias Nissler To: stefanha@redhat.com, qemu-devel@nongnu.org, peterx@redhat.com, jag.raman@oracle.com Cc: "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , David Hildenbrand , Richard Henderson , Paolo Bonzini , Elena Ufimtseva , john.levon@nutanix.com, Mattias Nissler Subject: [PATCH v9 4/5] vfio-user: Message-based DMA support Date: Tue, 7 May 2024 02:42:08 -0700 Message-ID: <20240507094210.300566-5-mnissler@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240507094210.300566-1-mnissler@rivosinc.com> References: <20240507094210.300566-1-mnissler@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=mnissler@rivosinc.com; helo=mail-ot1-x32d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1715075000909100002 Content-Type: text/plain; charset="utf-8" Wire up support for DMA for the case where the vfio-user client does not provide mmap()-able file descriptors, but DMA requests must be performed via the VFIO-user protocol. This installs an indirect memory region, which already works for pci_dma_{read,write}, and pci_dma_map works thanks to the existing DMA bounce buffering support. Note that while simple scenarios work with this patch, there's a known race condition in libvfio-user that will mess up the communication channel. See https://github.com/nutanix/libvfio-user/issues/279 for details as well as a proposed fix. Reviewed-by: Jagannathan Raman Signed-off-by: Mattias Nissler --- hw/remote/trace-events | 2 + hw/remote/vfio-user-obj.c | 100 ++++++++++++++++++++++++++++++++------ 2 files changed, 87 insertions(+), 15 deletions(-) diff --git a/hw/remote/trace-events b/hw/remote/trace-events index 0d1b7d56a5..358a68fb34 100644 --- a/hw/remote/trace-events +++ b/hw/remote/trace-events @@ -9,6 +9,8 @@ vfu_cfg_read(uint32_t offset, uint32_t val) "vfu: cfg: 0x%x= -> 0x%x" vfu_cfg_write(uint32_t offset, uint32_t val) "vfu: cfg: 0x%x <- 0x%x" vfu_dma_register(uint64_t gpa, size_t len) "vfu: registering GPA 0x%"PRIx6= 4", %zu bytes" vfu_dma_unregister(uint64_t gpa) "vfu: unregistering GPA 0x%"PRIx64"" +vfu_dma_read(uint64_t gpa, size_t len) "vfu: DMA read 0x%"PRIx64", %zu byt= es" +vfu_dma_write(uint64_t gpa, size_t len) "vfu: DMA write 0x%"PRIx64", %zu b= ytes" vfu_bar_register(int i, uint64_t addr, uint64_t size) "vfu: BAR %d: addr 0= x%"PRIx64" size 0x%"PRIx64"" vfu_bar_rw_enter(const char *op, uint64_t addr) "vfu: %s request for BAR a= ddress 0x%"PRIx64"" vfu_bar_rw_exit(const char *op, uint64_t addr) "vfu: Finished %s of BAR ad= dress 0x%"PRIx64"" diff --git a/hw/remote/vfio-user-obj.c b/hw/remote/vfio-user-obj.c index d9b879e056..a15e291c9a 100644 --- a/hw/remote/vfio-user-obj.c +++ b/hw/remote/vfio-user-obj.c @@ -300,6 +300,63 @@ static ssize_t vfu_object_cfg_access(vfu_ctx_t *vfu_ct= x, char * const buf, return count; } =20 +static MemTxResult vfu_dma_read(void *opaque, hwaddr addr, uint64_t *val, + unsigned size, MemTxAttrs attrs) +{ + MemoryRegion *region =3D opaque; + vfu_ctx_t *vfu_ctx =3D VFU_OBJECT(region->owner)->vfu_ctx; + uint8_t buf[sizeof(uint64_t)]; + + trace_vfu_dma_read(region->addr + addr, size); + + g_autofree dma_sg_t *sg =3D g_malloc0(dma_sg_size()); + vfu_dma_addr_t vfu_addr =3D (vfu_dma_addr_t)(region->addr + addr); + if (vfu_addr_to_sgl(vfu_ctx, vfu_addr, size, sg, 1, PROT_READ) < 0 || + vfu_sgl_read(vfu_ctx, sg, 1, buf) !=3D 0) { + return MEMTX_ERROR; + } + + *val =3D ldn_he_p(buf, size); + + return MEMTX_OK; +} + +static MemTxResult vfu_dma_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) +{ + MemoryRegion *region =3D opaque; + vfu_ctx_t *vfu_ctx =3D VFU_OBJECT(region->owner)->vfu_ctx; + uint8_t buf[sizeof(uint64_t)]; + + trace_vfu_dma_write(region->addr + addr, size); + + stn_he_p(buf, size, val); + + g_autofree dma_sg_t *sg =3D g_malloc0(dma_sg_size()); + vfu_dma_addr_t vfu_addr =3D (vfu_dma_addr_t)(region->addr + addr); + if (vfu_addr_to_sgl(vfu_ctx, vfu_addr, size, sg, 1, PROT_WRITE) < 0 || + vfu_sgl_write(vfu_ctx, sg, 1, buf) !=3D 0) { + return MEMTX_ERROR; + } + + return MEMTX_OK; +} + +static const MemoryRegionOps vfu_dma_ops =3D { + .read_with_attrs =3D vfu_dma_read, + .write_with_attrs =3D vfu_dma_write, + .endianness =3D DEVICE_HOST_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + .unaligned =3D true, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + static void dma_register(vfu_ctx_t *vfu_ctx, vfu_dma_info_t *info) { VfuObject *o =3D vfu_get_private(vfu_ctx); @@ -308,17 +365,30 @@ static void dma_register(vfu_ctx_t *vfu_ctx, vfu_dma_= info_t *info) g_autofree char *name =3D NULL; struct iovec *iov =3D &info->iova; =20 - if (!info->vaddr) { - return; - } - name =3D g_strdup_printf("mem-%s-%"PRIx64"", o->device, - (uint64_t)info->vaddr); + (uint64_t)iov->iov_base); =20 subregion =3D g_new0(MemoryRegion, 1); =20 - memory_region_init_ram_ptr(subregion, NULL, name, - iov->iov_len, info->vaddr); + if (info->vaddr) { + memory_region_init_ram_ptr(subregion, OBJECT(o), name, + iov->iov_len, info->vaddr); + } else { + /* + * Note that I/O regions' MemoryRegionOps handle accesses of at mo= st 8 + * bytes at a time, and larger accesses are broken down. However, + * many/most DMA accesses are larger than 8 bytes and VFIO-user can + * handle large DMA accesses just fine, thus this size restriction + * unnecessarily hurts performance, in particular given that each + * access causes a round trip on the VFIO-user socket. + * + * TODO: Investigate how to plumb larger accesses through memory + * regions, possibly by amending MemoryRegionOps or by creating a = new + * memory region type. + */ + memory_region_init_io(subregion, OBJECT(o), &vfu_dma_ops, subregio= n, + name, iov->iov_len); + } =20 dma_as =3D pci_device_iommu_address_space(o->pci_dev); =20 @@ -330,20 +400,20 @@ static void dma_register(vfu_ctx_t *vfu_ctx, vfu_dma_= info_t *info) static void dma_unregister(vfu_ctx_t *vfu_ctx, vfu_dma_info_t *info) { VfuObject *o =3D vfu_get_private(vfu_ctx); + MemoryRegionSection mr_section; AddressSpace *dma_as =3D NULL; - MemoryRegion *mr =3D NULL; - ram_addr_t offset; =20 - mr =3D memory_region_from_host(info->vaddr, &offset); - if (!mr) { + dma_as =3D pci_device_iommu_address_space(o->pci_dev); + + mr_section =3D + memory_region_find(dma_as->root, (hwaddr)info->iova.iov_base, 1); + if (!mr_section.mr) { return; } =20 - dma_as =3D pci_device_iommu_address_space(o->pci_dev); - - memory_region_del_subregion(dma_as->root, mr); + memory_region_del_subregion(dma_as->root, mr_section.mr); =20 - object_unparent((OBJECT(mr))); + object_unparent((OBJECT(mr_section.mr))); =20 trace_vfu_dma_unregister((uint64_t)info->iova.iov_base); } --=20 2.43.2