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Mon, 06 May 2024 01:10:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGakMioupiMs26QN5IKeVEpaLiRwPQcs7rbX+drMOML3EadBvz4BOoNBxd287oj5aT5v5ZufA== X-Received: by 2002:ac2:51b3:0:b0:515:a8c9:6e99 with SMTP id f19-20020ac251b3000000b00515a8c96e99mr7441012lfk.5.1714983009052; Mon, 06 May 2024 01:10:09 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, zhao1.liu@intel.com Subject: [PATCH v2 03/25] target/i386: remove mask from CCPrepare Date: Mon, 6 May 2024 10:09:35 +0200 Message-ID: <20240506080957.10005-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240506080957.10005-1-pbonzini@redhat.com> References: <20240506080957.10005-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.431, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1714983073420100003 Content-Type: text/plain; charset="utf-8" With the introduction of TSTEQ and TSTNE the .mask field is always -1, so remove all the now-unnecessary code. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 81 +++++++++++++------------------------ 1 file changed, 27 insertions(+), 54 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 62ba21c1d74..9aecd415b38 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -923,7 +923,6 @@ typedef struct CCPrepare { TCGv reg; TCGv reg2; target_ulong imm; - target_ulong mask; bool use_reg2; bool no_setcond; } CCPrepare; @@ -931,9 +930,9 @@ typedef struct CCPrepare { static CCPrepare gen_prepare_sign_nz(TCGv src, MemOp size) { if (size =3D=3D MO_TL) { - return (CCPrepare) { .cond =3D TCG_COND_LT, .reg =3D src, .mask = =3D -1 }; + return (CCPrepare) { .cond =3D TCG_COND_LT, .reg =3D src }; } else { - return (CCPrepare) { .cond =3D TCG_COND_TSTNE, .reg =3D src, .mask= =3D -1, + return (CCPrepare) { .cond =3D TCG_COND_TSTNE, .reg =3D src, .imm =3D 1ull << ((8 << size) - 1) }; } } @@ -962,17 +961,17 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s= , TCGv reg) t0 =3D gen_ext_tl(reg, cpu_cc_dst, size, false); add_sub: return (CCPrepare) { .cond =3D TCG_COND_LTU, .reg =3D t0, - .reg2 =3D t1, .mask =3D -1, .use_reg2 =3D tru= e }; + .reg2 =3D t1, .use_reg2 =3D true }; =20 case CC_OP_LOGICB ... CC_OP_LOGICQ: case CC_OP_CLR: case CC_OP_POPCNT: - return (CCPrepare) { .cond =3D TCG_COND_NEVER, .mask =3D -1 }; + return (CCPrepare) { .cond =3D TCG_COND_NEVER }; =20 case CC_OP_INCB ... CC_OP_INCQ: case CC_OP_DECB ... CC_OP_DECQ: return (CCPrepare) { .cond =3D TCG_COND_NE, .reg =3D cpu_cc_src, - .mask =3D -1, .no_setcond =3D true }; + .no_setcond =3D true }; =20 case CC_OP_SHLB ... CC_OP_SHLQ: /* (CC_SRC >> (DATA_BITS - 1)) & 1 */ @@ -981,23 +980,23 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s= , TCGv reg) =20 case CC_OP_MULB ... CC_OP_MULQ: return (CCPrepare) { .cond =3D TCG_COND_NE, - .reg =3D cpu_cc_src, .mask =3D -1 }; + .reg =3D cpu_cc_src }; =20 case CC_OP_BMILGB ... CC_OP_BMILGQ: size =3D s->cc_op - CC_OP_BMILGB; t0 =3D gen_ext_tl(reg, cpu_cc_src, size, false); - return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D t0, .mask =3D= -1 }; + return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D t0 }; =20 case CC_OP_ADCX: case CC_OP_ADCOX: return (CCPrepare) { .cond =3D TCG_COND_NE, .reg =3D cpu_cc_dst, - .mask =3D -1, .no_setcond =3D true }; + .no_setcond =3D true }; =20 case CC_OP_EFLAGS: case CC_OP_SARB ... CC_OP_SARQ: /* CC_SRC & 1 */ return (CCPrepare) { .cond =3D TCG_COND_TSTNE, - .reg =3D cpu_cc_src, .mask =3D -1, .imm =3D C= C_C }; + .reg =3D cpu_cc_src, .imm =3D CC_C }; =20 default: /* The need to compute only C from CC_OP_DYNAMIC is important @@ -1006,7 +1005,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s= , TCGv reg) gen_helper_cc_compute_c(reg, cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_op); return (CCPrepare) { .cond =3D TCG_COND_NE, .reg =3D reg, - .mask =3D -1, .no_setcond =3D true }; + .no_setcond =3D true }; } } =20 @@ -1015,7 +1014,7 @@ static CCPrepare gen_prepare_eflags_p(DisasContext *s= , TCGv reg) { gen_compute_eflags(s); return (CCPrepare) { .cond =3D TCG_COND_TSTNE, .reg =3D cpu_cc_src, - .mask =3D -1, .imm =3D CC_P }; + .imm =3D CC_P }; } =20 /* compute eflags.S to reg */ @@ -1030,10 +1029,10 @@ static CCPrepare gen_prepare_eflags_s(DisasContext = *s, TCGv reg) case CC_OP_ADOX: case CC_OP_ADCOX: return (CCPrepare) { .cond =3D TCG_COND_TSTNE, .reg =3D cpu_cc_src, - .mask =3D -1, .imm =3D CC_S }; + .imm =3D CC_S }; case CC_OP_CLR: case CC_OP_POPCNT: - return (CCPrepare) { .cond =3D TCG_COND_NEVER, .mask =3D -1 }; + return (CCPrepare) { .cond =3D TCG_COND_NEVER }; default: { MemOp size =3D (s->cc_op - CC_OP_ADDB) & 3; @@ -1049,17 +1048,16 @@ static CCPrepare gen_prepare_eflags_o(DisasContext = *s, TCGv reg) case CC_OP_ADOX: case CC_OP_ADCOX: return (CCPrepare) { .cond =3D TCG_COND_NE, .reg =3D cpu_cc_src2, - .mask =3D -1, .no_setcond =3D true }; + .no_setcond =3D true }; case CC_OP_CLR: case CC_OP_POPCNT: - return (CCPrepare) { .cond =3D TCG_COND_NEVER, .mask =3D -1 }; + return (CCPrepare) { .cond =3D TCG_COND_NEVER }; case CC_OP_MULB ... CC_OP_MULQ: - return (CCPrepare) { .cond =3D TCG_COND_NE, - .reg =3D cpu_cc_src, .mask =3D -1 }; + return (CCPrepare) { .cond =3D TCG_COND_NE, .reg =3D cpu_cc_src }; default: gen_compute_eflags(s); return (CCPrepare) { .cond =3D TCG_COND_TSTNE, .reg =3D cpu_cc_src, - .mask =3D -1, .imm =3D CC_O }; + .imm =3D CC_O }; } } =20 @@ -1075,21 +1073,19 @@ static CCPrepare gen_prepare_eflags_z(DisasContext = *s, TCGv reg) case CC_OP_ADOX: case CC_OP_ADCOX: return (CCPrepare) { .cond =3D TCG_COND_TSTNE, .reg =3D cpu_cc_src, - .mask =3D -1, .imm =3D CC_Z }; + .imm =3D CC_Z }; case CC_OP_CLR: - return (CCPrepare) { .cond =3D TCG_COND_ALWAYS, .mask =3D -1 }; + return (CCPrepare) { .cond =3D TCG_COND_ALWAYS }; case CC_OP_POPCNT: - return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D cpu_cc_src, - .mask =3D -1 }; + return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D cpu_cc_src }; default: { MemOp size =3D (s->cc_op - CC_OP_ADDB) & 3; if (size =3D=3D MO_TL) { - return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D cpu_c= c_dst, - .mask =3D -1 }; + return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D cpu_c= c_dst }; } else { return (CCPrepare) { .cond =3D TCG_COND_TSTEQ, .reg =3D cp= u_cc_dst, - .mask =3D -1, .imm =3D (1ull << (8 <<= size)) - 1 }; + .imm =3D (1ull << (8 << size)) - 1 }; } } } @@ -1117,7 +1113,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int = b, TCGv reg) gen_extu(size, s->tmp4); t0 =3D gen_ext_tl(s->tmp0, cpu_cc_src, size, false); cc =3D (CCPrepare) { .cond =3D TCG_COND_LEU, .reg =3D s->tmp4, - .reg2 =3D t0, .mask =3D -1, .use_reg2 =3D t= rue }; + .reg2 =3D t0, .use_reg2 =3D true }; break; =20 case JCC_L: @@ -1130,7 +1126,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int = b, TCGv reg) gen_exts(size, s->tmp4); t0 =3D gen_ext_tl(s->tmp0, cpu_cc_src, size, true); cc =3D (CCPrepare) { .cond =3D cond, .reg =3D s->tmp4, - .reg2 =3D t0, .mask =3D -1, .use_reg2 =3D t= rue }; + .reg2 =3D t0, .use_reg2 =3D true }; break; =20 default: @@ -1154,7 +1150,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int = b, TCGv reg) case JCC_BE: gen_compute_eflags(s); cc =3D (CCPrepare) { .cond =3D TCG_COND_TSTNE, .reg =3D cpu_cc= _src, - .mask =3D -1, .imm =3D CC_Z | CC_C }; + .imm =3D CC_Z | CC_C }; break; case JCC_S: cc =3D gen_prepare_eflags_s(s, reg); @@ -1169,7 +1165,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int = b, TCGv reg) } tcg_gen_addi_tl(reg, cpu_cc_src, CC_O - CC_S); cc =3D (CCPrepare) { .cond =3D TCG_COND_TSTNE, .reg =3D reg, - .mask =3D -1, .imm =3D CC_O }; + .imm =3D CC_O }; break; default: case JCC_LE: @@ -1179,7 +1175,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int = b, TCGv reg) } tcg_gen_addi_tl(reg, cpu_cc_src, CC_O - CC_S); cc =3D (CCPrepare) { .cond =3D TCG_COND_TSTNE, .reg =3D reg, - .mask =3D -1, .imm =3D CC_O | CC_Z }; + .imm =3D CC_O | CC_Z }; break; } break; @@ -1204,16 +1200,6 @@ static void gen_setcc1(DisasContext *s, int b, TCGv = reg) return; } =20 - if (cc.cond =3D=3D TCG_COND_NE && !cc.use_reg2 && cc.imm =3D=3D 0 && - cc.mask !=3D 0 && (cc.mask & (cc.mask - 1)) =3D=3D 0) { - tcg_gen_shri_tl(reg, cc.reg, ctztl(cc.mask)); - tcg_gen_andi_tl(reg, reg, 1); - return; - } - if (cc.mask !=3D -1) { - tcg_gen_andi_tl(reg, cc.reg, cc.mask); - cc.reg =3D reg; - } if (cc.use_reg2) { tcg_gen_setcond_tl(cc.cond, reg, cc.reg, cc.reg2); } else { @@ -1232,10 +1218,6 @@ static inline void gen_jcc1_noeob(DisasContext *s, i= nt b, TCGLabel *l1) { CCPrepare cc =3D gen_prepare_cc(s, b, s->T0); =20 - if (cc.mask !=3D -1) { - tcg_gen_andi_tl(s->T0, cc.reg, cc.mask); - cc.reg =3D s->T0; - } if (cc.use_reg2) { tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1); } else { @@ -1251,10 +1233,6 @@ static inline void gen_jcc1(DisasContext *s, int b, = TCGLabel *l1) CCPrepare cc =3D gen_prepare_cc(s, b, s->T0); =20 gen_update_cc_op(s); - if (cc.mask !=3D -1) { - tcg_gen_andi_tl(s->T0, cc.reg, cc.mask); - cc.reg =3D s->T0; - } set_cc_op(s, CC_OP_DYNAMIC); if (cc.use_reg2) { tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1); @@ -2519,11 +2497,6 @@ static void gen_cmovcc1(DisasContext *s, int b, TCGv= dest, TCGv src) { CCPrepare cc =3D gen_prepare_cc(s, b, s->T1); =20 - if (cc.mask !=3D -1) { - TCGv t0 =3D tcg_temp_new(); - tcg_gen_andi_tl(t0, cc.reg, cc.mask); - cc.reg =3D t0; - } if (!cc.use_reg2) { cc.reg2 =3D tcg_constant_tl(cc.imm); } --=20 2.45.0