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Mon, 06 May 2024 01:11:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGm/bRyirMtfTdNpoQcH3zneCD7u+riuR4NDkb0Py2F1fODwTMEg7iAfi5Bm6qVKagcJHW/wg== X-Received: by 2002:a50:a412:0:b0:570:d85:f296 with SMTP id u18-20020a50a412000000b005700d85f296mr8483905edb.26.1714983074365; Mon, 06 May 2024 01:11:14 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, zhao1.liu@intel.com Subject: [PATCH v2 25/25] target/i386: remove duplicate prefix decoding Date: Mon, 6 May 2024 10:09:57 +0200 Message-ID: <20240506080957.10005-26-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240506080957.10005-1-pbonzini@redhat.com> References: <20240506080957.10005-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.431, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1714983250237100003 Content-Type: text/plain; charset="utf-8" Now that a bulk of opcodes go through the new decoder, it is sensible to do some cleanup. Go immediately through disas_insn_new and only jump back after parsing the prefixes. disas_insn() now only contains the three sigsetjmp cases, and they are more easily managed if they are inlined into i386_tr_translate_insn. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 259 +++++++------------------------ target/i386/tcg/decode-new.c.inc | 60 +++++-- 2 files changed, 100 insertions(+), 219 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 8c1062c8e13..df6e046d0c3 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2450,10 +2450,6 @@ static void gen_sty_env_A0(DisasContext *s, int offs= et, bool align) tcg_gen_qemu_st_i128(t, s->tmp0, mem_index, mop); } =20 -#include "decode-new.h" -#include "emit.c.inc" -#include "decode-new.c.inc" - static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) { TCGv_i64 cmp, val, old; @@ -3116,183 +3112,6 @@ static bool disas_insn_x87(DisasContext *s, CPUStat= e *cpu, int b) return true; } =20 -static void disas_insn_old(DisasContext *s, CPUState *cpu, int b); - -/* convert one instruction. s->base.is_jmp is set if the translation must - be stopped. Return the next pc value */ -static bool disas_insn(DisasContext *s, CPUState *cpu) -{ - CPUX86State *env =3D cpu_env(cpu); - int b, prefixes; - MemOp aflag, dflag; - bool orig_cc_op_dirty =3D s->cc_op_dirty; - CCOp orig_cc_op =3D s->cc_op; - target_ulong orig_pc_save =3D s->pc_save; - - s->pc =3D s->base.pc_next; - s->override =3D -1; - s->popl_esp_hack =3D 0; -#ifdef TARGET_X86_64 - s->rex_r =3D 0; - s->rex_x =3D 0; - s->rex_b =3D 0; -#endif - s->rip_offset =3D 0; /* for relative ip address */ - s->vex_l =3D 0; - s->vex_v =3D 0; - s->vex_w =3D false; - switch (sigsetjmp(s->jmpbuf, 0)) { - case 0: - break; - case 1: - gen_exception_gpf(s); - return true; - case 2: - /* Restore state that may affect the next instruction. */ - s->pc =3D s->base.pc_next; - /* - * TODO: These save/restore can be removed after the table-based - * decoder is complete; we will be decoding the insn completely - * before any code generation that might affect these variables. - */ - s->cc_op_dirty =3D orig_cc_op_dirty; - s->cc_op =3D orig_cc_op; - s->pc_save =3D orig_pc_save; - /* END TODO */ - s->base.num_insns--; - tcg_remove_ops_after(s->prev_insn_end); - s->base.insn_start =3D s->prev_insn_start; - s->base.is_jmp =3D DISAS_TOO_MANY; - return false; - default: - g_assert_not_reached(); - } - - prefixes =3D 0; - - next_byte: - s->prefix =3D prefixes; - b =3D x86_ldub_code(env, s); - /* Collect prefixes. */ - switch (b) { - case 0x0f: - b =3D x86_ldub_code(env, s) + 0x100; - break; - case 0xf3: - prefixes |=3D PREFIX_REPZ; - prefixes &=3D ~PREFIX_REPNZ; - goto next_byte; - case 0xf2: - prefixes |=3D PREFIX_REPNZ; - prefixes &=3D ~PREFIX_REPZ; - goto next_byte; - case 0xf0: - prefixes |=3D PREFIX_LOCK; - goto next_byte; - case 0x2e: - s->override =3D R_CS; - goto next_byte; - case 0x36: - s->override =3D R_SS; - goto next_byte; - case 0x3e: - s->override =3D R_DS; - goto next_byte; - case 0x26: - s->override =3D R_ES; - goto next_byte; - case 0x64: - s->override =3D R_FS; - goto next_byte; - case 0x65: - s->override =3D R_GS; - goto next_byte; - case 0x66: - prefixes |=3D PREFIX_DATA; - goto next_byte; - case 0x67: - prefixes |=3D PREFIX_ADR; - goto next_byte; -#ifdef TARGET_X86_64 - case 0x40 ... 0x4f: - if (CODE64(s)) { - /* REX prefix */ - prefixes |=3D PREFIX_REX; - s->vex_w =3D (b >> 3) & 1; - s->rex_r =3D (b & 0x4) << 1; - s->rex_x =3D (b & 0x2) << 2; - s->rex_b =3D (b & 0x1) << 3; - goto next_byte; - } - break; -#endif - case 0xc5: /* 2-byte VEX */ - case 0xc4: /* 3-byte VEX */ - if (CODE32(s) && !VM86(s)) { - int vex2 =3D x86_ldub_code(env, s); - s->pc--; /* rewind the advance_pc() x86_ldub_code() did */ - - if (!CODE64(s) && (vex2 & 0xc0) !=3D 0xc0) { - /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b, - otherwise the instruction is LES or LDS. */ - break; - } - disas_insn_new(s, cpu, b); - return s->pc; - } - break; - } - - /* Post-process prefixes. */ - if (CODE64(s)) { - /* In 64-bit mode, the default data size is 32-bit. Select 64-bit - data with rex_w, and 16-bit data with 0x66; rex_w takes precede= nce - over 0x66 if both are present. */ - dflag =3D (REX_W(s) ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_= 32); - /* In 64-bit mode, 0x67 selects 32-bit addressing. */ - aflag =3D (prefixes & PREFIX_ADR ? MO_32 : MO_64); - } else { - /* In 16/32-bit mode, 0x66 selects the opposite data size. */ - if (CODE32(s) ^ ((prefixes & PREFIX_DATA) !=3D 0)) { - dflag =3D MO_32; - } else { - dflag =3D MO_16; - } - /* In 16/32-bit mode, 0x67 selects the opposite addressing. */ - if (CODE32(s) ^ ((prefixes & PREFIX_ADR) !=3D 0)) { - aflag =3D MO_32; - } else { - aflag =3D MO_16; - } - } - - s->prefix =3D prefixes; - s->aflag =3D aflag; - s->dflag =3D dflag; - - switch (b) { - case 0 ... 0xd7: - case 0xe0 ... 0xff: - case 0x10e ... 0x117: - case 0x128 ... 0x12f: - case 0x138 ... 0x19f: - case 0x1a0 ... 0x1a1: - case 0x1a8 ... 0x1a9: - case 0x1af: - case 0x1b2: - case 0x1b4 ... 0x1b7: - case 0x1be ... 0x1bf: - case 0x1c2 ... 0x1c6: - case 0x1c8 ... 0x1ff: - disas_insn_new(s, cpu, b); - break; - default: - disas_insn_old(s, cpu, b); - break; - } - return true; -} - static void disas_insn_old(DisasContext *s, CPUState *cpu, int b) { CPUX86State *env =3D cpu_env(cpu); @@ -3501,14 +3320,6 @@ static void disas_insn_old(DisasContext *s, CPUState= *cpu, int b) } break; =20 - /************************/ - /* floats */ - case 0xd8 ... 0xdf: - if (!disas_insn_x87(s, cpu, b)) { - goto unknown_op; - } - break; - /************************/ /* bit operations */ case 0x1ba: /* bt/bts/btr/btc Gv, im */ @@ -4758,7 +4569,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) set_cc_op(s, CC_OP_POPCNT); break; default: - goto unknown_op; + g_assert_not_reached(); } return; illegal_op: @@ -4768,6 +4579,10 @@ static void disas_insn_old(DisasContext *s, CPUState= *cpu, int b) gen_unknown_opcode(env, s); } =20 +#include "decode-new.h" +#include "emit.c.inc" +#include "decode-new.c.inc" + void tcg_x86_init(void) { static const char reg_names[CPU_NB_REGS][4] =3D { @@ -4889,7 +4704,6 @@ static void i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu) =20 dc->cc_op =3D CC_OP_DYNAMIC; dc->cc_op_dirty =3D false; - dc->popl_esp_hack =3D 0; /* select memory access functions */ dc->mem_index =3D cpu_mmu_index(cpu, false); dc->cpuid_features =3D env->features[FEAT_1_EDX]; @@ -4941,6 +4755,9 @@ static void i386_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); + bool orig_cc_op_dirty =3D dc->cc_op_dirty; + CCOp orig_cc_op =3D dc->cc_op; + target_ulong orig_pc_save =3D dc->pc_save; =20 #ifdef TARGET_VSYSCALL_PAGE /* @@ -4953,23 +4770,51 @@ static void i386_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) } #endif =20 - if (disas_insn(dc, cpu)) { - target_ulong pc_next =3D dc->pc; - dc->base.pc_next =3D pc_next; + switch (sigsetjmp(dc->jmpbuf, 0)) { + case 0: + disas_insn(dc, cpu); + break; + case 1: + gen_exception_gpf(dc); + break; + case 2: + /* Restore state that may affect the next instruction. */ + dc->pc =3D dc->base.pc_next; + /* + * TODO: These save/restore can be removed after the table-based + * decoder is complete; we will be decoding the insn completely + * before any code generation that might affect these variables. + */ + dc->cc_op_dirty =3D orig_cc_op_dirty; + dc->cc_op =3D orig_cc_op; + dc->pc_save =3D orig_pc_save; + /* END TODO */ + dc->base.num_insns--; + tcg_remove_ops_after(dc->prev_insn_end); + dc->base.insn_start =3D dc->prev_insn_start; + dc->base.is_jmp =3D DISAS_TOO_MANY; + return; + default: + g_assert_not_reached(); + } =20 - if (dc->base.is_jmp =3D=3D DISAS_NEXT) { - if (dc->flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)) { - /* - * If single step mode, we generate only one instruction a= nd - * generate an exception. - * If irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear - * the flag and abort the translation to give the irqs a - * chance to happen. - */ - dc->base.is_jmp =3D DISAS_EOB_NEXT; - } else if (!is_same_page(&dc->base, pc_next)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } + /* + * Instruction decoding completed (possibly with #GP if the + * 15-byte boundary was exceeded). + */ + dc->base.pc_next =3D dc->pc; + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + if (dc->flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)) { + /* + * If single step mode, we generate only one instruction and + * generate an exception. + * If irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear + * the flag and abort the translation to give the irqs a + * chance to happen. + */ + dc->base.is_jmp =3D DISAS_EOB_NEXT; + } else if (!is_same_page(&dc->base, dc->base.pc_next)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; } } } diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index 14218882681..46682cfe070 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -2219,22 +2219,31 @@ illegal: * Convert one instruction. s->base.is_jmp is set if the translation must * be stopped. */ -static void disas_insn_new(DisasContext *s, CPUState *cpu, int b) +static void disas_insn(DisasContext *s, CPUState *cpu) { CPUX86State *env =3D cpu_env(cpu); - bool first =3D true; X86DecodedInsn decode; X86DecodeFunc decode_func =3D decode_root; - uint8_t cc_live; + uint8_t cc_live, b; =20 + s->pc =3D s->base.pc_next; + s->override =3D -1; + s->popl_esp_hack =3D 0; +#ifdef TARGET_X86_64 + s->rex_r =3D 0; + s->rex_x =3D 0; + s->rex_b =3D 0; +#endif + s->rip_offset =3D 0; /* for relative ip address */ + s->vex_l =3D 0; + s->vex_v =3D 0; + s->vex_w =3D false; s->has_modrm =3D false; + s->prefix =3D 0; =20 next_byte: - if (first) { - first =3D false; - } else { - b =3D x86_ldub_code(env, s); - } + b =3D x86_ldub_code(env, s); + /* Collect prefixes. */ switch (b) { case 0xf3: @@ -2346,10 +2355,6 @@ static void disas_insn_new(DisasContext *s, CPUState= *cpu, int b) } break; default: - if (b >=3D 0x100) { - b -=3D 0x100; - decode_func =3D do_decode_0F; - } break; } =20 @@ -2378,6 +2383,37 @@ static void disas_insn_new(DisasContext *s, CPUState= *cpu, int b) } } =20 + /* Go back to old decoder for unconverted opcodes. */ + if (!(s->prefix & PREFIX_VEX)) { + if ((b & ~7) =3D=3D 0xd8) { + if (!disas_insn_x87(s, cpu, b)) { + goto unknown_op; + } + return; + } + + if (b =3D=3D 0x0f) { + b =3D x86_ldub_code(env, s); + switch (b) { + case 0x00 ... 0x0d: /* mostly privileged instructions */ + case 0x18 ... 0x27: /* prefetch, MPX, mov from/to CR and DR */ + case 0x30 ... 0x37: /* more privileged instructions */ + case 0xa2 ... 0xa7: /* CPUID, BT, SHLD */ + case 0xaa ... 0xae: /* RSM, SHRD, grp15 */ + case 0xb0 ... 0xb1: /* cmpxchg */ + case 0xb3: /* btr */ + case 0xb8 ... 0xbd: /* integer ops */ + case 0xc0 ... 0xc1: /* xadd */ + case 0xc7: /* grp9 */ + disas_insn_old(s, cpu, b + 0x100); + return; + default: + decode_func =3D do_decode_0F; + break; + } + } + } + memset(&decode, 0, sizeof(decode)); decode.cc_op =3D -1; decode.b =3D b; --=20 2.45.0