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Mon, 06 May 2024 01:11:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFsIwsUsm7ETinu6hxHriZOD24QCUttvcbW3F2C8anuLfep/AWW6JL/qt6ylr6rDsCVlrP+BA== X-Received: by 2002:a50:8d13:0:b0:572:6f3d:7208 with SMTP id s19-20020a508d13000000b005726f3d7208mr6178487eds.29.1714983061307; Mon, 06 May 2024 01:11:01 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, zhao1.liu@intel.com Subject: [PATCH v2 21/25] target/i386: port extensions of one-byte opcodes to new decoder Date: Mon, 6 May 2024 10:09:53 +0200 Message-ID: <20240506080957.10005-22-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240506080957.10005-1-pbonzini@redhat.com> References: <20240506080957.10005-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.431, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1714983340413100003 Content-Type: text/plain; charset="utf-8" A few two-byte opcodes are simple extensions of existing one-byte opcodes; they are easy to decode and need no change to emit.c.inc. Port them to the new decoder. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.h | 1 + target/i386/tcg/translate.c | 4 ++++ target/i386/tcg/decode-new.c.inc | 31 +++++++++++++++++++++++++++++++ target/i386/tcg/emit.c.inc | 15 +++++++++++++++ 4 files changed, 51 insertions(+) diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h index cd7ceca21e8..2ea06b44787 100644 --- a/target/i386/tcg/decode-new.h +++ b/target/i386/tcg/decode-new.h @@ -47,6 +47,7 @@ typedef enum X86OpType { X86_TYPE_Y, /* string destination */ =20 /* Custom */ + X86_TYPE_EM, /* modrm byte selects an ALU memory operand */ X86_TYPE_WM, /* modrm byte selects an XMM/YMM memory operand */ X86_TYPE_I_unsigned, /* Immediate, zero-extended */ X86_TYPE_2op, /* 2-operand RMW instruction */ diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 87ecf082316..14417b961ce 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3208,6 +3208,10 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) #endif if (use_new && ((b >=3D 0x138 && b <=3D 0x19f) || + (b & ~9) =3D=3D 0x1a0 || + b =3D=3D 0x1af || b =3D=3D 0x1b2 || + (b >=3D 0x1b4 && b <=3D 0x1b7) || + b =3D=3D 0x1be || b =3D=3D 0x1bf || b =3D=3D 0x1c3 || (b >=3D 0x1c8 && b <=3D 0x1cf))) { disas_insn_new(s, cpu, b); return true; diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index e65fa208a43..8311b479846 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -43,6 +43,12 @@ * Operand types * ------------- * + * For memory-only operands, if the emitter functions wants to rely on + * generic load and writeback, the decoder needs to know the type of the + * operand. Therefore, M is often replaced by the more specific EM and WM + * (respectively selecting an ALU operand, like the operand type E, or a + * vector operand like the operand type W). + * * Immediates are almost always signed or masked away in helpers. Two * common exceptions are IN/OUT and absolute jumps. For these, there is * an additional custom operand type "I_unsigned". Alternatively, the @@ -1047,6 +1053,9 @@ static const X86OpEntry opcodes_0F[256] =3D { [0x96] =3D X86_OP_ENTRYw(SETcc, E,b), [0x97] =3D X86_OP_ENTRYw(SETcc, E,b), =20 + [0xa0] =3D X86_OP_ENTRYr(PUSH, FS, w), + [0xa1] =3D X86_OP_ENTRYw(POP, FS, w), + [0x28] =3D X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_6= 6), /* MOVAPS */ [0x29] =3D X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_6= 6), /* MOVAPS */ [0x2A] =3D X86_OP_GROUP0(0F2A), @@ -1111,9 +1120,26 @@ static const X86OpEntry opcodes_0F[256] =3D { [0x9e] =3D X86_OP_ENTRYw(SETcc, E,b), [0x9f] =3D X86_OP_ENTRYw(SETcc, E,b), =20 + [0xa8] =3D X86_OP_ENTRYr(PUSH, GS, w), + [0xa9] =3D X86_OP_ENTRYw(POP, GS, w), [0xae] =3D X86_OP_GROUP0(group15), + /* + * It's slightly more efficient to put Ev operand in T0 and allow gen_= IMUL3 + * to assume sextT0. Multiplication is commutative anyway. + */ + [0xaf] =3D X86_OP_ENTRY3(IMUL3, G,v, E,v, 2op,v, sextT0), + + [0xb2] =3D X86_OP_ENTRY3(LSS, G,v, M,p, None, None), + [0xb4] =3D X86_OP_ENTRY3(LFS, G,v, M,p, None, None), + [0xb5] =3D X86_OP_ENTRY3(LGS, G,v, M,p, None, None), + [0xb6] =3D X86_OP_ENTRY3(MOV, G,v, E,b, None, None, zextT0), /* MOV= ZX */ + [0xb7] =3D X86_OP_ENTRY3(MOV, G,v, E,w, None, None, zextT0), /* MOV= ZX */ + + [0xbe] =3D X86_OP_ENTRY3(MOV, G,v, E,b, None, None, sextT0), /* MOV= SX */ + [0xbf] =3D X86_OP_ENTRY3(MOV, G,v, E,w, None, None, sextT0), /* MOV= SX */ =20 [0xc2] =3D X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_= 00_66_f3_f2), + [0xc3] =3D X86_OP_ENTRY3(MOV, EM,y,G,y, None,None, cpuid(SSE2))= , /* MOVNTI */ [0xc4] =3D X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_0= 0_66), [0xc5] =3D X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_0= 0_66), [0xc6] =3D X86_OP_ENTRY4(VSHUF, V,x, H,x, W,x, vex4 p_00_66= ), @@ -1815,8 +1841,13 @@ static bool decode_op(DisasContext *s, CPUX86State *= env, X86DecodedInsn *decode, =20 case X86_TYPE_WM: /* modrm byte selects an XMM/YMM memory operand */ op->unit =3D X86_OP_SSE; + goto get_modrm_mem; + + case X86_TYPE_EM: /* modrm byte selects an ALU memory operand */ + op->unit =3D X86_OP_INT; /* fall through */ case X86_TYPE_M: /* modrm byte selects a memory operand */ + get_modrm_mem: modrm =3D get_modrm(s, env); if ((modrm >> 6) =3D=3D 3) { return false; diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index c826adbbbb8..01aed001075 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1979,6 +1979,16 @@ static void gen_LES(DisasContext *s, CPUX86State *en= v, X86DecodedInsn *decode) gen_lxx_seg(s, env, decode, R_ES); } =20 +static void gen_LFS(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + gen_lxx_seg(s, env, decode, R_FS); +} + +static void gen_LGS(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + gen_lxx_seg(s, env, decode, R_GS); +} + static void gen_LODS(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) { MemOp ot =3D decode->op[2].ot; @@ -2023,6 +2033,11 @@ static void gen_LOOPNE(DisasContext *s, CPUX86State = *env, X86DecodedInsn *decode gen_conditional_jump_labels(s, decode->immediate, not_taken, taken); } =20 +static void gen_LSS(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + gen_lxx_seg(s, env, decode, R_SS); +} + static void gen_MOV(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) { /* nothing to do! */ --=20 2.45.0