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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-mips-smp-v1-1-3cc234786910@flygoat.com> References: <20240506-mips-smp-v1-0-3cc234786910@flygoat.com> In-Reply-To: <20240506-mips-smp-v1-0-3cc234786910@flygoat.com> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3976; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=CJg+yb6JSEoXL9V2aoefjDejZ9YFbsgnL4KcYazjW70=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjSL74+bF+kt7ckz/LWGMWIl23a5xZLH/mrsP1Evvt1p1 evutwpLOkpZGMQ4GGTFFFlCBJT6NjReXHD9QdYfmDmsTCBDGLg4BWAiyT2MDIfU1DY9vsxQo712 rd+ZU7ndDiynp1uW3UoVl9F/4DzHQJGRYclvFsvlkxpmuN1rmJvknPZvusrq1O9etr+WR2atObs jiAsA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.152; envelope-from=jiaxun.yang@flygoat.com; helo=wfhigh1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @flygoat.com) X-ZM-MESSAGEID: 1715009558240100001 GlobalNumber marks topology information of a CPU instance. Make it a CPU property to allow CPS to override topology information. Signed-off-by: Jiaxun Yang --- target/mips/cpu.c | 16 +++++++++++++++- target/mips/cpu.h | 10 +++++++++- target/mips/sysemu/machine.c | 5 ++--- 3 files changed, 26 insertions(+), 5 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bbe01d07dd..762000d09b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -296,7 +296,6 @@ static void mips_cpu_reset_hold(Object *obj, ResetType = type) env->CP0_Random =3D env->tlb->nb_tlb - 1; env->tlb->tlb_in_use =3D env->tlb->nb_tlb; env->CP0_Wired =3D 0; - env->CP0_GlobalNumber =3D (cs->cpu_index & 0xFF) << CP0GN_VPId; env->CP0_EBase =3D KSEG0_BASE | (cs->cpu_index & 0x3FF); if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { env->CP0_CMGCRBase =3D 0x1fbf8000 >> 4; @@ -484,6 +483,12 @@ static void mips_cpu_realizefn(DeviceState *dev, Error= **errp) =20 env->exception_base =3D (int32_t)0xBFC00000; =20 +#if !defined(CONFIG_USER_ONLY) + if (env->CP0_GlobalNumber =3D=3D -1) { + env->CP0_GlobalNumber =3D (cs->cpu_index & 0xFF) << CP0GN_VPId; + } +#endif + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) mmu_init(env, env->cpu_model); #endif @@ -563,6 +568,13 @@ static const TCGCPUOps mips_tcg_ops =3D { }; #endif /* CONFIG_TCG */ =20 +static Property mips_cpu_properties[] =3D { +#if !defined(CONFIG_USER_ONLY) + DEFINE_PROP_INT32("globalnumber", MIPSCPU, env.CP0_GlobalNumber, -1), +#endif + DEFINE_PROP_END_OF_LIST(), +}; + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(c); @@ -592,6 +604,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) #ifdef CONFIG_TCG cc->tcg_ops =3D &mips_tcg_ops; #endif /* CONFIG_TCG */ + + device_class_set_props(dc, mips_cpu_properties); } =20 static const TypeInfo mips_cpu_type_info =3D { diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3e906a175a..7499608678 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -612,8 +612,13 @@ typedef struct CPUArchState { # define CP0EnLo_RI 31 # define CP0EnLo_XI 30 #endif - int32_t CP0_GlobalNumber; + /* CP0_GlobalNumber is preserved across CPU reset. */ #define CP0GN_VPId 0 +#define CP0GN_VPId_MASK (0xFFUL << CP0GN_VPId) +#define CP0GN_CoreNum 8 +#define CP0GN_CoreNum_MASK (0xFUL << CP0GN_CoreNum) +#define CP0GN_ClusterNum 16 +#define CP0GN_ClusterNum_MASK (0xFUL << CP0GN_ClusterNum) /* * CP0 Register 4 */ @@ -1175,6 +1180,9 @@ typedef struct CPUArchState { struct {} end_reset_fields; =20 /* Fields from here on are preserved across CPU reset. */ +#if !defined(CONFIG_USER_ONLY) + int32_t CP0_GlobalNumber; +#endif CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c index 213fd637fc..235d640862 100644 --- a/target/mips/sysemu/machine.c +++ b/target/mips/sysemu/machine.c @@ -218,8 +218,8 @@ static const VMStateDescription vmstate_tlb =3D { =20 const VMStateDescription vmstate_mips_cpu =3D { .name =3D "cpu", - .version_id =3D 21, - .minimum_version_id =3D 21, + .version_id =3D 22, + .minimum_version_id =3D 22, .post_load =3D cpu_post_load, .fields =3D (const VMStateField[]) { /* Active TC */ @@ -257,7 +257,6 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU), VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU), VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU), - VMSTATE_INT32(env.CP0_GlobalNumber, MIPSCPU), VMSTATE_UINTTL(env.CP0_Context, MIPSCPU), VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU), VMSTATE_INT32(env.CP0_PageMask, MIPSCPU), --=20 2.34.1