From nobody Tue Feb 10 20:54:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714659494693102.46749390692673; Thu, 2 May 2024 07:18:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s2XFM-0002v2-2Q; Thu, 02 May 2024 10:17:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s2XFG-0002uG-Ck; Thu, 02 May 2024 10:17:10 -0400 Received: from new-mail.astralinux.ru ([51.250.53.244]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s2XFB-0007KH-OS; Thu, 02 May 2024 10:17:09 -0400 Received: from rbta-msk-lt-302690.astralinux.ru (unknown [10.177.234.226]) by new-mail.astralinux.ru (Postfix) with ESMTPA id 4VVbbQ6mlnzlVth; Thu, 2 May 2024 17:16:50 +0300 (MSK) From: Alexandra Diupina To: Alistair Francis Cc: Alexandra Diupina , "Konrad, Frederic" , "Edgar E. Iglesias" , Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org, sdl.qemu@linuxtesting.org Subject: [PATCH v5] xlnx_dpdma: fix descriptor endianness bug Date: Thu, 2 May 2024 17:16:28 +0300 Message-Id: <20240502141628.28103-1-adiupina@astralinux.ru> X-Mailer: git-send-email 2.30.2 In-Reply-To: <87y18u3hjf.fsf@draig.linaro.org> References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DrWeb-SpamScore: -100 X-DrWeb-SpamState: legit X-DrWeb-SpamDetail: gggruggvucftvghtrhhoucdtuddrgedvfedrvdehuddgtddvucetufdoteggodetrfcurfhrohhfihhlvgemucfftfghgfeunecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeetlhgvgigrnhgurhgrucffihhuphhinhgruceorgguihhuphhinhgrsegrshhtrhgrlhhinhhugidrrhhuqeenucggtffrrghtthgvrhhnpeefkedufedvkeffuedtgfdugeeutdegvdffffejfffgleffieduhfejvdelffdvudenucffohhmrghinheplhhinhhugihtvghsthhinhhgrdhorhhgnecukfhppedutddrudejjedrvdefgedrvddvieenucfrrghrrghmpehhvghloheprhgsthgrqdhmshhkqdhlthdqfedtvdeiledtrdgrshhtrhgrlhhinhhugidrrhhupdhinhgvthepuddtrddujeejrddvfeegrddvvdeimeegudehfeegpdhmrghilhhfrhhomheprgguihhuphhinhgrsegrshhtrhgrlhhinhhugidrrhhupdhnsggprhgtphhtthhopeekpdhrtghpthhtoheprghlihhsthgrihhrsegrlhhishhtrghirhdvfedrmhgvpdhrtghpthhtoheprgguihhuphhinhgrsegrshhtrhgrlhhinhhugidrrhhupdhrtghpthhtohephfhrvgguvghrihgtrdfmohhnrhgrugesrghmugdrtghomhdprhgtphhtthhopegvughgrghrrdhighhlvghsihgrshesghhmrghilhdrtghomhdprhgtphhtth hopehpvghtvghrrdhmrgihuggvlhhlsehlihhnrghrohdrohhrghdprhgtphhtthhopehqvghmuhdqrghrmhesnhhonhhgnhhurdhorhhgpdhrtghpthhtohepqhgvmhhuqdguvghvvghlsehnohhnghhnuhdrohhrghdprhgtphhtthhopehsughlrdhqvghmuheslhhinhhugihtvghsthhinhhgrdhorhhg X-DrWeb-SpamVersion: Vade Retro 01.423.251#02 AS+AV+AP Profile: DRWEB; Bailout: 300 X-AntiVirus: Checked by Dr.Web [MailD: 11.1.19.2307031128, SE: 11.1.12.2210241838, Core engine: 7.00.62.01180, Virus records: 12656802, Updated: 2024-May-02 12:36:40 UTC] Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=51.250.53.244; envelope-from=adiupina@astralinux.ru; helo=new-mail.astralinux.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1714659499407100003 Content-Type: text/plain; charset="utf-8" Add xlnx_dpdma_read_descriptor() and xlnx_dpdma_write_descriptor() functions. xlnx_dpdma_read_descriptor() combines reading a descriptor from desc_addr by calling dma_memory_read() and swapping the desc fields from guest memory order to host memory order. xlnx_dpdma_write_descriptor() performs similar actions when writing a descriptor. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: d3c6369a96 ("introduce xlnx-dpdma") Signed-off-by: Alexandra Diupina --- v5: fix subject and make xlnx_dpdma_write_descriptor() not void v4: remove rewriting desc in place v3: add xlnx_dpdma_write_descriptor() v2: minor changes in xlnx_dpdma_read_descriptor() hw/dma/xlnx_dpdma.c | 66 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 62 insertions(+), 4 deletions(-) diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c index 1f5cd64ed1..f582c1a085 100644 --- a/hw/dma/xlnx_dpdma.c +++ b/hw/dma/xlnx_dpdma.c @@ -614,6 +614,63 @@ static void xlnx_dpdma_register_types(void) type_register_static(&xlnx_dpdma_info); } =20 +static MemTxResult xlnx_dpdma_read_descriptor(XlnxDPDMAState *s, + uint64_t desc_addr, DPDMADescriptor *d= esc) +{ + MemTxResult res =3D dma_memory_read(&address_space_memory, desc_addr, + &desc, sizeof(DPDMADescriptor), MEMTXATTRS_UNSPECIFIED); + if (res) { + return res; + } + + /* Convert from LE into host endianness. */ + desc->control =3D le32_to_cpu(desc->control); + desc->descriptor_id =3D le32_to_cpu(desc->descriptor_id); + desc->xfer_size =3D le32_to_cpu(desc->xfer_size); + desc->line_size_stride =3D le32_to_cpu(desc->line_size_stride); + desc->timestamp_lsb =3D le32_to_cpu(desc->timestamp_lsb); + desc->timestamp_msb =3D le32_to_cpu(desc->timestamp_msb); + desc->address_extension =3D le32_to_cpu(desc->address_extension); + desc->next_descriptor =3D le32_to_cpu(desc->next_descriptor); + desc->source_address =3D le32_to_cpu(desc->source_address); + desc->address_extension_23 =3D le32_to_cpu(desc->address_extension_23); + desc->address_extension_45 =3D le32_to_cpu(desc->address_extension_45); + desc->source_address2 =3D le32_to_cpu(desc->source_address2); + desc->source_address3 =3D le32_to_cpu(desc->source_address3); + desc->source_address4 =3D le32_to_cpu(desc->source_address4); + desc->source_address5 =3D le32_to_cpu(desc->source_address5); + desc->crc =3D le32_to_cpu(desc->crc); + + return res; +} + +static MemTxResult xlnx_dpdma_write_descriptor(uint64_t desc_addr, + DPDMADescriptor *desc) +{ + DPDMADescriptor tmp_desc =3D *desc; + + /* Convert from host endianness into LE. */ + tmp_desc.control =3D cpu_to_le32(tmp_desc.control); + tmp_desc.descriptor_id =3D cpu_to_le32(tmp_desc.descriptor_id); + tmp_desc.xfer_size =3D cpu_to_le32(tmp_desc.xfer_size); + tmp_desc.line_size_stride =3D cpu_to_le32(tmp_desc.line_size_stride); + tmp_desc.timestamp_lsb =3D cpu_to_le32(tmp_desc.timestamp_lsb); + tmp_desc.timestamp_msb =3D cpu_to_le32(tmp_desc.timestamp_msb); + tmp_desc.address_extension =3D cpu_to_le32(tmp_desc.address_extension); + tmp_desc.next_descriptor =3D cpu_to_le32(tmp_desc.next_descriptor); + tmp_desc.source_address =3D cpu_to_le32(tmp_desc.source_address); + tmp_desc.address_extension_23 =3D cpu_to_le32(tmp_desc.address_extensi= on_23); + tmp_desc.address_extension_45 =3D cpu_to_le32(tmp_desc.address_extensi= on_45); + tmp_desc.source_address2 =3D cpu_to_le32(tmp_desc.source_address2); + tmp_desc.source_address3 =3D cpu_to_le32(tmp_desc.source_address3); + tmp_desc.source_address4 =3D cpu_to_le32(tmp_desc.source_address4); + tmp_desc.source_address5 =3D cpu_to_le32(tmp_desc.source_address5); + tmp_desc.crc =3D cpu_to_le32(tmp_desc.crc); + + return dma_memory_write(&address_space_memory, desc_addr, &tmp_desc, + sizeof(DPDMADescriptor), MEMTXATTRS_UNSPECIFIE= D); +} + size_t xlnx_dpdma_start_operation(XlnxDPDMAState *s, uint8_t channel, bool one_desc) { @@ -651,8 +708,7 @@ size_t xlnx_dpdma_start_operation(XlnxDPDMAState *s, ui= nt8_t channel, desc_addr =3D xlnx_dpdma_descriptor_next_address(s, channel); } =20 - if (dma_memory_read(&address_space_memory, desc_addr, &desc, - sizeof(DPDMADescriptor), MEMTXATTRS_UNSPECIFIE= D)) { + if (xlnx_dpdma_read_descriptor(s, desc_addr, &desc)) { s->registers[DPDMA_EISR] |=3D ((1 << 1) << channel); xlnx_dpdma_update_irq(s); s->operation_finished[channel] =3D true; @@ -755,8 +811,10 @@ size_t xlnx_dpdma_start_operation(XlnxDPDMAState *s, u= int8_t channel, /* The descriptor need to be updated when it's completed. */ DPRINTF("update the descriptor with the done flag set.\n"); xlnx_dpdma_desc_set_done(&desc); - dma_memory_write(&address_space_memory, desc_addr, &desc, - sizeof(DPDMADescriptor), MEMTXATTRS_UNSPECIFI= ED); + if (xlnx_dpdma_write_descriptor(desc_addr, &desc)) { + DPRINTF("Can't write the descriptor.\n"); + break; + } } =20 if (xlnx_dpdma_desc_completion_interrupt(&desc)) { --=20 2.30.2