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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041605; x=1714646405; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=aKgAIExeXe22iXmvncCzPBD6wUC7eTZRMMv1MDBAcwE=; b=ZjT8EGa4SbQ2lcNkoeukDJwUQYz1onssSsS0noMIBneJQtqiDdZ6PonzUCzSk7Nfp3 DWteL+jCaDkVj6z1SyZS6jMeHe/Zu/7qa31WuvrLBChvTARnzsRb9WISxvBOsG6AMmlY KQdd88Yfq7t5UelBOZQSiNohu+Eqy5zcUPavJ1Komm/IY0ZagveA7+gT/CVKiWPldSvb C2BwufixCILM9rwr64AxP6l7LSkqhYpEXVeSi1IvrHVNTQolyYD5s6/gD/n4v+1PdlZG IYQy1e342viqnoqshRkWiv3kEnXkzLMvOSgsGAIIZ6GumwHUgg2cXo4tM6cN/kjftgqF W9Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041605; x=1714646405; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aKgAIExeXe22iXmvncCzPBD6wUC7eTZRMMv1MDBAcwE=; b=XHkgP43VO3WjPgEeA/9Kb6qQKXlBIKt4A4bKUlUXkV57DPrPApPm12jm4zbdV8dB/z gZKWzSe6zEZcHqSo6xJJLbC14d5ej5jR/H1dgFutCofnrSoOxw3Yua43pZH4dz5OUoeD 1niU6uu3cIj0qAxOKhKt5qSJpa/fz+uj9f7byBoer2fX4P7B7vKq761RZFKRlBY4UgOO 7hjoUlPDgq9zIDIrd/NuXe3o/EMV/+uT8mnRF0z2z1qZg2Jx6iB+3XVu61YmVNQENoRr f/TNyjqDYe9b49h7xkpdHJ81EYipKeHUJOiCSDaUp7u5k1wmqKxbhHMxQhcpaoKQDwMR zVmQ== X-Gm-Message-State: AOJu0YzZ5J17d/w7+suwpDCJQiSWSnBKl4wvCPaypqpIEb1ribX0AQ4v evb6bhFJq90BXwBLy493P6eLJ52X13n3/sKgJs2ZdddU0+CRvEgIklTFHylBloWIYSIt5Q6y+mj J X-Google-Smtp-Source: AGHT+IH4ZI0My2ovJWqjUWMox/A0hOF+S40KWYbGcCXyVHkq2Qb1XVK3lopDxZ75yeJQdpnyx49KwA== X-Received: by 2002:a05:6000:1361:b0:349:9e18:9f73 with SMTP id q1-20020a056000136100b003499e189f73mr5218145wrz.67.1714041605094; Thu, 25 Apr 2024 03:40:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/37] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI Date: Thu, 25 Apr 2024 11:39:29 +0100 Message-Id: <20240425103958.3237225-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041995978100004 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-9-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 08a6bc50de2..97997dbd087 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1398,6 +1398,8 @@ void pmu_init(ARMCPU *cpu); #define CPSR_N (1U << 31) #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) +#define ISR_FS (1U << 9) +#define ISR_IS (1U << 10) =20 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ diff --git a/target/arm/helper.c b/target/arm/helper.c index 4ee59b37059..6b6d8a349a2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2021,16 +2021,29 @@ static uint64_t isr_read(CPUARMState *env, const AR= MCPRegInfo *ri) if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { ret |=3D CPSR_I; } + if (cs->interrupt_request & CPU_INTERRUPT_VINMI) { + ret |=3D ISR_IS; + ret |=3D CPSR_I; + } } else { if (cs->interrupt_request & CPU_INTERRUPT_HARD) { ret |=3D CPSR_I; } + + if (cs->interrupt_request & CPU_INTERRUPT_NMI) { + ret |=3D ISR_IS; + ret |=3D CPSR_I; + } } =20 if (hcr_el2 & HCR_FMO) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { ret |=3D CPSR_F; } + if (cs->interrupt_request & CPU_INTERRUPT_VFNMI) { + ret |=3D ISR_FS; + ret |=3D CPSR_F; + } } else { if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { ret |=3D CPSR_F; --=20 2.34.1