From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041774; cv=none; d=zohomail.com; s=zohoarc; b=Z1lgIBzCbYe42a3dyuezu7hp13L/K13jw33GpdYcIDZAlPLE4HZVMUvghWGCP8ehE5+O7biNy6a283V2JENCsQWqWN6Mos+veFIP4L/S7agarALae3rc0Ir76Rs1nFuRtqfDyqL9JE0v1+++60FqoW8WrDECBHISs5YVTopBVj8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041774; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=D6sUqMTkg3AZ/EzB3wSEo9MXBvR+VUgJR/HaUz5GIjY=; b=dq7zBqHqprLzofMMw028MOuJxvTf0f7X3XGWYStOZ+EMgaT9PC4LvqZCClwGGIpTQufW1Mh6v6N8gLK0/r3mNuKFXLJZx/qresXE3L9Nw75saXA/1rNptY7bwPjfm2uSzLZEdAJQPEPxKGqtoYfkxGcLS0yDLfoGnNvdmfm/0gE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041774515417.5687292034511; Thu, 25 Apr 2024 03:42:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWO-0001z9-To; Thu, 25 Apr 2024 06:40:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWK-0001wl-IW for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:04 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWI-0006xK-BY for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:04 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-34782453ffdso757299f8f.1 for ; Thu, 25 Apr 2024 03:40:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041600; x=1714646400; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=D6sUqMTkg3AZ/EzB3wSEo9MXBvR+VUgJR/HaUz5GIjY=; b=EW3Vt0S/Fi0dAqid9SXUDrJnwyZgZ9OZLEmiD8P9X/mfgkl2Tv9LUTJqpVwFPX9z39 5ytdfRR0x6Wi5aT2VXUrwFCYf8bKW6gAOPKrlXqmw6p0ft2QQMzyHeSrVKRVUyWduV86 QnfKRncs66yGu+QldaA7x9riIOzH4OTpd7sA7yXnF9DAXnRjql6TFQBuLA1HDYnWUB7q Fw0/6rBTuawejhQM+HztYT/kt4Vw4K39zgysP+4Sq8XMh0qIB1K2J/Mx7Jvk2H12UG9B wqAZY/W2cZRcJQ9UD8UBd524OVgMHJ9/yaSFjFfGcLgcDTZlMmCKAiXQIhjrk1Q3qkLk 1+0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041600; x=1714646400; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D6sUqMTkg3AZ/EzB3wSEo9MXBvR+VUgJR/HaUz5GIjY=; b=nAnzBscGa+wgDadqZV6GQpuox43+GP7/e38Hmt5xA8euLvA5jnhVuHhLLGTQDqI7OT jqwCW9Y9pPnGsMZVuaPpQQkSIKRbMBnH/GbipxIXmroucCVoecbJ+mJjXiuNTMUPw15p dRgikdvJX95o7Mzpcvxnk7SdEkdWDhfFuN4Pf6y0zEH542nkpmoJTCG9+Dupzyz0mtBC idG8K/WzXLSiFIU5hC83EGXWxDACH+6+02VyRKPpQpB71L4xnCckv1HSEDE4CSNf6AAA jY2JteMCWM5c2MbmsOF3nICfPkiruvN716/wkMIAeNc8Zl4RSSGde0njK6QYPgdEU3jj tUTQ== X-Gm-Message-State: AOJu0YxC62g1ziaUdqgOCWXHu3WnaXwqL2wDxVNF1BeumDWcZs3OJWZT Qh4n14o/psDNWMI9KlNYogJbYqoQqPS7z8kHTQcqHxXcPHmYv6ltFR3C2j/f9qX/NMlD8IWG/52 b X-Google-Smtp-Source: AGHT+IHs92x3xf+ZTwwh0pG9Iug+PY7yk3F6/MmszFduc/R3keQYh/GpRWG3fVGG6Tjg/arGMzDjNg== X-Received: by 2002:adf:f1c4:0:b0:34a:5663:40b with SMTP id z4-20020adff1c4000000b0034a5663040bmr4464045wro.3.1714041600512; Thu, 25 Apr 2024 03:40:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/37] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI Date: Thu, 25 Apr 2024 11:39:22 +0100 Message-Id: <20240425103958.3237225-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041775439100005 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and HCRX_VFNMI. When the feature is enabled, allow these bits to be written in HCRX_EL2. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-2-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 5 +++++ target/arm/helper.c | 8 +++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e5758d9fbc8..b300d0446d8 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -681,6 +681,11 @@ static inline bool isar_feature_aa64_sme(const ARMISAR= egisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) !=3D 0; } =20 +static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, NMI) !=3D 0; +} + static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 1; diff --git a/target/arm/helper.c b/target/arm/helper.c index a620481d7cf..7a25ea65c9a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6187,13 +6187,19 @@ bool el_is_in_host(CPUARMState *env, int el) static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu =3D env_archcpu(env); uint64_t valid_mask =3D 0; =20 /* FEAT_MOPS adds MSCEn and MCE2 */ - if (cpu_isar_feature(aa64_mops, env_archcpu(env))) { + if (cpu_isar_feature(aa64_mops, cpu)) { valid_mask |=3D HCRX_MSCEN | HCRX_MCE2; } =20 + /* FEAT_NMI adds TALLINT, VINMI and VFNMI */ + if (cpu_isar_feature(aa64_nmi, cpu)) { + valid_mask |=3D HCRX_TALLINT | HCRX_VINMI | HCRX_VFNMI; + } + /* Clear RES0 bits. */ env->cp15.hcrx_el2 =3D value & valid_mask; } --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041997; cv=none; d=zohomail.com; s=zohoarc; b=EAvL+bbVG1QIfLDBAKRZpB1nY7cwybG2vkvACUZiz3Zz2QGKWbfsUUgGZhb88ZgrPES7peQni0SgW+u9gmjloMF3oul4lC3q+64GaNiNgB8rPEufLbTU8DIV5Oo0Ji0UcmM7PTZsTBqzHizpUGtksU3tRlxEw7dIf1DKrvtuwy4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041997; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=y6I7eopQEiXePMFfuuglLJED0IgYNow8XyLPv9LxTAY=; b=jvpcHTNCHgbCj6mViB2q82h6qhIOUa28DNidU2QU8kMuCdhg2njZ1GuCnFzLoQmwKHjxkNrL5Bit5TnRg65mIJRy1N2cJnnNrwoLoACDjPgyrJQvAgkrfIIUz3piJhqCQdF+wAcCBbnLCT8yv1+sFjXi6j9k0ai4b89SEnZJbvw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041997232541.6113649470827; Thu, 25 Apr 2024 03:46:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWN-0001xn-3y; Thu, 25 Apr 2024 06:40:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWL-0001x3-Mm for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:05 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWI-0006xm-To for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:05 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-34be34b3296so784167f8f.1 for ; Thu, 25 Apr 2024 03:40:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041601; x=1714646401; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=y6I7eopQEiXePMFfuuglLJED0IgYNow8XyLPv9LxTAY=; b=R98+e1E23BMmnj6FZ+bXoWlaPh+mxHpL1Qb+4PSBxsPfJ1fAgXgEMDflEm1IFSlvYb A8MQeC1imZkBG1uvpqVtTZW3fN2dM6j6HADlqdRjsBuM7RudH42TxpEzB8JrYzG7IDXh L+5Q0Lj24nx3aT3MqgtLrUkodz92XiYIO+dKgAYufc9ohtVC95AJF4f+Hve+bJ6d9A1L vZVMwON7uutgjQjZi6qfTCRedVN8fB8HQBGDb3qWX2NZxLd2WwJPTpdVvhoTjgJOLYnO MtuOUDJHU8myzaJV1vA4nnuNcKJem4FYGg4v1mbiBHWeKC3R+GhSO0NR/4JcplLOV5D+ B3zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041601; x=1714646401; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y6I7eopQEiXePMFfuuglLJED0IgYNow8XyLPv9LxTAY=; b=cjFMXzjuipjcyTxVvTA+9nEVLj6S0t3bLWGnGVBIZWdeze/p9it5kF9Cog8mYDgdu7 OT1ysQ9kEeVowO9p00GHTiVqIL6zv0meu0lD08ljifXVgydAFExoW7GrJ8QnPFesHTg5 qhs8sDgNYxSmS649AxrzA3vRkipWurXM4Iftafzels20mydU7gyo1+d73Gh/LMcI1nZ0 SqSXEo66yLBqYNhvpPf+xuijm8jCTDzuOzlsgSgSKJL5BhPFR0icgKLQX48rLrRTrm41 rxk26WsFiEJuLVtpZI7ouHEahuPwLrr8/WwCs3IrNd+VWuqUQUI6D4sKUoWjGcvROz2i yKNw== X-Gm-Message-State: AOJu0Yy935zI+bzsFCg3QUT5GOq+UZ9T9r4AoG6KE2b7OWcmswn3rr6w 7MkEfh5WBLp/xlHqUI0BDS4jsSHqoOXX7iZGSFKGeR535LS53cCq/BTYVhA4zD5FpaqXONTxhXG 5 X-Google-Smtp-Source: AGHT+IFy3IqbE1xDbneFglPX26pi/zREeqlNb9QykjMaNu5wtYIjTq8Rnf51Ta2idsWnHgh6JSFhcg== X-Received: by 2002:a05:6000:1042:b0:343:a183:4218 with SMTP id c2-20020a056000104200b00343a1834218mr4625611wrx.52.1714041601143; Thu, 25 Apr 2024 03:40:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/37] target/arm: Add PSTATE.ALLINT Date: Thu, 25 Apr 2024 11:39:23 +0100 Message-Id: <20240425103958.3237225-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041998026100024 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to ELx, with or without superpriority is masked. As Richard suggested, place ALLINT bit in PSTATE in env->pstate. In the pseudocode, AArch64.ExceptionReturn() calls SetPSTATEFromPSR(), which treats PSTATE.ALLINT as one of the bits which are reinstated from SPSR to PSTATE regardless of whether this is an illegal exception return or not. So handle PSTATE.ALLINT the same way as PSTATE.DAIF in the illegal_return exit path of the exception_return helper. With the change, exception entry and return are automatically handled. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-3-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/tcg/helper-a64.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bc0c84873ff..de740d223fa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1430,6 +1430,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_D (1U << 9) #define PSTATE_BTYPE (3U << 10) #define PSTATE_SSBS (1U << 12) +#define PSTATE_ALLINT (1U << 13) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index ebaa7f00df3..29f3ef274ae 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -892,8 +892,8 @@ illegal_return: */ env->pstate |=3D PSTATE_IL; env->pc =3D new_pc; - spsr &=3D PSTATE_NZCV | PSTATE_DAIF; - spsr |=3D pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); + spsr &=3D PSTATE_NZCV | PSTATE_DAIF | PSTATE_ALLINT; + spsr |=3D pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF | PSTATE_ALLI= NT); pstate_write(env, spsr); if (!arm_singlestep_active(env)) { env->pstate &=3D ~PSTATE_SS; --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714042108; cv=none; d=zohomail.com; s=zohoarc; b=BZA/QUV5CSVOiACdMwhGCVUIHIVvaS97jDo77COHElv9TseHlpyXbbX/bU9B0I7RKJTyhdQ8VSmHkEHjkHgD8clPSy2JdTxY23uzxteXXHo81MXJl4gYSltx1Zcghgp4QO8+mz3d2gIDhA7l/2DoVZ7En1gbZjKDFdXVMEeIMzY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714042108; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=UIo/4Y0jCkZhZbVf1z/K9VYt8JNRKmGPNz3rHCYkyTk=; b=DFe63zkCNG2B458NiFpGNgqX4cukNB2R3Ngs1mCx1PFjzFZ7FojUS02R/w5Y81jQNhx7zmSLbFmHoFhIScFGJMBS128Y3RblIBcf4tM9mi5j1LHTkg07s6rNak8K+v6fdhcTaMRT0dDtYgdNVqLbHrqNKg1Gi/48ehnqj5Vx80k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714042108251661.9727877698855; Thu, 25 Apr 2024 03:48:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWN-0001xo-6Z; Thu, 25 Apr 2024 06:40:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWM-0001x9-0q for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:06 -0400 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWK-00070Q-46 for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:05 -0400 Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-5194cebd6caso901880e87.0 for ; Thu, 25 Apr 2024 03:40:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041602; x=1714646402; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UIo/4Y0jCkZhZbVf1z/K9VYt8JNRKmGPNz3rHCYkyTk=; b=kmTUlo5n+PIezLqs8wHwqp1IlssJuLBtzASP4yPrLIDef8U3c6B2HG2l87/eVRfJJf Ns1efYXazFPpvydnIHlLG9LmeR7FyXH8T7Crg6gMqcUeguT1AWL7vdVO2IesoiheH/X4 LuFUh/jzEMURxkL4cBl/ecbS8xeJTCX8aWbAbToAH1akgLaAfWVI8UGF6gSHP701ToSj J6GP4xK7zSXEEQn52kO59K/Dz/l3MtU/5GcEgHB5DCSJa422JEj5VnANNEuD3gnSCHDi mvTqTQwIAymAGu/roljDqVHGEW4UWx2FmzoQWsH49HysbmAup0UPgzCJBF42y4zFBh6A /GJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041602; x=1714646402; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UIo/4Y0jCkZhZbVf1z/K9VYt8JNRKmGPNz3rHCYkyTk=; b=Y0A731qTbU0hhC3yuzEZ2Kz77WX3PxL3Hs0ufhnnR0U59TfTEkYTyPtISikYk8ioCs qlYjxvto7DK6gCll8oyV6DIgB7JhArs/rpEmIU/TO2Ro1RNQwZOlIcmZmB9rEpJc0VFA VUjV5u0038ky/OuTAU2AY6XtBpZpWxGJ95Qtfg7z9hm1rsaeQrcB8PK2IHAzRDIVe4fg 9ZngXROAPN7qB275YNa3QTS3LYUcGdeX8FEdOfM/uzi+ppezyugWmH3yEr+Uk58FoU5s tuCDkpoVi+2fUR0kGTYex70ywJUXVzIO5JLIXxAzFBMzQjGnL9BP2mZtywWzvC1wWcmk ILEg== X-Gm-Message-State: AOJu0YxGruwP8cL3vVodNEN0YBXpxspbCLXyHI7BwZcyQTP10tFmIiP2 xL/pcZcDhEQtVXnavbcRVPNCyebdeLEYnRv8SuFbhiM2sE/49WM+0VkMDKnVCc5wgTQcfAABMl8 x X-Google-Smtp-Source: AGHT+IGIUXUfL8ed/1eQi8VCDsq26Ev2gMqoSW7iJUd273qsKnkkXDALYoppPKazDECXEm1E2urHKQ== X-Received: by 2002:ac2:4984:0:b0:51c:3e9e:98ee with SMTP id f4-20020ac24984000000b0051c3e9e98eemr1261876lfl.23.1714041602293; Thu, 25 Apr 2024 03:40:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/37] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt Date: Thu, 25 Apr 2024 11:39:24 +0100 Message-Id: <20240425103958.3237225-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714042110323100003 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in ARMv8.8-A and ARM v9.3-A. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-4-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- target/arm/internals.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index dd3da211a3f..516e0584bf5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1229,6 +1229,9 @@ static inline uint32_t aarch64_pstate_valid_mask(cons= t ARMISARegisters *id) if (isar_feature_aa64_mte(id)) { valid |=3D PSTATE_TCO; } + if (isar_feature_aa64_nmi(id)) { + valid |=3D PSTATE_ALLINT; + } =20 return valid; } --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714042138; cv=none; d=zohomail.com; s=zohoarc; b=YNHFpj2at+jw4w4LSQ87P71Icuf/mJGoSXPnMHqH5erqDC2BafLN/lNQIXoKX+8KJX7Uj4AwPx+aUzAN/adzVzcD8nAV1IwGWZp+ZyiDxR7fY8EGjmyRPeFI0fWB3eShE626mR4q3etVBs10I555H4korGPzKaXsGKolyi0dRG0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714042138; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=957rAqnR2jdbtNnjgxfqiz7CRvR1nL/QXsIUUvuurzY=; b=fvnWEw6UZQdkmIOm09SQmFVvOfkK/HRZlPyJ175uqJgIxNgWhxMdmsM5oo7DVtktUX8tWfdKXNhkCjRXKSzS+aq+8fK51CHhCR/w/TQMkilAFxLdz+X/AOxLFgjt556RsNW0ms/TiCn/DFZfMfkbg62HEHulEoGiG+qblwMwoG4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714042138591165.31332711483208; Thu, 25 Apr 2024 03:48:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWN-0001xv-BM; Thu, 25 Apr 2024 06:40:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWM-0001xS-FT for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:06 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWK-000751-Oz for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:06 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-343d2b20c4bso605454f8f.2 for ; Thu, 25 Apr 2024 03:40:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041603; x=1714646403; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=957rAqnR2jdbtNnjgxfqiz7CRvR1nL/QXsIUUvuurzY=; b=i4et7G0tr6OLfDSOHucAWHm/rDT+IhiKqY+c9xiwX10PL0tMvtAmNnNxYOvN11Ke9+ UsScK4r3TZDfpkx06CxzLJT1BPuTaCa57WDKvLg0HGiWxaIx20VIohTrfPUU3rViarcW uGL+hv1JF2AabOdg+YCKjvqfTLRdCfskcdkz5IP1fqE5XvgjFr6qh6IMpR8WWch7clPR MP3+X89EQTmwWg5meS/RuGTBgJZ6r5zwDqJVQDEa7YhFw2NhPdHNjdoeYyGR8Qx9fUWd 7sqcaF9Y0gEn3QYEk8XGShnBKmYNlIw7W9vi0kpUn671sZr/gC9PZHJVZ8ySxKVO0FCJ lX8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041603; x=1714646403; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=957rAqnR2jdbtNnjgxfqiz7CRvR1nL/QXsIUUvuurzY=; b=H7sBMriT+71a28l2Lx2lQd1oaGa9MhlmVea9T9NZdLRqvEQI8GRxwv1/owqecnkQs+ f0PCXe9hf8vuiAUbwQFlKvDtcRG3eSL/o7fEnNU3aYU6Pmj4SRbLMhk0vmXs3NRJScQS B1TK9W6JYDO5qa+qX9z6y6VsLwY50fGoodEPKcB2a47vj4X8wmmu/OQkDLVbyiIyQ4ru ZEWezfTte0rsFQMzT+M5TIqDvFzlrmdrfTqQ20HP7SqJZ+EymEX/WaKHDxclUXtccyeM LBC1Ha9TYE14rflbH2ZgfaMnNKxkKR3iO7v+Dad0r5QpljS76N4shRqOse4kKqVgZ+Uv qnpQ== X-Gm-Message-State: AOJu0YykC4Hw28B/IGdOD3XwYR2J92NS0h582lm+WoKDeZKR05BIZxva Ily1dfOomYy17nh/rMJyvsPWo5Kbtog4hfrWCH7PGq2i3oCc5JOb22E/5ItLtcNbfVnQAtZa1cd a X-Google-Smtp-Source: AGHT+IF57MvCH0I+WRvuZIvG4vQo1H2m8Na0/u8rmqxDPUb6n9oeSOS3vISd3nPf/cr1z5K3H2yEdQ== X-Received: by 2002:adf:8b5d:0:b0:34b:2a61:b3c9 with SMTP id v29-20020adf8b5d000000b0034b2a61b3c9mr4093361wra.40.1714041602822; Thu, 25 Apr 2024 03:40:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/37] target/arm: Implement ALLINT MSR (immediate) Date: Thu, 25 Apr 2024 11:39:25 +0100 Message-Id: <20240425103958.3237225-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714042140400100007 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The EL0 check is necessary to ALLINT, and the EL1 check is necessary when imm =3D=3D 1. So implement it inline for EL2/3, or EL1 with imm=3D=3D0. Avo= id the unconditional write to pc and use raise_exception_ra to unwind. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-5-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- target/arm/tcg/helper-a64.h | 1 + target/arm/tcg/a64.decode | 1 + target/arm/tcg/helper-a64.c | 12 ++++++++++++ target/arm/tcg/translate-a64.c | 19 +++++++++++++++++++ 4 files changed, 33 insertions(+) diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h index 575a5dab7dc..05181653999 100644 --- a/target/arm/tcg/helper-a64.h +++ b/target/arm/tcg/helper-a64.h @@ -22,6 +22,7 @@ DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_2(msr_i_spsel, void, env, i32) DEF_HELPER_2(msr_i_daifset, void, env, i32) DEF_HELPER_2(msr_i_daifclear, void, env, i32) +DEF_HELPER_1(msr_set_allint_el1, void, env) DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 8a20dce3c8f..0e7656fd158 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -207,6 +207,7 @@ MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 1111= 1 @msr_i MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i +MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111 MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 =20 # MRS, MSR (register), SYS, SYSL. These are all essentially the diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 29f3ef274ae..0ea8668ab4c 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -66,6 +66,18 @@ void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm) update_spsel(env, imm); } =20 +void HELPER(msr_set_allint_el1)(CPUARMState *env) +{ + /* ALLINT update to PSTATE. */ + if (arm_hcrx_el2_eff(env) & HCRX_TALLINT) { + raise_exception_ra(env, EXCP_UDEF, + syn_aa64_sysregtrap(0, 1, 0, 4, 1, 0x1f, 0), 2, + GETPC()); + } + + env->pstate |=3D PSTATE_ALLINT; +} + static void daif_check(CPUARMState *env, uint32_t op, uint32_t imm, uintptr_t ra) { diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2666d527111..976094a5c80 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2036,6 +2036,25 @@ static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, a= rg_i *a) return true; } =20 +static bool trans_MSR_i_ALLINT(DisasContext *s, arg_i *a) +{ + if (!dc_isar_feature(aa64_nmi, s) || s->current_el =3D=3D 0) { + return false; + } + + if (a->imm =3D=3D 0) { + clear_pstate_bits(PSTATE_ALLINT); + } else if (s->current_el > 1) { + set_pstate_bits(PSTATE_ALLINT); + } else { + gen_helper_msr_set_allint_el1(tcg_env); + } + + /* Exit the cpu loop to re-evaluate pending IRQs. */ + s->base.is_jmp =3D DISAS_UPDATE_EXIT; + return true; +} + static bool trans_MSR_i_SVCR(DisasContext *s, arg_MSR_i_SVCR *a) { if (!dc_isar_feature(aa64_sme, s) || a->mask =3D=3D 0) { --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041655; cv=none; d=zohomail.com; s=zohoarc; b=K9uBHN68LY9nvd8G+U+zJPqb2GR02eumtSu8Xm/uPEpknZnPf3j3pLGDuMx2yVbohVwM8jnM/41Y4FZiHP32ls38ntSqoJAy02cmqb+xAiZ8cs4tltlC4Q/DJcW0Rm704wXIunZipFJJvsvE27pvMVa5d3H2FMIaDx7mXczk1tM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041655; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=4h8d6UwgIGiFHRbvrM5SoXNPNiyUuHID0a2JGu04tl8=; b=ikZdK8Fj32Jgy8QhyTfBPqsU+3WpNDhCN+VBES7nj8rbXXzca4XCe1XYdV4SvpUOeZC7xzGL/9S+ij/nT4cQKm1HY4XLuzcHSSxuGNFaTYRl+x9/P3ly9utxvXqEM+fOql4PWdtKIFm5MNg9HBjST3p/9oxmCgmc1myCMV7cT8c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041655124682.9031295774026; Thu, 25 Apr 2024 03:40:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWP-0001zK-8j; Thu, 25 Apr 2024 06:40:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWN-0001xm-1q for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:07 -0400 Received: from mail-lf1-x135.google.com ([2a00:1450:4864:20::135]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWL-00079Z-BQ for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:06 -0400 Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-51b09c3a111so1153259e87.1 for ; Thu, 25 Apr 2024 03:40:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041603; x=1714646403; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4h8d6UwgIGiFHRbvrM5SoXNPNiyUuHID0a2JGu04tl8=; b=bj/szA5oyR7tLutdUtFaONVA/nF7IIAw0DRks2cvxEECuL7yymK1xp71pGxilQjaeH Vfi6K+5xdXXz9wMoIi7o+vyyzn6OWgU4JbJ2IKQI6P6MPHKZGvVnG2CaP3X+569dhDHc S7hUgb1LPdnRP+/UUEvf7iKTnhG6KNQySURu/E8L7jZu30XtWKm2KezgspMyez8q1xd7 r255IpmMSIGmlCqh7H9qQ5VLeFTwfT9YNiu481E40HER3V4wKKfao768uMqAcXcxg+l2 1cx/qgV8UJJ30k/TdL3aqNDgB+e6hYStcsRWIMNPwi4gdaRmdxjQfgZVPIj2kmJCrK6f hZNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041603; x=1714646403; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041657070100003 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan Support ALLINT msr access as follow: mrs , ALLINT // read allint msr ALLINT, // write allint with imm Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-6-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7a25ea65c9a..b9443b1813a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7500,6 +7500,37 @@ static const ARMCPRegInfo rme_mte_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NOP }, }; + +static void aa64_allint_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_ALLINT) | (value & PSTATE_ALLIN= T); +} + +static uint64_t aa64_allint_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_ALLINT; +} + +static CPAccessResult aa64_allint_access(CPUARMState *env, + const ARMCPRegInfo *ri, bool isre= ad) +{ + if (!isread && arm_current_el(env) =3D=3D 1 && + (arm_hcrx_el2_eff(env) & HCRX_TALLINT)) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo nmi_reginfo[] =3D { + { .name =3D "ALLINT", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 0, .crn =3D 4, .crm =3D 3, + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, .accessfn =3D aa64_allint_access, + .fieldoffset =3D offsetof(CPUARMState, pstate), + .writefn =3D aa64_allint_write, .readfn =3D aa64_allint_read, + .resetfn =3D arm_cp_reset_ignore }, +}; #endif /* TARGET_AARCH64 */ =20 static void define_pmu_regs(ARMCPU *cpu) @@ -9894,6 +9925,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_nv2, cpu)) { define_arm_cp_regs(cpu, nv2_reginfo); } + + if (cpu_isar_feature(aa64_nmi, cpu)) { + define_arm_cp_regs(cpu, nmi_reginfo); + } #endif =20 if (cpu_isar_feature(any_predinv, cpu)) { --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041673; cv=none; d=zohomail.com; s=zohoarc; b=fjTL4Nx/UOfQpcXTH4pWZuHFLmua/wq7v4fYIbtVBV2zxh5AYGBocwQwrqKulTM4lawZYXQpyJEw0eVkNbYyLw2MqaVv5PH4toO/gvY8yuk1K3soHFvbL2VqhjasWsdDojhjxDTQeucWLI2vAV5o5O8TEbX5cn38enFSMTW7xAI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041673; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041604; x=1714646404; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+/rRCyBjJYpKJB9PngM6SBcXpQkobdS6pXKimrxoEgk=; b=H9VbUmafxYPwitIICHFo5rPAdBugFdUpeJmJiQF0yajGZAL+tBilmRZw1b/3vyOW79 MIkWpD8KJaX2XBYVqg1g3BMYODichKZj36/2FJl1+FCMkQyrtsgXdRlzwIOfMZRT4LXb zTjTORNbKDgki+kX5jcIl5hU23rPnrnjFh6x+/vIGsyDTLNT5eGiZM26yGC7zxaVL/wP n++vtW+eyNCe0kfwzsOpsfGeNEKAFXw5D6buatTSeSpl8YwRTb0G0xaW8EBSlEjZdGl9 BNRVsiNxYgCSQkJ6etelMtcsOjwsrVf63YXlQphQM9NCXxA3XvulePwLgsrBsyrgaIVZ 0+MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041604; x=1714646404; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+/rRCyBjJYpKJB9PngM6SBcXpQkobdS6pXKimrxoEgk=; b=g5RLNvNg9hW3WWcw+i/UMIRi2aORt4GbLfKyDfI7wMcevCRUFrogUbCOue8hcdWxDG dsVdW58F9326MdNjQd83oZegeWf40HLTYFRG6VGyfJpGo1YQUZU2NxcyRKrv7T66T1SA Te7rG/KDOlbsQ4OYCxsSUjnBwT7uk2YOkXrm0VAU3JYpe12lgTyDgjNLwW2URvB/Mcn2 fZ5J9NM6AkN2uqorhGXojYE4bSeAZfob6p3opeENT6E3O9Sdun9BHHoeDb2dAqiqq5XH ipczyS0DkaWcbBCNyZqQqFjGatJxslJkYEntgsId7aEb9qluqquG7k1ROTH8GxLQ7ti6 vBsA== X-Gm-Message-State: AOJu0YxVKWIey1tKbB6sc7mZuw+xVT1M3khSQXQKJqQWszZQBdIjoVdI s3lSWkMl20gUgrLxE6LqWHfuo+jmjBsbu6zwL1/fSXrtiuN9NqKMb+vQCK2GHcqy+krxTr2pYRt u X-Google-Smtp-Source: AGHT+IFkRygel/7Wz+gcdBbSZcgt+CnjIqsqWsjmF0XOamCqt94VGpBsgGq3EaLJudaA/8U0lrfLfw== X-Received: by 2002:ac2:410a:0:b0:51b:7c36:da61 with SMTP id b10-20020ac2410a000000b0051b7c36da61mr3233607lfi.56.1714041603764; Thu, 25 Apr 2024 03:40:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/37] target/arm: Add support for Non-maskable Interrupt Date: Thu, 25 Apr 2024 11:39:27 +0100 Message-Id: <20240425103958.3237225-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041675117100003 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan This only implements the external delivery method via the GICv3. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-7-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- target/arm/cpu-qom.h | 5 +- target/arm/cpu.h | 6 ++ target/arm/internals.h | 18 +++++ target/arm/cpu.c | 147 ++++++++++++++++++++++++++++++++++++++--- target/arm/helper.c | 33 +++++++-- 5 files changed, 193 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 8e032691dbf..b497667d61e 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -36,11 +36,14 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) =20 -/* Meanings of the ARMCPU object's four inbound GPIO lines */ +/* Meanings of the ARMCPU object's seven inbound GPIO lines */ #define ARM_CPU_IRQ 0 #define ARM_CPU_FIQ 1 #define ARM_CPU_VIRQ 2 #define ARM_CPU_VFIQ 3 +#define ARM_CPU_NMI 4 +#define ARM_CPU_VINMI 5 +#define ARM_CPU_VFNMI 6 =20 /* For M profile, some registers are banked secure vs non-secure; * these are represented as a 2-element array where the first element diff --git a/target/arm/cpu.h b/target/arm/cpu.h index de740d223fa..08a6bc50de2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -61,6 +61,9 @@ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ #define EXCP_VSERR 24 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ +#define EXCP_NMI 26 +#define EXCP_VINMI 27 +#define EXCP_VFNMI 28 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 @@ -80,6 +83,9 @@ #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 +#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 +#define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0 +#define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1 =20 /* The usual mapping for an AArch64 system register to its AArch32 * counterpart is for the 32 bit world to have access to the lower diff --git a/target/arm/internals.h b/target/arm/internals.h index 516e0584bf5..b53f5e8ff2a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1109,6 +1109,24 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); =20 +/** + * arm_cpu_update_vinmi: Update CPU_INTERRUPT_VINMI bit in cs->interrupt_r= equest + * + * Update the CPU_INTERRUPT_VINMI bit in cs->interrupt_request, following + * a change to either the input VNMI line from the GIC or the HCRX_EL2.VIN= MI. + * Must be called with the BQL held. + */ +void arm_cpu_update_vinmi(ARMCPU *cpu); + +/** + * arm_cpu_update_vfnmi: Update CPU_INTERRUPT_VFNMI bit in cs->interrupt_r= equest + * + * Update the CPU_INTERRUPT_VFNMI bit in cs->interrupt_request, following + * a change to the HCRX_EL2.VFNMI. + * Must be called with the BQL held. + */ +void arm_cpu_update_vfnmi(ARMCPU *cpu); + /** * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit * diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ab8d007a86c..d2dfd36fd45 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -122,6 +122,13 @@ void arm_restore_state_to_opc(CPUState *cs, } #endif /* CONFIG_TCG */ =20 +/* + * With SCTLR_ELx.NMI =3D=3D 0, IRQ with Superpriority is masked identical= ly with + * IRQ without Superpriority. Moreover, if the GIC is configured so that + * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see + * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here + * unconditionally. + */ static bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -129,6 +136,7 @@ static bool arm_cpu_has_work(CPUState *cs) return (cpu->power_state !=3D PSCI_OFF) && cs->interrupt_request & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD + | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | CPU_INTERRUPT_EXITTB); } @@ -668,6 +676,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, CPUARMState *env =3D cpu_env(cs); bool pstate_unmasked; bool unmasked =3D false; + bool allIntMask =3D false; =20 /* * Don't take exceptions if they target a lower EL. @@ -678,13 +687,36 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, return false; } =20 + if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && + env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el =3D=3D target_= el) { + allIntMask =3D env->pstate & PSTATE_ALLINT || + ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) && + (env->pstate & PSTATE_SP)); + } + switch (excp_idx) { + case EXCP_NMI: + pstate_unmasked =3D !allIntMask; + break; + + case EXCP_VINMI: + if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { + /* VINMIs are only taken when hypervized. */ + return false; + } + return !allIntMask; + case EXCP_VFNMI: + if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { + /* VFNMIs are only taken when hypervized. */ + return false; + } + return !allIntMask; case EXCP_FIQ: - pstate_unmasked =3D !(env->daif & PSTATE_F); + pstate_unmasked =3D (!(env->daif & PSTATE_F)) && (!allIntMask); break; =20 case EXCP_IRQ: - pstate_unmasked =3D !(env->daif & PSTATE_I); + pstate_unmasked =3D (!(env->daif & PSTATE_I)) && (!allIntMask); break; =20 case EXCP_VFIQ: @@ -692,13 +724,13 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, /* VFIQs are only taken when hypervized. */ return false; } - return !(env->daif & PSTATE_F); + return !(env->daif & PSTATE_F) && (!allIntMask); case EXCP_VIRQ: if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { /* VIRQs are only taken when hypervized. */ return false; } - return !(env->daif & PSTATE_I); + return !(env->daif & PSTATE_I) && (!allIntMask); case EXCP_VSERR: if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { /* VIRQs are only taken when hypervized. */ @@ -804,6 +836,48 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int i= nterrupt_request) =20 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ =20 + if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && + (arm_sctlr(env, cur_el) & SCTLR_NMI)) { + if (interrupt_request & CPU_INTERRUPT_NMI) { + excp_idx =3D EXCP_NMI; + target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, se= cure); + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + if (interrupt_request & CPU_INTERRUPT_VINMI) { + excp_idx =3D EXCP_VINMI; + target_el =3D 1; + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + if (interrupt_request & CPU_INTERRUPT_VFNMI) { + excp_idx =3D EXCP_VFNMI; + target_el =3D 1; + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + } else { + /* + * NMI disabled: interrupts with superpriority are handled + * as if they didn't have it + */ + if (interrupt_request & CPU_INTERRUPT_NMI) { + interrupt_request |=3D CPU_INTERRUPT_HARD; + } + if (interrupt_request & CPU_INTERRUPT_VINMI) { + interrupt_request |=3D CPU_INTERRUPT_VIRQ; + } + if (interrupt_request & CPU_INTERRUPT_VFNMI) { + interrupt_request |=3D CPU_INTERRUPT_VFIQ; + } + } + if (interrupt_request & CPU_INTERRUPT_FIQ) { excp_idx =3D EXCP_FIQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); @@ -867,7 +941,8 @@ void arm_cpu_update_virq(ARMCPU *cpu) CPUARMState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); =20 - bool new_state =3D (env->cp15.hcr_el2 & HCR_VI) || + bool new_state =3D ((arm_hcr_el2_eff(env) & HCR_VI) && + !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) || (env->irq_line_state & CPU_INTERRUPT_VIRQ); =20 if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) !=3D = 0)) { @@ -888,7 +963,8 @@ void arm_cpu_update_vfiq(ARMCPU *cpu) CPUARMState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); =20 - bool new_state =3D (env->cp15.hcr_el2 & HCR_VF) || + bool new_state =3D ((arm_hcr_el2_eff(env) & HCR_VF) && + !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) || (env->irq_line_state & CPU_INTERRUPT_VFIQ); =20 if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) !=3D = 0)) { @@ -900,6 +976,48 @@ void arm_cpu_update_vfiq(ARMCPU *cpu) } } =20 +void arm_cpu_update_vinmi(ARMCPU *cpu) +{ + /* + * Update the interrupt level for VINMI, which is the logical OR of + * the HCRX_EL2.VINMI bit and the input line level from the GIC. + */ + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + + bool new_state =3D ((arm_hcr_el2_eff(env) & HCR_VI) && + (arm_hcrx_el2_eff(env) & HCRX_VINMI)) || + (env->irq_line_state & CPU_INTERRUPT_VINMI); + + if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VINMI) !=3D= 0)) { + if (new_state) { + cpu_interrupt(cs, CPU_INTERRUPT_VINMI); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI); + } + } +} + +void arm_cpu_update_vfnmi(ARMCPU *cpu) +{ + /* + * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI b= it. + */ + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + + bool new_state =3D (arm_hcr_el2_eff(env) & HCR_VF) && + (arm_hcrx_el2_eff(env) & HCRX_VFNMI); + + if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) !=3D= 0)) { + if (new_state) { + cpu_interrupt(cs, CPU_INTERRUPT_VFNMI); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI); + } + } +} + void arm_cpu_update_vserr(ARMCPU *cpu) { /* @@ -929,7 +1047,9 @@ static void arm_cpu_set_irq(void *opaque, int irq, int= level) [ARM_CPU_IRQ] =3D CPU_INTERRUPT_HARD, [ARM_CPU_FIQ] =3D CPU_INTERRUPT_FIQ, [ARM_CPU_VIRQ] =3D CPU_INTERRUPT_VIRQ, - [ARM_CPU_VFIQ] =3D CPU_INTERRUPT_VFIQ + [ARM_CPU_VFIQ] =3D CPU_INTERRUPT_VFIQ, + [ARM_CPU_NMI] =3D CPU_INTERRUPT_NMI, + [ARM_CPU_VINMI] =3D CPU_INTERRUPT_VINMI, }; =20 if (!arm_feature(env, ARM_FEATURE_EL2) && @@ -955,8 +1075,12 @@ static void arm_cpu_set_irq(void *opaque, int irq, in= t level) case ARM_CPU_VFIQ: arm_cpu_update_vfiq(cpu); break; + case ARM_CPU_VINMI: + arm_cpu_update_vinmi(cpu); + break; case ARM_CPU_IRQ: case ARM_CPU_FIQ: + case ARM_CPU_NMI: if (level) { cpu_interrupt(cs, mask[irq]); } else { @@ -1350,12 +1474,13 @@ static void arm_cpu_initfn(Object *obj) #else /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { - /* VIRQ and VFIQ are unused with KVM but we add them to maintain - * the same interface as non-KVM CPUs. + /* + * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add + * them to maintain the same interface as non-KVM CPUs. */ - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6); } else { - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); } =20 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, diff --git a/target/arm/helper.c b/target/arm/helper.c index b9443b1813a..f61a65d8114 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6046,15 +6046,19 @@ static void do_hcr_write(CPUARMState *env, uint64_t= value, uint64_t valid_mask) * and the state of the input lines from the GIC. (This requires * that we have the BQL, which is done by marking the * reginfo structs as ARM_CP_IO.) - * Note that if a write to HCR pends a VIRQ or VFIQ it is never - * possible for it to be taken immediately, because VIRQ and - * VFIQ are masked unless running at EL0 or EL1, and HCR - * can only be written at EL2. + * Note that if a write to HCR pends a VIRQ or VFIQ or VINMI or + * VFNMI, it is never possible for it to be taken immediately + * because VIRQ, VFIQ, VINMI and VFNMI are masked unless running + * at EL0 or EL1, and HCR can only be written at EL2. */ g_assert(bql_locked()); arm_cpu_update_virq(cpu); arm_cpu_update_vfiq(cpu); arm_cpu_update_vserr(cpu); + if (cpu_isar_feature(aa64_nmi, cpu)) { + arm_cpu_update_vinmi(cpu); + arm_cpu_update_vfnmi(cpu); + } } =20 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) @@ -6202,6 +6206,23 @@ static void hcrx_write(CPUARMState *env, const ARMCP= RegInfo *ri, =20 /* Clear RES0 bits. */ env->cp15.hcrx_el2 =3D value & valid_mask; + + /* + * Updates to VINMI and VFNMI require us to update the status of + * virtual NMI, which are the logical OR of these bits + * and the state of the input lines from the GIC. (This requires + * that we have the BQL, which is done by marking the + * reginfo structs as ARM_CP_IO.) + * Note that if a write to HCRX pends a VINMI or VFNMI it is never + * possible for it to be taken immediately, because VINMI and + * VFNMI are masked unless running at EL0 or EL1, and HCRX + * can only be written at EL2. + */ + if (cpu_isar_feature(aa64_nmi, cpu)) { + g_assert(bql_locked()); + arm_cpu_update_vinmi(cpu); + arm_cpu_update_vfnmi(cpu); + } } =20 static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, @@ -6217,6 +6238,7 @@ static CPAccessResult access_hxen(CPUARMState *env, c= onst ARMCPRegInfo *ri, =20 static const ARMCPRegInfo hcrx_el2_reginfo =3D { .name =3D "HCRX_EL2", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 2, .access =3D PL2_RW, .writefn =3D hcrx_write, .accessfn =3D access_hxen, .nv2_redirect_offset =3D 0xa0, @@ -10799,6 +10821,9 @@ void arm_log_exception(CPUState *cs) [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", [EXCP_VSERR] =3D "Virtual SERR", [EXCP_GPC] =3D "Granule Protection Check", + [EXCP_NMI] =3D "NMI", + [EXCP_VINMI] =3D "Virtual IRQ NMI", + [EXCP_VFNMI] =3D "Virtual FIQ NMI", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041796; cv=none; d=zohomail.com; s=zohoarc; b=itu8bMea5r922sR8EFJg3/aSgCcZSKeDzB9y5oZnF3pg9MI6sFxPLZDLbpUyD5QozL5YdeE9E70SM0Dr41srTuPnKpNHNuSJ92PHVAfcGuZyLuyloAjc5NxVhmPGnS/yd9VIizJyaGs2+nwmHwfUov+NlNscZWL2YXbVasa3fyI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041796; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Mn9K63HdD8L7FJC0CZzxAEg6D39lTDIquKUS1Fhgckk=; b=YR2QvusKJA4DzRdbLDZONOxdhTK1lGihw/fdhhOfqWkGbGHjGnqG6Y9mS76V/lv5cFDKcXVoOiry5hrAHIDWCcAaJ0W/vBBV9PKf9oGGAewT8JbB/azES/HmARZLudAQVb+IanEnuBJdlygG1NCU4U4kXDl8kSJcogcLTT3bnnc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041796461964.3723367954617; Thu, 25 Apr 2024 03:43:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWP-0001zW-Ll; Thu, 25 Apr 2024 06:40:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWN-0001y0-KS for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:07 -0400 Received: from mail-lj1-x22b.google.com ([2a00:1450:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWL-00079s-Ur for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:07 -0400 Received: by mail-lj1-x22b.google.com with SMTP id 38308e7fff4ca-2de232989aaso8444251fa.1 for ; Thu, 25 Apr 2024 03:40:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041604; x=1714646404; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Mn9K63HdD8L7FJC0CZzxAEg6D39lTDIquKUS1Fhgckk=; b=ceY2JbRKZ3Zgw2m/X/1TV6Pvj2+EQ8i1cPc1BWrKCtlxLzjZ8SJwHUTlp0caLXwIcK 5Vy8/VzdbN++cb3n3wTDMfiiRbl7C+V0+4xNTUAwmZIDsystLp/pxxHnSvaRFpFqC7Tq cvfhJ76YwfMdwihMr/uyJoO4pxEAJrBY+EBrYDTm21dx2iJAuVHhasKna5fraHoNi3Cx 72sArzuZLuAfCm+9LjOKiFTk/vLLofIzvK4ohbjyK0ilqtyvQcZliTrReCRQ/o3inBrE nq824MBFj3rf0UKO+us+PiC9Uo73LoDDtKtzhS2OeqN139zSXS+vXXDc+4bLHW7IR0gJ LIpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041604; x=1714646404; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mn9K63HdD8L7FJC0CZzxAEg6D39lTDIquKUS1Fhgckk=; b=HyQRy4X1SdwCQ4IfRU3FHTqjr9ZJA1ek/NKDi+pnFG7CZjE3tgEnaXhijNOiJTrxfq ZIj/4HdCnVZePoEnSNAf7CQpstJxPmllkUzsd0N2tjFpl4ERyY+wE4dQloNmz3mcig2T poafQc5CnSf9jw2iiQjugcQyoZUrBgdfLArUofsUj377YbQihKkdXDcrE0+ct4FMCCiC RwtkQ+wD8zY98XYKaibdfSyXPRzPvnZuu57uK5ySHk6lZCIKe36cedj1PC28p+7CRGkV bWpJwzUpEN2mo/BQemzjZihwsNcN+m0B+9FE2WV36TRk1d0fLScA8O2/2U1StsjfnXRX oV0Q== X-Gm-Message-State: AOJu0YyZhEekQ29v3UQoFHBf7iNPLlWPUGsSKBuqtxL0rZVoS0n7ukGg cMTdWJpqSHTJJ7sNO/9mmuSjFbjAH7iA77Ir6yIA9gh3ofIE9bWLEvhCI89XbcuJnYGjkn8dVlJ n X-Google-Smtp-Source: AGHT+IGfPYl0KtmFyP4UqpaLkWP+508nQz29WNu0e90cVrFAcmuMYyjio+FVAJYoN82GnMzhi3LQTw== X-Received: by 2002:a2e:9dd4:0:b0:2db:348f:5c28 with SMTP id x20-20020a2e9dd4000000b002db348f5c28mr3336495ljj.51.1714041604274; Thu, 25 Apr 2024 03:40:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/37] target/arm: Add support for NMI in arm_phys_excp_target_el() Date: Thu, 25 Apr 2024 11:39:28 +0100 Message-Id: <20240425103958.3237225-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041797459100001 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in arm_phys_excp_target_el(). Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-8-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index f61a65d8114..4ee59b37059 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10763,6 +10763,7 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint= 32_t excp_idx, hcr_el2 =3D arm_hcr_el2_eff(env); switch (excp_idx) { case EXCP_IRQ: + case EXCP_NMI: scr =3D ((env->cp15.scr_el3 & SCR_IRQ) =3D=3D SCR_IRQ); hcr =3D hcr_el2 & HCR_IMO; break; --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041995; cv=none; d=zohomail.com; s=zohoarc; b=n/hZ+f12d9UWp29Mb0JZ5WPoA7K3YZbhGbXsgB2lr71hOrGeuNoStjXeMxtvUUIYkLtCeEi6W9MlusgGXIiM3HY1supVk4MMmCJkz5u0xchK2uExt06aftUo/vsYmF8dV+UKSKAhas5t2TaOxZp2FLxnBAMtkE0s4g3ZtyuqPN4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041995; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=aKgAIExeXe22iXmvncCzPBD6wUC7eTZRMMv1MDBAcwE=; b=bVklaymndc1Lfd2Y34ZfcNiu8JUvjFpgYy6Xrae8a9in8iX01cbBQPdpC8NkO8ztfRRHjkxN/z6DNNvGIXAUwMlRp4djDOcwbcw1uzOXjKRlnUaepPbAitUXhNzSnDFIUuaGI9xNzDWiHTGKb3jZBnsN3MXnHl0IrbBB1WrxBOU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041995758950.029052957407; Thu, 25 Apr 2024 03:46:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWY-00022q-0U; Thu, 25 Apr 2024 06:40:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWO-0001ys-G8 for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:08 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWM-0007A6-H0 for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:08 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-34a00533d08so465366f8f.3 for ; Thu, 25 Apr 2024 03:40:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041605; x=1714646405; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=aKgAIExeXe22iXmvncCzPBD6wUC7eTZRMMv1MDBAcwE=; b=ZjT8EGa4SbQ2lcNkoeukDJwUQYz1onssSsS0noMIBneJQtqiDdZ6PonzUCzSk7Nfp3 DWteL+jCaDkVj6z1SyZS6jMeHe/Zu/7qa31WuvrLBChvTARnzsRb9WISxvBOsG6AMmlY KQdd88Yfq7t5UelBOZQSiNohu+Eqy5zcUPavJ1Komm/IY0ZagveA7+gT/CVKiWPldSvb C2BwufixCILM9rwr64AxP6l7LSkqhYpEXVeSi1IvrHVNTQolyYD5s6/gD/n4v+1PdlZG IYQy1e342viqnoqshRkWiv3kEnXkzLMvOSgsGAIIZ6GumwHUgg2cXo4tM6cN/kjftgqF W9Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041605; x=1714646405; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aKgAIExeXe22iXmvncCzPBD6wUC7eTZRMMv1MDBAcwE=; b=XHkgP43VO3WjPgEeA/9Kb6qQKXlBIKt4A4bKUlUXkV57DPrPApPm12jm4zbdV8dB/z gZKWzSe6zEZcHqSo6xJJLbC14d5ej5jR/H1dgFutCofnrSoOxw3Yua43pZH4dz5OUoeD 1niU6uu3cIj0qAxOKhKt5qSJpa/fz+uj9f7byBoer2fX4P7B7vKq761RZFKRlBY4UgOO 7hjoUlPDgq9zIDIrd/NuXe3o/EMV/+uT8mnRF0z2z1qZg2Jx6iB+3XVu61YmVNQENoRr f/TNyjqDYe9b49h7xkpdHJ81EYipKeHUJOiCSDaUp7u5k1wmqKxbhHMxQhcpaoKQDwMR zVmQ== X-Gm-Message-State: AOJu0YzZ5J17d/w7+suwpDCJQiSWSnBKl4wvCPaypqpIEb1ribX0AQ4v evb6bhFJq90BXwBLy493P6eLJ52X13n3/sKgJs2ZdddU0+CRvEgIklTFHylBloWIYSIt5Q6y+mj J X-Google-Smtp-Source: AGHT+IH4ZI0My2ovJWqjUWMox/A0hOF+S40KWYbGcCXyVHkq2Qb1XVK3lopDxZ75yeJQdpnyx49KwA== X-Received: by 2002:a05:6000:1361:b0:349:9e18:9f73 with SMTP id q1-20020a056000136100b003499e189f73mr5218145wrz.67.1714041605094; Thu, 25 Apr 2024 03:40:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/37] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI Date: Thu, 25 Apr 2024 11:39:29 +0100 Message-Id: <20240425103958.3237225-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041995978100004 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-9-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 08a6bc50de2..97997dbd087 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1398,6 +1398,8 @@ void pmu_init(ARMCPU *cpu); #define CPSR_N (1U << 31) #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) +#define ISR_FS (1U << 9) +#define ISR_IS (1U << 10) =20 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ diff --git a/target/arm/helper.c b/target/arm/helper.c index 4ee59b37059..6b6d8a349a2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2021,16 +2021,29 @@ static uint64_t isr_read(CPUARMState *env, const AR= MCPRegInfo *ri) if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { ret |=3D CPSR_I; } + if (cs->interrupt_request & CPU_INTERRUPT_VINMI) { + ret |=3D ISR_IS; + ret |=3D CPSR_I; + } } else { if (cs->interrupt_request & CPU_INTERRUPT_HARD) { ret |=3D CPSR_I; } + + if (cs->interrupt_request & CPU_INTERRUPT_NMI) { + ret |=3D ISR_IS; + ret |=3D CPSR_I; + } } =20 if (hcr_el2 & HCR_FMO) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { ret |=3D CPSR_F; } + if (cs->interrupt_request & CPU_INTERRUPT_VFNMI) { + ret |=3D ISR_FS; + ret |=3D CPSR_F; + } } else { if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { ret |=3D CPSR_F; --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041665; cv=none; d=zohomail.com; s=zohoarc; b=NsjNpuvE5R+t9DUM5RsFQP6db5d9gzvzIZXBzUE5RIE4hDNRbU3190go+9UsMBuYl9xxjhEt31HdjmHy1lefx0swrInqmRZ9pKMAzLgY4mpZIrCMg+DkzBY9YIxqn2hx5d3z4lRq5BbA6S66r3D2uTk0Oe6tdURiCUp+x2d7LWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041665; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=gARoGDMIdUZMnXzrWbmOnf1y6D1PI72py8fT6x9T7So=; b=L64r1CnZ/UTV3Oa8E48VHLXqargITYT8KWuvBdRkJQrhKZbhhn6amd6BfjDOGfHWTLtsS5j4SH4I6T5cIYQM2l090YmZezysUvG5WgR/4iOL3zVOmuFQwnxp3nRntu2UBOyM7T1W0D2izXe+dQOTnH8qmav3bFjX3RiaD70M9uM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 171404166548028.91738633367106; Thu, 25 Apr 2024 03:41:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWX-00023H-RS; Thu, 25 Apr 2024 06:40:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWO-0001yv-Lt for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:08 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWM-0007AJ-Td for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:08 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-34af8b880e8so514390f8f.0 for ; Thu, 25 Apr 2024 03:40:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041605; x=1714646405; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gARoGDMIdUZMnXzrWbmOnf1y6D1PI72py8fT6x9T7So=; b=N9QbpVIxHKWlzqsaqCJ3MppvdyMHvEbnbbT1E0eMm9osg1KeZIZqLEOZUBYILjk3WI W+lBAZY2cyZPtnztqwc71SnISeJeLrd+k1cbGqAW4RUEnhMgG/GyR1y/egS1NHQOqcgl m1hR5anGpQ5GiZFzhxgNrJ6+gPw1lBBbUwAvdz6Iy/3X+hTWiarMy0dtd0YD5UC/CMUI OOwugGAZsPSGbNzSqpVETjmFL7Bqlk2jBOARN860BABDw8rrjTEAwGtisclRcVoAkwFP IrL8ZXw5g+yxEM8xyhXoHCs6aXs1BfJk3i02IDVti0D+hj67tv4UtfdMR+yu8xCoaW6M o3Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041605; x=1714646405; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gARoGDMIdUZMnXzrWbmOnf1y6D1PI72py8fT6x9T7So=; b=fYhXq1lSyrst5G6MfjIm/SyrZGr4mFeNATwAsKiEsW7Rs6V03bwJEIT1ij3kg0YIHR QNH5kJGhzFVhC5xHVcfdRD9li/1GLjqZM2fxiP5vP1iGScMa28+POddvAGgDIwag8Iin wrymCvoAGaWxWrdB2bWNXCdH8q0mVOH2zJ/jFoz717lxdPR+5dAE87y2RysYV5DGGgW3 d5c53Sj5h473UKvsMZ/WjIrbBHz7fkEDD8Ssgrx+ioSFBxaC6JkygVoIPrWfp+uxMown 38AKMuZxvM4iFu1MPWMQ8xXXzGMZSYBTpGY7z1ai9eOGelZkSbpCDPGa1+8Lt084iiQ4 bdIw== X-Gm-Message-State: AOJu0YzMl+yUsYTPP1vngE/McDk0wKgwoTBXfA4u1kupYyLc5Z6WzZuI m3hHPJCrrYEBskRSIh0ky5XhSYziCHdkxc0Gstwwc50RYnqHKZI4HvZIwtJb3Mb1FrP+seXO70x r X-Google-Smtp-Source: AGHT+IErkZXY+qwYkYiUygEITthTgLNfIPVDMdXrCNnDPmEDaW/2nXIJ7XZrxRsUPLd4Noc432qiCQ== X-Received: by 2002:a05:6000:1967:b0:34b:7f51:7bc4 with SMTP id da7-20020a056000196700b0034b7f517bc4mr1485361wrb.17.1714041605499; Thu, 25 Apr 2024 03:40:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/37] target/arm: Handle PSTATE.ALLINT on taking an exception Date: Thu, 25 Apr 2024 11:39:30 +0100 Message-Id: <20240425103958.3237225-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041667209100003 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan Set or clear PSTATE.ALLINT on taking an exception to ELx according to the SCTLR_ELx.SPINTMASK bit. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-10-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6b6d8a349a2..5ff9e44649a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11733,6 +11733,14 @@ static void arm_cpu_do_interrupt_aarch64(CPUState = *cs) } } =20 + if (cpu_isar_feature(aa64_nmi, cpu)) { + if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPINTMASK)) { + new_mode |=3D PSTATE_ALLINT; + } else { + new_mode &=3D ~PSTATE_ALLINT; + } + } + pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 =3D true; aarch64_restore_sp(env, new_el); --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041940; cv=none; d=zohomail.com; s=zohoarc; b=gk2wsHAeDSz3wEIAp8okoSzsbPQqzA7zUTDj3pVKXgQSVoYuwwmkRPgppn2m68GFlqzPQRhzem3/c/Y1CD0HhJdETlHPjeACx3pxK528uE5Ynj+MvNbDCn0c0E16EtmU3VA1YWL/zGj9/GZu1lOyjzoj5OMOtJ1+eOTXtfX8cvY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041940; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=W1vuqdUJDiebxiqtPqaJPfGS9dPS4E9rgVyHYzZb3+c=; b=iIum8lxkl3oI855xtEmpDeV4D4b7xKGJGlg/r/VQPpX13ROco6DsLq0wBuM+TpTAN3eZkgL791IqlVbh9MyZtAilOK9MfHeDBM7/5pAO/HxdG/trWTNB2ovfP01Do9Ioy9zGBv/oAH2b9GJFqmCmFl8r7SyEYBNimkltGOstU7A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041940166898.8671134268709; Thu, 25 Apr 2024 03:45:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWT-00021N-QW; Thu, 25 Apr 2024 06:40:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWP-0001zZ-RE for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:10 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWN-0007Af-G0 for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:09 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-41b5e74f7d1so1547975e9.3 for ; Thu, 25 Apr 2024 03:40:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041606; x=1714646406; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=W1vuqdUJDiebxiqtPqaJPfGS9dPS4E9rgVyHYzZb3+c=; b=p8grnZL1z3qbL89vrf5wkWOCirFMBQrxvEiCmeb4uenZSyJU1/SuJoEWAvzgP1Q2FM XNPsgAcHEnGXhKSZItRfAsrg9bgIviaBIhNqqz4WDVl8Stk5S5LBmrq/wW4Z2oI/XVLn bqVSl3DF1knP3pm1XR4GN4l5zyOIWDlzFv/xLJSiXWzq4kg2mXbrksr1/a1iIhsKRGJO /TN+v6mRODPqDgHpTDrlSK5KoehleuVFXfBeU/R4z9e04m8vXEItRQaueZZY5xfsqeym 7eq7RJRQwPY7RBp1MoNKuqSPhRHI4ugRv1yVay3bLBOHIIFMBSCFwnFFBpY+0acz8YXQ RgGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041606; x=1714646406; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W1vuqdUJDiebxiqtPqaJPfGS9dPS4E9rgVyHYzZb3+c=; b=cbtghypzAj847iwI0M8sfGQNTfhzh0UFzl3pbXGypuVxfQcKxuZGO2aejSYVAiVHhU a8RLPUMEAi3Y4LEmC0zjaEuyBinSl2/StzDuYBMoBQ4lDYrmdv45dbEZtb6pH8R8a/za WEX7AldeKuJ8GcrzgTCVAdJoKYp1ZOBcKIgEar1wq8/Ka3A4ZRQZn0mXFsMBU0gwdc3R T0eUPCgbDmWlGe3MfoiIHkjrVCV2nhhRuan9FgEVhbGI1efT+CP38ONhbPzw91DsAcVO MSnsAtNC8U3gCExb4CgL5fIrB1fSW8W3Re5fDhVj17ho9vs0jmzjLGYRYMXEb6QZ8bPw zbAQ== X-Gm-Message-State: AOJu0YyGi9VSK+kYo21BmC3eCarmZ4DFi2L1TtmFJSQ9fuXTYa1VTWG8 IBLFTRp1M21sAiuQlkyWyhrFc0SpcFEr+HsQeJHuKghsDPqumXOWKtb2jEN6d2vMWjMjiu90GQb n X-Google-Smtp-Source: AGHT+IFILE5l75VqWQQrB+py+3SebJkG83ywHExDMjZ9HLxI4QlpyCrmH1HVNcFqYSphd26gBeCUEg== X-Received: by 2002:a05:600c:35d4:b0:418:f184:53f8 with SMTP id r20-20020a05600c35d400b00418f18453f8mr4732350wmq.36.1714041605985; Thu, 25 Apr 2024 03:40:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/37] hw/intc/arm_gicv3: Add external IRQ lines for NMI Date: Thu, 25 Apr 2024 11:39:31 +0100 Message-Id: <20240425103958.3237225-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041941942100001 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan Augment the GICv3's QOM device interface by adding one new set of sysbus IRQ line, to signal NMI to each CPU. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-11-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- include/hw/intc/arm_gic_common.h | 2 ++ include/hw/intc/arm_gicv3_common.h | 2 ++ hw/intc/arm_gicv3_common.c | 6 ++++++ 3 files changed, 10 insertions(+) diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_com= mon.h index 70803750081..97fea4102d3 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -71,6 +71,8 @@ struct GICState { qemu_irq parent_fiq[GIC_NCPU]; qemu_irq parent_virq[GIC_NCPU]; qemu_irq parent_vfiq[GIC_NCPU]; + qemu_irq parent_nmi[GIC_NCPU]; + qemu_irq parent_vnmi[GIC_NCPU]; qemu_irq maintenance_irq[GIC_NCPU]; =20 /* GICD_CTLR; for a GIC with the security extensions the NS banked ver= sion diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 4e2fb518e72..7324c7d983f 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -155,6 +155,8 @@ struct GICv3CPUState { qemu_irq parent_fiq; qemu_irq parent_virq; qemu_irq parent_vfiq; + qemu_irq parent_nmi; + qemu_irq parent_vnmi; =20 /* Redistributor */ uint32_t level; /* Current IRQ level */ diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index cb55c726810..c52f060026a 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -299,6 +299,12 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_= handler handler, for (i =3D 0; i < s->num_cpu; i++) { sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq); } + for (i =3D 0; i < s->num_cpu; i++) { + sysbus_init_irq(sbd, &s->cpu[i].parent_nmi); + } + for (i =3D 0; i < s->num_cpu; i++) { + sysbus_init_irq(sbd, &s->cpu[i].parent_vnmi); + } =20 memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, "gicv3_dist", 0x10000); --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714042137; cv=none; d=zohomail.com; s=zohoarc; b=TeS9cGaQ8UnI8sN1nDtqdL5Z7vs8IL3oayzwR1rgo3DgF/boAxk8DM8i6oy50dkA/PvyGUcios3AR+lFhckJBNAIuM19cVVY+rpIJU2wGkz7OYTLS7EVL16121ICnzVq66OQjFLbIZl9//fd9+5Mk8dymCyWW7c6KkDVnYdm5cs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714042137; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=b6yIAJM8jr7uSpt6r8if5DSOdOSQk5RvqykVEUvE64g=; b=aIGez3fCnSiY8zF5QjIrfbEE22DG/ieJwGbmFyCT2tKaJFyl4MLH4kSzZHlfS/NSn1XSdqrk/fI7EVSu/5ouWC9Mj79TVyIsF3qKtaG7EfMyhvMPe7ATsvG8bHxEXKQsnNCZPg/jrQoOAqCb5caIpgE3PcNaw2XwI0EXcIlyMGc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714042137544877.7400519281039; Thu, 25 Apr 2024 03:48:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWZ-00023x-5c; Thu, 25 Apr 2024 06:40:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWP-0001za-Rx for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:10 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWO-0007Ao-7v for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:09 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-34c09040154so412764f8f.3 for ; Thu, 25 Apr 2024 03:40:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041606; x=1714646406; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=b6yIAJM8jr7uSpt6r8if5DSOdOSQk5RvqykVEUvE64g=; b=YPRs4cYsaYHY97jxa0Ozwm+RG3Zws7TRiTWbD+I4LiVUZyOkoY12FkFNDE+eTtllRx 7RvNNieuGmNJ5KbUTe2WU/M/6jQInFjNEtZkS74x2T1AzQXdqZZtcvdKGqXkNIz/7PJd OKGPu7UoRuVRUJnunL1xVuFDHlZo67hZvAOQbFdDf8tZrgdaPhHYYx933ckb6sOYFxQg E/Mv63d6af0HuqhYB5ONF2ghlhFs463OMdQZQm5a5rNZte5BIdehtASwsnfHWYMMn96m jx5h8UaHfwOeqMbJ0bykO1NjwQoNfKr5Q6druXmGAsF7BPFfGN8H4/Uno2nLVikmrMog O8PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041606; x=1714646406; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b6yIAJM8jr7uSpt6r8if5DSOdOSQk5RvqykVEUvE64g=; b=fIfL3KrEtliRcRaTX1n14NHMcN3yY17L99sIa+GKg+FH912n4VrJUyrOvQ6+DolGTf vUeFwXIz16Db6i5mAy0+T6EFkwSkR5/jfM7mi2UCutsZcKbgzimwohpQA45mEwlfj3lO A2jKO8C5XOPWo4T45wg2MtzxzLr7bkhP1QmZMIO0FR2veAyZVANDMWmsQ3NFmFAJ6C0t TG4pF67MYecFKIX8VVS46vc02yGAoBOoVVQhzZ8toxYZDah2cfuPqLljpyu4XPR0lsxi mtgo42HiAIfB4N+FyVc1hmODYCSGzpVUg6Tk7R+nDSHale7vKwdAI/dZxftvilnOgZro /0Sw== X-Gm-Message-State: AOJu0YxPCdymPLIZEzV87dFeBYrvMaqOTJ6d92sfmHqC8x2RhwwExf0p ZhHUR3RkuFdfV+fwyXhk2eX3RIiKpqyEoF2EUX5xJxgTNCMweKDmnWM169K+pHFWJVqAIr7PoRS q X-Google-Smtp-Source: AGHT+IEunhto1DYegTMoTqYfpazsOcWviVv5WM0Xs1q5WXDh7tAE0qPpdVz04ZUYT5J+bmAd3XxsQQ== X-Received: by 2002:a5d:46cd:0:b0:343:edfd:113d with SMTP id g13-20020a5d46cd000000b00343edfd113dmr2818121wrs.71.1714041606455; Thu, 25 Apr 2024 03:40:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/37] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU Date: Thu, 25 Apr 2024 11:39:32 +0100 Message-Id: <20240425103958.3237225-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714042138401100003 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan Wire the new NMI and VINMI interrupt line from the GIC to each CPU if it is not GICv2. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Message-id: 20240407081733.3231820-12-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c9119ef3847..c4b03b09c27 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -821,7 +821,8 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 /* Wire the outputs from each CPU's generic timer and the GICv3 * maintenance interrupt signal to the appropriate GIC PPI inputs, - * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inpu= ts. + * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the + * CPU's inputs. */ for (i =3D 0; i < smp_cpus; i++) { DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); @@ -865,6 +866,13 @@ static void create_gic(VirtMachineState *vms, MemoryRe= gion *mem) qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + + if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { + sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); + sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); + } } =20 fdt_add_gic_node(vms); --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041807; cv=none; d=zohomail.com; s=zohoarc; b=IwQOLj2K7p1jhM61tG/00xlu/u/d5oM96DgWfZh7LvQvcdo6ebU/j9ydckEk2b+cDuNBRyLAdy1YIR/aCrOcW5Qv/zK3cADZpgLDP0ohRHia9S17TsDY54dlSyFxU+xrEx9Jq7amxsFn/Wvy+nXH6jz+6sFVbDEAnr8LHUEtT24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041807; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=k3HQo9h6O4YNEO0q4im8nAu5Lx/+PmmdfjaGGgAzyoE=; b=IbT9sSQMETA5mcufVP6QWrT2fgY3uitq+stutwe1Ms0wXrnUXCwJpcFLj1d5nSL4UHw7HVHbTmvPqTeunWQ/xiKzx4veJDzUS8V5CTnr5F7facW5v3GfBTm+J6EAphrijOJq9zJhh5nLT16JUhCzhZTEq5K/mZVd7xOO6Q/X9Os= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041807661385.30167656239644; Thu, 25 Apr 2024 03:43:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWW-00022U-Gf; Thu, 25 Apr 2024 06:40:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWQ-0001zc-6S for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:10 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWO-0007B1-DY for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:09 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-41b5aed246dso1833265e9.2 for ; Thu, 25 Apr 2024 03:40:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041607; x=1714646407; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=k3HQo9h6O4YNEO0q4im8nAu5Lx/+PmmdfjaGGgAzyoE=; b=xIn1VHJMsaCip0KKKhOx+TDsiVCHqx89z6i+FZmiubMWHO6OOOl+ECvPyLm78UJ98B xueRJmlD8hpm4aD9Y7Rm/0LfzccFIJJ3iyWhPTK3gVpuFcvaJx1+4fs9VHh52QzuQyT1 3FyO+DG5bwwwJTOXoIwlZH6hgjlBG05Az1v002ReUjMmq+EDAhRU8LeMp+WlQTuLZlug E2fM3I/y/1oRbJPHPWtyfQ1O8kc8XmgxrdiZAGEeAm/BGiKmlB+tdjRpk3M3eGYlzwF6 9DXHkZ5omMXYSspfC80V8llKdXbcE+8+zu2mHvl77CmDpk3XCbQNuijbu8ADIOjbU5Wt Y8/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041607; x=1714646407; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k3HQo9h6O4YNEO0q4im8nAu5Lx/+PmmdfjaGGgAzyoE=; b=StBzr5rps+44RZ2AxwhTPA8n6g3iBgQ5E6r+/J99IKWNTB5LqCIdBCwUdteSK2v1oz LSxN152lXVx65QpVpq0OOUAY9JuhJMEDTuXbCoJZB7O2VGqgrVPajLoLLRRnyEyYcFgv vDa54YlQFnUBsXNS/X63GAFrKz03cXc1UN8+cl1+F2zHX+UJj4PtYuwaQ9c4uDBEXGd4 Y7huJm0s3PJFjuhhKj+FSSL+ALhcjleTB2TUMNj7zLv70v9zFLRdILxA4sb+3kEJA4/7 HxbHC4TX5wb5JGMYizO/IHBdq78ZpDRe2FWGdxVbdrECVw/J0/gIWatapDDRBp7Xl+fZ Kn6w== X-Gm-Message-State: AOJu0YyfyqR+rGOcpWRUeLQiG629KQVSFAjamgG8qAqz2oeAlttGCsIo +Vv+qgmWgBWuHuNLcAHAPeIRc2Cadlk2Ag5eZBRtCw8uroMHFfeHfzufOEYRjxBHBQcF7xs1o1u r X-Google-Smtp-Source: AGHT+IEoSaLuZlwAxp/K4AATgBO7poCtRidPGko92k72xJ93hSjRbYlVnf4PCWGFGSTytWLcytgMkA== X-Received: by 2002:a05:600c:4f03:b0:418:ed13:315e with SMTP id l3-20020a05600c4f0300b00418ed13315emr3712939wmq.2.1714041606966; Thu, 25 Apr 2024 03:40:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/37] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64() Date: Thu, 25 Apr 2024 11:39:33 +0100 Message-Id: <20240425103958.3237225-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041809530100003 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so the NMI exception trap entry behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the GIC or come from the hcrx_el2.HCRX_VINMI bit, VFNMI(vFIQ with Superpriority) come from the hcrx_el2.HCRX_VFNMI bit. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-13-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5ff9e44649a..6b224826fbb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11653,10 +11653,13 @@ static void arm_cpu_do_interrupt_aarch64(CPUState= *cs) break; case EXCP_IRQ: case EXCP_VIRQ: + case EXCP_NMI: + case EXCP_VINMI: addr +=3D 0x80; break; case EXCP_FIQ: case EXCP_VFIQ: + case EXCP_VFNMI: addr +=3D 0x100; break; case EXCP_VSERR: --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041996; cv=none; d=zohomail.com; s=zohoarc; b=aHHkJUAS/ADzRPywKMkoPWfyz8vr/FYFwU+vsc5ClSLq5W/qsesQxDDb+Zs95n5BMr5Jd+a5RiYKu01b4gof84qBttcgk/3ZTXagCCefLNjHJSuC8D+1oCaAy92fnsej+JZW645KPXp+jShCUHyhBw24qvoSeAqPU13TKiH6N1g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041996; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=uNspTAtU5EEDrEwByNRMRLu3g41/4uLvJCYO3m3A7Lk=; b=B0NnKcEEZfMD42R1Ys2aASmjW0RWGRl7+NJCXphBXBjApd3dSydPLEZoX0kr2xLIR+mumNetuJmtQwNgYEgJ+5FzPerUl1Vl2xbWF8hzox4RynJNTUnigzxddZV+cbj7NJnm+W2ooCS+ZtfEyc++qqHG7hWZWx6dGquE87A2dug= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041996924416.40986098222027; Thu, 25 Apr 2024 03:46:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWY-00023h-Tc; Thu, 25 Apr 2024 06:40:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWQ-0001zp-QU for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:10 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWO-0007BB-SG for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:10 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-343e46ec237so669892f8f.2 for ; Thu, 25 Apr 2024 03:40:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041607; x=1714646407; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uNspTAtU5EEDrEwByNRMRLu3g41/4uLvJCYO3m3A7Lk=; b=J68u941rXX9MnpxzrrzYI3EpxyLXe7AvTIRvfitpcDzO0GvXY7N43rr3S/ZzjdSvPm 473iqos/YUvF2j4g5m5lMPd4TeKOWkxal3v/dGnpGkpuqACFFxB9O6WRYdWYne5UPXOz gsCw4peL0POsRuRDh1KOy0+wMj3IMStjAVqXog8nCHJJbrBKjiW5Ywasf8Rx8xgS95Xn OI040NRzBDeRNBeFZBlW80ziTtNnGpnSlAtl/6kbsMI9MAc3vmbP9Z/WDc0b3S20My2A xhJltiaJTEpGdwRx4VaxGn+cPGHos+OyG39d+/A2APAOEJIV14omkdx8tZmvdC4qOX6M XQ1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041607; x=1714646407; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uNspTAtU5EEDrEwByNRMRLu3g41/4uLvJCYO3m3A7Lk=; b=qfLgt4SJpiHpC9fjxB2IZnMW8JBWdIRnsY6vn9jqGOKz3No8fI7hfTVCNKQSVJINOu zXhxei/f7quELqhc1RLms+p775O/acpxYN9w35l/OaEhJvKp6rc8B+IXoiiL+/LWEbKe F5yATSFpNNyO3x99q/jFC0YpXyrmgZWJ5X8BbnZOuOaOn253MNTDse38WO5PdpI2yza3 tFJEpEJrDunBFsi782yIGoaYKzkoEwiZKX8c20bLpM8g/KPk6C8pg/Ix2T7WIEEvm0n5 /+MowfuBgkx59tdPpXD3eWzwqt+cDeAiYMv1eUNyYHIfmcGpFDSw43nZpm5VZzFYNRgs TC0g== X-Gm-Message-State: AOJu0Yyqoa+FOJuVmaJ2zid7mcNxXNpSVHRZ4tsXWixqPSKcG/q672/k dNp0RfZSbBZx+xyEBO3k3wuCPddhT2HSU+DoY/Fez7Lg4TzoyUXZHHVyfGzXSWHvt44uIaF2N7t G X-Google-Smtp-Source: AGHT+IETpKrHhN5BW/MZiS2IsgPcpdYDlnFnjzES2iyzJQZkN4lnxZG9giIGeJCySc+4y7alUmxjkg== X-Received: by 2002:a05:6000:d92:b0:343:b295:4d99 with SMTP id dv18-20020a0560000d9200b00343b2954d99mr3907998wrb.56.1714041607424; Thu, 25 Apr 2024 03:40:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/37] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device Date: Thu, 25 Apr 2024 11:39:34 +0100 Message-Id: <20240425103958.3237225-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041998035100027 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan Add a property has-nmi to the GICv3 device, and use this to set the NMI bit in the GICD_TYPER register. This isn't visible to guests yet because the property defaults to false and we won't set it in the board code until we've landed all of the changes needed to implement FEAT_GICV3_NMI. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-14-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- hw/intc/gicv3_internal.h | 1 + include/hw/intc/arm_gicv3_common.h | 1 + hw/intc/arm_gicv3_common.c | 1 + hw/intc/arm_gicv3_dist.c | 2 ++ 4 files changed, 5 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 29d5cdc1b69..8f4ebed2f42 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -68,6 +68,7 @@ #define GICD_CTLR_E1NWF (1U << 7) #define GICD_CTLR_RWP (1U << 31) =20 +#define GICD_TYPER_NMI_SHIFT 9 #define GICD_TYPER_LPIS_SHIFT 17 =20 /* 16 bits EventId */ diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 7324c7d983f..4358c5319c1 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -249,6 +249,7 @@ struct GICv3State { uint32_t num_irq; uint32_t revision; bool lpi_enable; + bool nmi_support; bool security_extn; bool force_8bit_prio; bool irq_reset_nonsecure; diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index c52f060026a..2d2cea6858a 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -569,6 +569,7 @@ static Property arm_gicv3_common_properties[] =3D { DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0), + DEFINE_PROP_BOOL("has-nmi", GICv3State, nmi_support, 0), DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn,= 0), /* * Compatibility property: force 8 bits of physical priority, even diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 35e850685c0..22ddc0d6661 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -389,6 +389,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, * by GICD_TYPER.IDbits) * MBIS =3D=3D 0 (message-based SPIs not supported) * SecurityExtn =3D=3D 1 if security extns supported + * NMI =3D 1 if Non-maskable interrupt property is supported * CPUNumber =3D=3D 0 since for us ARE is always 1 * ITLinesNumber =3D=3D (((max SPI IntID + 1) / 32) - 1) */ @@ -402,6 +403,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, bool dvis =3D s->revision >=3D 4; =20 *data =3D (1 << 25) | (1 << 24) | (dvis << 18) | (sec_extn << 10) | + (s->nmi_support << GICD_TYPER_NMI_SHIFT) | (s->lpi_enable << GICD_TYPER_LPIS_SHIFT) | (0xf << 19) | itlinesnumber; return true; --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714042104; cv=none; d=zohomail.com; s=zohoarc; b=mdzg4fnq+2wL3dEluJaAwIZefBJlmR93Ya5OxryOKw2+QqXrMlGsO9vk4dHezGXetQcu4jdZ7eBXa9LgVageOe998z6VPVvQDG+k9PQuR81qFc7i3P/auAEgF0OsR+mjbsE42z9411seFBCuYtnln5qadDCCVV65UrsnjTCXnWo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714042104; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=qTCnu62k+8U/GjNoTGBqIqRdrEXskM+ZoSSojfJIbBw=; b=JTM9Y7+MMoGT7BZoy5/f3tN59KXMozR2+b5oAc7fNsOqxdrt9PKwhCGivD0Za8C6h5oYOcsjzhSGUac6iBv9CaPO3QmZuCubuzrKrrw67QUoyltOFEs1KXjREYiA4qdxFeAXpR1HV88Ko7j0x1Tm4hKzy2gV3FeKE0wRcXXjz1c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714042104839299.5778812189683; Thu, 25 Apr 2024 03:48:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWZ-00024y-Nj; Thu, 25 Apr 2024 06:40:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWQ-0001zx-UP for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:11 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWP-0007BM-9K for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:10 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4196c62bb4eso6441395e9.2 for ; Thu, 25 Apr 2024 03:40:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041608; x=1714646408; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qTCnu62k+8U/GjNoTGBqIqRdrEXskM+ZoSSojfJIbBw=; b=YXp1e3M1Z9c+SSQa9H77H3X3JIQ5X6PgZtrXsUGIMv4SYX1qaH0cQ7nwDa2R9iEdGv zCiEAlMTkTW38+sKO1rTxDsdkhHXveY2LqF/F016nzlGHlYstwjYNXNwUn/M8b7iBGRy gSP9+2m5pq9+nm7K6CP0P6jwf44wKKDv8S1fXUhPp2mS6kPtDniC4PTz3hMS+ocXQdu8 070VNCKmUrJYBHysa3lZLFeDK5/NV1bDYtV3JcVdPEFtFK1W+6UxfNMPkkvw4hCLCCgd BfxWhphZIBlaY2UGQa6oFY9yogCyNBlM+dyF5vpy2pUiN1fe3OOO5dyYZsNP3bXUZifO iOtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041608; x=1714646408; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qTCnu62k+8U/GjNoTGBqIqRdrEXskM+ZoSSojfJIbBw=; b=izPigaV2FjHSfz/R/iy93c5zUMEdtjHF5mpryqH1Zc5gGJ8U9AmJPuGlMhAlWksEku TieSpUFUoSKdxPWJ38doLVuRoMzagm6JZRhy18KuX7RFwHjj2BYa7Osdz/Fn7ITdv1io aOwn1SD54Xc3hxlmbt06OBICIuuxLvbOyxzLMWJhSk6qTlVCWUkgf+/NOhxFMc4OxbuQ gHqhYeNYscCS8X1Xr7/gJC8wBU2kKj8yNsSF8wgl7hvIe6s+QW8gCYOdhTtTA+3Xm/IX VyknU5MK0nRbXB/qgeQmfFdufHvAnASOjqf7LS9aw/uZQ1Nf3VQpIRs5jxv5KdrqT1o8 CE0w== X-Gm-Message-State: AOJu0YxZgm4VBb7HY1huiT3q09pP8W/htzYJamdwRF8dOwTQqx4zpprE bikzsef/DOI1QaIvO2/d20C30ufcLINtd3JGRPKdXPFjq1hjy7pZHXbusPOi/S7Hzq6jfqaM3Uj N X-Google-Smtp-Source: AGHT+IFgvYz/LL7COI7sVcEFIk86rsMy7bHZdmbmd/IL5LKkjeAXw5WTY7QNHEBHgYe89p/qdxAbqA== X-Received: by 2002:a05:600c:4fd1:b0:418:be2e:df9e with SMTP id o17-20020a05600c4fd100b00418be2edf9emr3499976wmq.41.1714041607855; Thu, 25 Apr 2024 03:40:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/37] hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3 Date: Thu, 25 Apr 2024 11:39:35 +0100 Message-Id: <20240425103958.3237225-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714042106310100003 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan So far, there is no FEAT_GICv3_NMI support in the in-kernel GIC, so make it an error to try to set has-nmi=3Dtrue for the KVM GICv3. Signed-off-by: Jinjie Ruan Message-id: 20240407081733.3231820-15-ruanjinjie@huawei.com Suggested-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_kvm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 77eb37e1317..00a383079b9 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -805,6 +805,11 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Er= ror **errp) return; } =20 + if (s->nmi_support) { + error_setg(errp, "NMI is not supported with the in-kernel GIC"); + return; + } + gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); =20 for (i =3D 0; i < s->num_cpu; i++) { --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041877; cv=none; d=zohomail.com; s=zohoarc; b=gMQqw6IInbjVsDp4M/QlU3IPEA5rUm9eqODuhhndk284+p02VZr48TyYfBvLTM05fXcI03hUwwRnzVKXXbJAWAO84cVmwVY2R5dJAkHvigi6H5RqnIwOCScTMGluoxV9I0z2Zoy4wDK0Rk40UPQBaRAH1nuxa6J251TfpTY2tfA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041877; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=zL893TbguEiecy15rywhbwwUs63qI5E247V3sEKStjY=; b=BEJIYGeXo/Rd0/ABOJvNsnNnZOYrLSenPRwqtYrG7H61jzFW5jI7piAC+Jee7j+UcEG4ScBHs1RZmzcrQSKjDASHsou5r9KzIkYITSeUSZVtEGUy5BFo4bmrFAE8diYTylJFH4qEkKgJ/0QMSSU2mLNZgE1k8wV72JE/X5i3Ck4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041877664384.4545608378312; Thu, 25 Apr 2024 03:44:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWa-00026c-4D; Thu, 25 Apr 2024 06:40:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWR-00020M-HU for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:11 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWP-0007Bi-Mk for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:11 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-34af8b880e8so514426f8f.0 for ; Thu, 25 Apr 2024 03:40:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041608; x=1714646408; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=zL893TbguEiecy15rywhbwwUs63qI5E247V3sEKStjY=; b=G95NYyVTWwuPMgTF26x6ZVNQSqr9vRS7h7Xp9SsrblBbQww8fe2Tdn8ypOTOEwwkME XTluFPQ2gRGk5kWd3VD38DABFAUx1a1Sj8l/ODF+kf13P8byqwP68GuwJw257znMHN6z plDk2enUFdTM95rZPCYdfgdCrSonqt2wnsKnK+1B/DUOqZkVeWpowkdOAozIGB1vtVAY apdgm4rfsCL5TlIih3WvjdacioOx0JJQ9bJpoAdCc7xlVWJ05WFgq+75Rd5vyOzuYgw0 QAMf5Xf1vMNhoDI3URygOTmoTUJpxmhS+W3TiUDe6b8CuR/bQMWssK8NspsGKe8cA+sZ bK7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041608; x=1714646408; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zL893TbguEiecy15rywhbwwUs63qI5E247V3sEKStjY=; b=Zz5pDLcjxyg13v926CzBt99ibOceZ0RzBLBKmIBgya7aUGhVRVm+LvuLjUhRlentV7 t0sXMRKYvyxFbOE1qpOFtNgwlLJzv6f3DdexeHNE1noH/1bCHE0xDvyX/z6Ojt0pDW6K Dz83flL/awI1DMAuqgcrN+MH02h+1sCH7VY+RHFoRDQFLd6HEabubEQ2v4wXF3KJ0Sb5 ijsl1oJF10IawuZ0eRGZGjuBc8Ql0fZDmF3w/rIyV1EgJ533PeywdyQz/aksNVBTYOA2 a51V2Ahr0rpJhfjsP9Oqr9GJ9ea2DDwm9wviVD76DGue6LM+OmSsVKaZ0PE89Dl83hng t1HA== X-Gm-Message-State: AOJu0Yz+lwGvwesxK/VcWZrdkTbdbrNhe2aQ0UAumi9io6Bvj06LQG/Q 8isDVLlMD9saKlBPw1J2mk6Pn0nEKLw2wKJFBlfrFKOtaDsLofU0/yAGdyeJm7YYxjFoYWluxsV p X-Google-Smtp-Source: AGHT+IGmBhCLFLnZyFRaTA+1RvpEWQZvX4SIeWDi2w6sEnxkT1zdfC8oZPT8I//CkFDwgzelp9w/Bw== X-Received: by 2002:a5d:47c8:0:b0:349:fb67:896e with SMTP id o8-20020a5d47c8000000b00349fb67896emr2192912wrc.3.1714041608261; Thu, 25 Apr 2024 03:40:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/37] hw/intc/arm_gicv3: Add irq non-maskable property Date: Thu, 25 Apr 2024 11:39:36 +0100 Message-Id: <20240425103958.3237225-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041879693100003 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan A SPI, PPI or SGI interrupt can have non-maskable property. So maintain non-maskable property in PendingIrq and GICR/GICD. Since add new device state, it also needs to be migrated, so also save NMI info in vmstate_gicv3_cpu and vmstate_gicv3. Signed-off-by: Jinjie Ruan Acked-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-16-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- include/hw/intc/arm_gicv3_common.h | 4 ++++ hw/intc/arm_gicv3_common.c | 38 ++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 4358c5319c1..88533749ebb 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -146,6 +146,7 @@ typedef struct { int irq; uint8_t prio; int grp; + bool nmi; } PendingIrq; =20 struct GICv3CPUState { @@ -172,6 +173,7 @@ struct GICv3CPUState { uint32_t gicr_ienabler0; uint32_t gicr_ipendr0; uint32_t gicr_iactiver0; + uint32_t gicr_inmir0; uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */ uint32_t gicr_igrpmodr0; uint32_t gicr_nsacr; @@ -275,6 +277,7 @@ struct GICv3State { GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */ GIC_DECLARE_BITMAP(level); /* Current level */ GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */ + GIC_DECLARE_BITMAP(nmi); /* GICD_INMIR */ uint8_t gicd_ipriority[GICV3_MAXIRQ]; uint64_t gicd_irouter[GICV3_MAXIRQ]; /* Cached information: pointer to the cpu i/f for the CPUs specified @@ -314,6 +317,7 @@ GICV3_BITMAP_ACCESSORS(pending) GICV3_BITMAP_ACCESSORS(active) GICV3_BITMAP_ACCESSORS(level) GICV3_BITMAP_ACCESSORS(edge_trigger) +GICV3_BITMAP_ACCESSORS(nmi) =20 #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common" typedef struct ARMGICv3CommonClass ARMGICv3CommonClass; diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 2d2cea6858a..9810558b076 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -164,6 +164,24 @@ const VMStateDescription vmstate_gicv3_gicv4 =3D { } }; =20 +static bool gicv3_cpu_nmi_needed(void *opaque) +{ + GICv3CPUState *cs =3D opaque; + + return cs->gic->nmi_support; +} + +static const VMStateDescription vmstate_gicv3_cpu_nmi =3D { + .name =3D "arm_gicv3_cpu/nmi", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D gicv3_cpu_nmi_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(gicr_inmir0, GICv3CPUState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_gicv3_cpu =3D { .name =3D "arm_gicv3_cpu", .version_id =3D 1, @@ -196,6 +214,7 @@ static const VMStateDescription vmstate_gicv3_cpu =3D { &vmstate_gicv3_cpu_virt, &vmstate_gicv3_cpu_sre_el1, &vmstate_gicv3_gicv4, + &vmstate_gicv3_cpu_nmi, NULL } }; @@ -238,6 +257,24 @@ const VMStateDescription vmstate_gicv3_gicd_no_migrati= on_shift_bug =3D { } }; =20 +static bool gicv3_nmi_needed(void *opaque) +{ + GICv3State *cs =3D opaque; + + return cs->nmi_support; +} + +const VMStateDescription vmstate_gicv3_gicd_nmi =3D { + .name =3D "arm_gicv3/gicd_nmi", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D gicv3_nmi_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(nmi, GICv3State, GICV3_BMP_SIZE), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_gicv3 =3D { .name =3D "arm_gicv3", .version_id =3D 1, @@ -266,6 +303,7 @@ static const VMStateDescription vmstate_gicv3 =3D { }, .subsections =3D (const VMStateDescription * const []) { &vmstate_gicv3_gicd_no_migration_shift_bug, + &vmstate_gicv3_gicd_nmi, NULL } }; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041609; x=1714646409; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DvQe61721AEsWn6GQQEObJc/efW7ULaM2R9N/D/TYJk=; b=vYbMW6Qiu5095ujh2HZjvXFN0w2Lz/ybTZ0NWl+J2YghxNep/T+dwOm/VU/Fgr0I+5 cBtiVPckTagSnlF5fGQgSTnlCylj9ndvnmYl7sunutPCF0oLSEmwjN3UOTCTFoSHMOPE PBmkN//AOjrhdPU3V2mQmttfxGVBmDXZmvWyYJa5+LexUFB9q8lxxxE9BLwkBShpZejt GMI8XRbt2sa1NaQtP4VqYihHCH7b8mb8P5XLC4eyoSUCIignK0deegn4qW3eiZ/rH06C lxCYN0MipKUwalTGr0WzdU57UVTq7X1BzPOkqfa2WHOwZax/ff4ZvceUAXzBp5saY4KG uNbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041609; x=1714646409; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DvQe61721AEsWn6GQQEObJc/efW7ULaM2R9N/D/TYJk=; b=DzXBENPToZx3tndvM7zZWNNPXhSivRvb0xa0Kdkhwk9chIhhMl62+x8EoNyWAVQxq0 5++mi8pcpAsY5KoOj+k/yHTK6XvcsQMi9IavSR7rOeXKGSe6Wab6sygnEv4xYH/ZPEgj ve1G+aIh0S0W/7W1x5Rf3evi3WykK+Tx/D9JPTtjtBcZ04NUdj2KXbXVGqzJsU/GuNP0 0BAlSJP3Sdrx4b/XSPwLUyb2bGl6+zkeKTPOn8PgqK08MeVZLqJpP5Tn4olwAS8OBcWv 7w2vkTeEeXZHaaA8Ypo/v9fm1CYt8Qvv4hD9vvHHe0NvgdiU66MTDA5CMNjusLQ4vBIQ Bc7g== X-Gm-Message-State: AOJu0YwOZ9HlXbVtxUPVHmlT9GcODwvnli9muLJT9Vj2IqBO6WTV5cC5 L5dlaKnZ9TSfzhOaCQ1bRtxuKlfnAHPsR2KtG+JZ1fLhxA/CJ83tRWLoMBUioGshY6AOgH2xuXb b X-Google-Smtp-Source: AGHT+IH5HQANwqW9fekI1HIEGcO7jOSObUrwEDo5M+6S3eM//Pve6m7YkrTHkn3ScTpjW2ZHSwrVtw== X-Received: by 2002:a05:600c:4f53:b0:418:c2af:ab83 with SMTP id m19-20020a05600c4f5300b00418c2afab83mr4660298wmq.36.1714041608817; Thu, 25 Apr 2024 03:40:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/37] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0 Date: Thu, 25 Apr 2024 11:39:37 +0100 Message-Id: <20240425103958.3237225-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041998008100022 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan Add GICR_INMIR0 register and support access GICR_INMIR0. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-17-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- hw/intc/gicv3_internal.h | 1 + hw/intc/arm_gicv3_redist.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 8f4ebed2f42..21697ecf391 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -110,6 +110,7 @@ #define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04) #define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00) #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) +#define GICR_INMIR0 (GICR_SGI_OFFSET + 0x0F80) =20 /* VLPI redistributor registers, offsets from VLPI_base */ #define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 8153525849a..ed1f9d1e444 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -35,6 +35,15 @@ static int gicr_ns_access(GICv3CPUState *cs, int irq) return extract32(cs->gicr_nsacr, irq * 2, 2); } =20 +static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, + uint32_t *reg, uint32_t val) +{ + /* Helper routine to implement writing to a "set" register */ + val &=3D mask_group(cs, attrs); + *reg =3D val; + gicv3_redist_update(cs); +} + static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, uint32_t *reg, uint32_t val) { @@ -406,6 +415,10 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwadd= r offset, *data =3D value; return MEMTX_OK; } + case GICR_INMIR0: + *data =3D cs->gic->nmi_support ? + gicr_read_bitmap_reg(cs, attrs, cs->gicr_inmir0) : 0; + return MEMTX_OK; case GICR_ICFGR0: case GICR_ICFGR1: { @@ -555,6 +568,12 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwad= dr offset, gicv3_redist_update(cs); return MEMTX_OK; } + case GICR_INMIR0: + if (cs->gic->nmi_support) { + gicr_write_bitmap_reg(cs, attrs, &cs->gicr_inmir0, value); + } + return MEMTX_OK; + case GICR_ICFGR0: /* Register is all RAZ/WI or RAO/WI bits */ return MEMTX_OK; --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041996; cv=none; d=zohomail.com; s=zohoarc; b=lx9JnF5JC6Cr2cHb8i9UT0cT6PJgAYOm2AA6LQ07uFUUe59LmlbPwRKugWwxdJUleMznfpnthsyngnfDxQNyhordIhxBPU7w41b6rbNVQZbVUGDchhCV1cqYNbRi3OFNpFYzkkVpdLtTHqqB/Q4wC19xA9PapbCLiqIIYQUMwwU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041996; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=De3r6CnTq/eiBsjvjQ7Zn0Ov4u78G8vvXoWo+x3RBXE=; b=mzHaH/rOnqMXiAM56iEy0R0yIjybTepZhgzGwJN+wNzyQh6zaX1dApj7OZesqnCKiCZMgA1kkUyByhDXFC5Lg92P6/uyq/xof/Ov5FbdCVAuZHSBlSODFW8MakyBbsMQVR0V/HdDjHfzxO9sXx6zg8/A+uGSQBjGGj3n9Q0AFw8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041996495169.64910061695002; Thu, 25 Apr 2024 03:46:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWY-00023f-PV; Thu, 25 Apr 2024 06:40:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWS-00020e-Uw for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:13 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWQ-0007C9-S8 for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:12 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-41b5dc5e037so1724445e9.3 for ; Thu, 25 Apr 2024 03:40:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041609; x=1714646409; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=De3r6CnTq/eiBsjvjQ7Zn0Ov4u78G8vvXoWo+x3RBXE=; b=yPbljEArm5kepYpBiZ6woyadoBEtdu0Cyi1cJ8sXV/doOTpc9omSUoJknYXWFbKhC2 kjx9b7cjEea8hF2ATbvpACYFVQoD5loRfP8yqbHeffNwIgmb3yNg8lwAy5RMM8/XYRtT UkqzJ6sesFo9lq/Y+dpVAaIBXitb2zbLT732Fk/EF1a20q/E1xcipsf9p8qh7M2Z/enC pDFZnaPPuCC7cDXdKfQDsWKE+y5OQyKxHQZdb5DEyL9iR7HNH0fUMBkRFUprPY6yb4VI kcA2G49ITIoIrPoDsimjNpUrTJOavB1jL/YUdXwBg/n/9CQ7a4KFPUT/50sVNIEDmzWc yU4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041609; x=1714646409; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=De3r6CnTq/eiBsjvjQ7Zn0Ov4u78G8vvXoWo+x3RBXE=; b=S/bGo2Q6w0BBmTiUZzCBBMgkaowL15ChuXhQw+3rR7l8YxkMe1hDRGmZnksFKnptvD CvthRjySGnY67KT3N4z8sT445Bd5CGjAmX61xMyV/Qd/GmeIgXtqu3BmFLS2r9M3am0x e0MbL6O1y4xxzmEubh24jOYz8GaN71AJ97wCO0XFCOHulS4Im+9qWxyNpH+s+1z8wD85 7vZySnN2GIinalfOu/UUJPDlkuryk8jwKwD9XviSES+B0VVMC48uG8e5mKJoKSCpge2g gvfqdI8bsrw4J3Uj2xMgkv8JBWtSDAE6ZhySfD/Zp1qaVc8wh1L3r0m8ZCREyyDpYCJa m0Cg== X-Gm-Message-State: AOJu0Yw4JW8yWy5N+d0uL6/w266xXvMPZD7sGFnMf+ec3kug66kqUVh0 g9Ow0i6TyIDsWvWH9677GQ24icKa2FfxeEkC0JBatsCTfjIUQbgtkE37pohD0dVB/kdjrlyCiWu j X-Google-Smtp-Source: AGHT+IHQcqLQBfLppF0Lz9RXh+jIFRIu5Jet0yzT/50puhFYBCX3JcTSqbVk2XmhmE7X6fO4Y5+s/g== X-Received: by 2002:a05:600c:4f06:b0:419:d91e:ba41 with SMTP id l6-20020a05600c4f0600b00419d91eba41mr3606300wmq.32.1714041609251; Thu, 25 Apr 2024 03:40:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/37] hw/intc/arm_gicv3: Implement GICD_INMIR Date: Thu, 25 Apr 2024 11:39:38 +0100 Message-Id: <20240425103958.3237225-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041998016100023 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-18-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- hw/intc/gicv3_internal.h | 2 ++ hw/intc/arm_gicv3_dist.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 21697ecf391..8d793243f4e 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -52,6 +52,8 @@ #define GICD_SGIR 0x0F00 #define GICD_CPENDSGIR 0x0F10 #define GICD_SPENDSGIR 0x0F20 +#define GICD_INMIR 0x0F80 +#define GICD_INMIRnE 0x3B00 #define GICD_IROUTER 0x6000 #define GICD_IDREGS 0xFFD0 =20 diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 22ddc0d6661..d8207acb22c 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -89,6 +89,29 @@ static int gicd_ns_access(GICv3State *s, int irq) return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2); } =20 +static void gicd_write_bitmap_reg(GICv3State *s, MemTxAttrs attrs, + uint32_t *bmp, maskfn *maskfn, + int offset, uint32_t val) +{ + /* + * Helper routine to implement writing to a "set" register + * (GICD_INMIR, etc). + * Semantics implemented here: + * RAZ/WI for SGIs, PPIs, unimplemented IRQs + * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. + * offset should be the offset in bytes of the register from the start + * of its group. + */ + int irq =3D offset * 8; + + if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { + return; + } + val &=3D mask_group_and_nsacr(s, attrs, maskfn, irq); + *gic_bmp_ptr32(bmp, irq) =3D val; + gicv3_update(s, irq, 32); +} + static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs, uint32_t *bmp, maskfn *maskfn, @@ -545,6 +568,11 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, /* RAZ/WI since affinity routing is always enabled */ *data =3D 0; return true; + case GICD_INMIR ... GICD_INMIR + 0x7f: + *data =3D (!s->nmi_support) ? 0 : + gicd_read_bitmap_reg(s, attrs, s->nmi, NULL, + offset - GICD_INMIR); + return true; case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: { uint64_t r; @@ -754,6 +782,12 @@ static bool gicd_writel(GICv3State *s, hwaddr offset, case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: /* RAZ/WI since affinity routing is always enabled */ return true; + case GICD_INMIR ... GICD_INMIR + 0x7f: + if (s->nmi_support) { + gicd_write_bitmap_reg(s, attrs, s->nmi, NULL, + offset - GICD_INMIR, value); + } + return true; case GICD_IROUTER ... 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041610; x=1714646410; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5htmrfELNsneNGmKSlA9Gw3MrpMWp51ddAIN8u/Ht+I=; b=fHjfoLlJ6VmFd+f7YYcXbpXo4yzltqDDOrpGJPMrDSOm5gbUsv/hhiB287NGvyWS4h m/VtjBe7RTrC/EZ5oO5WUhV/cu2c+4ARCLdUgUpoO6nn4NtV6V2ToxR382j4/wYtCzgi S0BBXfNOEyg4vlEDI3QjUkrE0ta3qAKE211poNgDbKvWJPnm7l1eUNJom6CZP8sKK39p YK4FyGCRnrLphBRLay1c4/Y32XKEg6s9zWgz5YEKmp1m3N/otEP9O4MXb6ovJSmFVjo0 oCe2ZqiEhFwaKaQxpt03G6RiKGt5vBj9sPOUBOLG7uBesx4I9LeSm59hGCKPbXlMZ2ZO gtXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041610; x=1714646410; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5htmrfELNsneNGmKSlA9Gw3MrpMWp51ddAIN8u/Ht+I=; b=pLMmg36ve7OnM9YODfPmeTg3Q6fOldhNRnM2CjD/5BnI0sc8awUMrEqwfpBvg7I09C AQvaEztnKBgt8dGK05NChbl9cRxKJk6S9f1ws2OGapVWeIEuOkAQkGW5Huh4q/qVFK1I yBEo+jEt8YsNAZwWSQyHJ9B78NVcIt8wK8goYYW54r4+CBlRu6P/QHQWAVB/iYK3fSKn HZofy17RyyiWnD3/VrZDPGO4TsQJ9be4j4SBh4NP5fYQ/7HI0SMiS6sYcgmC1920B000 Kb2MG5Ho8TwPT8gf4eOeoGukASTKny2csrLpw52gZv43Kjz9RrjzCwx/JtmzNe3x/Ggb s6iA== X-Gm-Message-State: AOJu0Yzu8QPaLX7q05Kc5Jto/PnCkfEpMBWwZqPLfCa7PdzCA12aCt07 y0hu64Tz2AqJGAy+a7UwXRQO0Lx4KJn5sd52UuWnmtV7dx2oAbQS3ayVldWNsfhppT9MWrkNx7V + X-Google-Smtp-Source: AGHT+IFpL9BbEaWGLc7yKR43/3QXGzuhaK2TZi+hpvPDbAvwOTKYOM+zSEaLets4DNgtonIQG1rUFw== X-Received: by 2002:a05:651c:102a:b0:2d4:9fbe:b5f with SMTP id w10-20020a05651c102a00b002d49fbe0b5fmr3635838ljm.36.1714041609722; Thu, 25 Apr 2024 03:40:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/37] hw/intc/arm_gicv3: Add NMI handling CPU interface registers Date: Thu, 25 Apr 2024 11:39:39 +0100 Message-Id: <20240425103958.3237225-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041883720100003 Content-Type: text/plain; charset="utf-8" Add the NMIAR CPU interface registers which deal with acknowledging NMI. When introduce NMI interrupt, there are some updates to the semantics for t= he register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it should return 1022 if the intid has non-maskable property. And for ICC_NMIAR1_EL1 register, it should return 1023 if the intid do not have non-maskable property. Howerever, these are not necessary for ICC_HPPIR1_EL1 register. And the APR and RPR has NMI bits which should be handled correctly. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson [PMM: Separate out whether cpuif supports NMI from whether the GIC proper (IRI) supports NMI] Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-19-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- hw/intc/gicv3_internal.h | 5 + include/hw/intc/arm_gicv3_common.h | 7 ++ hw/intc/arm_gicv3_cpuif.c | 147 ++++++++++++++++++++++++++++- hw/intc/trace-events | 1 + 4 files changed, 155 insertions(+), 5 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 8d793243f4e..81200eb90e3 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -194,6 +194,10 @@ FIELD(GICR_VPENDBASER, VALID, 63, 1) #define ICC_CTLR_EL3_A3V (1U << 15) #define ICC_CTLR_EL3_NDS (1U << 17) =20 +#define ICC_AP1R_EL1_NMI (1ULL << 63) +#define ICC_RPR_EL1_NSNMI (1ULL << 62) +#define ICC_RPR_EL1_NMI (1ULL << 63) + #define ICH_VMCR_EL2_VENG0_SHIFT 0 #define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT) #define ICH_VMCR_EL2_VENG1_SHIFT 1 @@ -511,6 +515,7 @@ FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH) /* Special interrupt IDs */ #define INTID_SECURE 1020 #define INTID_NONSECURE 1021 +#define INTID_NMI 1022 #define INTID_SPURIOUS 1023 =20 /* Functions internal to the emulated GICv3 */ diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 88533749ebb..cd09bee3bc4 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -225,6 +225,13 @@ struct GICv3CPUState { =20 /* This is temporary working state, to avoid a malloc in gicv3_update(= ) */ bool seenbetter; + + /* + * Whether the CPU interface has NMI support (FEAT_GICv3_NMI). The + * CPU interface may support NMIs even when the GIC proper (what the + * spec calls the IRI; the redistributors and distributor) does not. + */ + bool nmi_support; }; =20 /* diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 67d8fd07b7f..715909d0f7d 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -21,6 +21,7 @@ #include "hw/irq.h" #include "cpu.h" #include "target/arm/cpregs.h" +#include "target/arm/cpu-features.h" #include "sysemu/tcg.h" #include "sysemu/qtest.h" =20 @@ -795,6 +796,13 @@ static uint64_t icv_iar_read(CPUARMState *env, const A= RMCPRegInfo *ri) return intid; } =20 +static uint64_t icv_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* todo */ + uint64_t intid =3D INTID_SPURIOUS; + return intid; +} + static uint32_t icc_fullprio_mask(GICv3CPUState *cs) { /* @@ -832,6 +840,23 @@ static int icc_highest_active_prio(GICv3CPUState *cs) */ int i; =20 + if (cs->nmi_support) { + /* + * If an NMI is active this takes precedence over anything else + * for priority purposes; the NMI bit is only in the AP1R0 bit. + * We return here the effective priority of the NMI, which is + * either 0x0 or 0x80. Callers will need to check NMI again for + * purposes of either setting the RPR register bits or for + * prioritization of NMI vs non-NMI. + */ + if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) { + return 0; + } + if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { + return (cs->gic->gicd_ctlr & GICD_CTLR_DS) ? 0 : 0x80; + } + } + for (i =3D 0; i < icc_num_aprs(cs); i++) { uint32_t apr =3D cs->icc_apr[GICV3_G0][i] | cs->icc_apr[GICV3_G1][i] | cs->icc_apr[GICV3_G1NS][i]; @@ -898,12 +923,24 @@ static bool icc_hppi_can_preempt(GICv3CPUState *cs) */ int rprio; uint32_t mask; + ARMCPU *cpu =3D ARM_CPU(cs->cpu); + CPUARMState *env =3D &cpu->env; =20 if (icc_no_enabled_hppi(cs)) { return false; } =20 - if (cs->hppi.prio >=3D cs->icc_pmr_el1) { + if (cs->hppi.nmi) { + if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && + cs->hppi.grp =3D=3D GICV3_G1NS) { + if (cs->icc_pmr_el1 < 0x80) { + return false; + } + if (arm_is_secure(env) && cs->icc_pmr_el1 =3D=3D 0x80) { + return false; + } + } + } else if (cs->hppi.prio >=3D cs->icc_pmr_el1) { /* Priority mask masks this interrupt */ return false; } @@ -923,6 +960,12 @@ static bool icc_hppi_can_preempt(GICv3CPUState *cs) return true; } =20 + if (cs->hppi.nmi && (cs->hppi.prio & mask) =3D=3D (rprio & mask)) { + if (!(cs->icc_apr[cs->hppi.grp][0] & ICC_AP1R_EL1_NMI)) { + return true; + } + } + return false; } =20 @@ -1044,8 +1087,13 @@ static void icc_activate_irq(GICv3CPUState *cs, int = irq) int aprbit =3D prio >> (8 - cs->prebits); int regno =3D aprbit / 32; int regbit =3D aprbit % 32; + bool nmi =3D cs->hppi.nmi; =20 - cs->icc_apr[cs->hppi.grp][regno] |=3D (1 << regbit); + if (nmi) { + cs->icc_apr[cs->hppi.grp][regno] |=3D ICC_AP1R_EL1_NMI; + } else { + cs->icc_apr[cs->hppi.grp][regno] |=3D (1 << regbit); + } =20 if (irq < GIC_INTERNAL) { cs->gicr_iactiver0 =3D deposit32(cs->gicr_iactiver0, irq, 1, 1); @@ -1159,6 +1207,7 @@ static uint64_t icc_iar0_read(CPUARMState *env, const= ARMCPRegInfo *ri) static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri) { GICv3CPUState *cs =3D icc_cs_from_env(env); + int el =3D arm_current_el(env); uint64_t intid; =20 if (icv_access(env, HCR_IMO)) { @@ -1172,13 +1221,44 @@ static uint64_t icc_iar1_read(CPUARMState *env, con= st ARMCPRegInfo *ri) } =20 if (!gicv3_intid_is_special(intid)) { - icc_activate_irq(cs, intid); + if (cs->hppi.nmi && env->cp15.sctlr_el[el] & SCTLR_NMI) { + intid =3D INTID_NMI; + } else { + icc_activate_irq(cs, intid); + } } =20 trace_gicv3_icc_iar1_read(gicv3_redist_affid(cs), intid); return intid; } =20 +static uint64_t icc_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + GICv3CPUState *cs =3D icc_cs_from_env(env); + uint64_t intid; + + if (icv_access(env, HCR_IMO)) { + return icv_nmiar1_read(env, ri); + } + + if (!icc_hppi_can_preempt(cs)) { + intid =3D INTID_SPURIOUS; + } else { + intid =3D icc_hppir1_value(cs, env); + } + + if (!gicv3_intid_is_special(intid)) { + if (!cs->hppi.nmi) { + intid =3D INTID_SPURIOUS; + } else { + icc_activate_irq(cs, intid); + } + } + + trace_gicv3_icc_nmiar1_read(gicv3_redist_affid(cs), intid); + return intid; +} + static void icc_drop_prio(GICv3CPUState *cs, int grp) { /* Drop the priority of the currently active interrupt in @@ -1205,6 +1285,12 @@ static void icc_drop_prio(GICv3CPUState *cs, int grp) if (!*papr) { continue; } + + if (i =3D=3D 0 && cs->nmi_support && (*papr & ICC_AP1R_EL1_NMI)) { + *papr &=3D (~ICC_AP1R_EL1_NMI); + break; + } + /* Clear the lowest set bit */ *papr &=3D *papr - 1; break; @@ -1239,6 +1325,15 @@ static int icc_highest_active_group(GICv3CPUState *c= s) */ int i; =20 + if (cs->nmi_support) { + if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) { + return GICV3_G1; + } + if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { + return GICV3_G1NS; + } + } + for (i =3D 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) { int g0ctz =3D ctz32(cs->icc_apr[GICV3_G0][i]); int g1ctz =3D ctz32(cs->icc_apr[GICV3_G1][i]); @@ -1693,7 +1788,11 @@ static void icc_ap_write(CPUARMState *env, const ARM= CPRegInfo *ri, return; } =20 - cs->icc_apr[grp][regno] =3D value & 0xFFFFFFFFU; + if (cs->nmi_support) { + cs->icc_apr[grp][regno] =3D value & (0xFFFFFFFFU | ICC_AP1R_EL1_NM= I); + } else { + cs->icc_apr[grp][regno] =3D value & 0xFFFFFFFFU; + } gicv3_cpuif_update(cs); } =20 @@ -1783,7 +1882,7 @@ static void icc_dir_write(CPUARMState *env, const ARM= CPRegInfo *ri, static uint64_t icc_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) { GICv3CPUState *cs =3D icc_cs_from_env(env); - int prio; + uint64_t prio; =20 if (icv_access(env, HCR_FMO | HCR_IMO)) { return icv_rpr_read(env, ri); @@ -1803,6 +1902,22 @@ static uint64_t icc_rpr_read(CPUARMState *env, const= ARMCPRegInfo *ri) } } =20 + if (cs->nmi_support) { + /* NMI info is reported in the high bits of RPR */ + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env)) { + if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { + prio |=3D ICC_RPR_EL1_NMI; + } + } else { + if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { + prio |=3D ICC_RPR_EL1_NSNMI; + } + if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) { + prio |=3D ICC_RPR_EL1_NMI; + } + } + } + trace_gicv3_icc_rpr_read(gicv3_redist_affid(cs), prio); return prio; } @@ -2482,6 +2597,15 @@ static const ARMCPRegInfo gicv3_cpuif_icc_apxr23_reg= info[] =3D { }, }; =20 +static const ARMCPRegInfo gicv3_cpuif_gicv3_nmi_reginfo[] =3D { + { .name =3D "ICC_NMIAR1_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 9, .opc2 =3D 5, + .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .access =3D PL1_R, .accessfn =3D gicv3_irq_access, + .readfn =3D icc_nmiar1_read, + }, +}; + static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) { GICv3CPUState *cs =3D icc_cs_from_env(env); @@ -2838,6 +2962,19 @@ void gicv3_init_cpuif(GICv3State *s) */ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); =20 + /* + * If the CPU implements FEAT_NMI and FEAT_GICv3 it must also + * implement FEAT_GICv3_NMI, which is the CPU interface part + * of NMI support. This is distinct from whether the GIC proper + * (redistributors and distributor) have NMI support. In QEMU + * that is a property of the GIC device in s->nmi_support; + * cs->nmi_support indicates the CPU interface's support. + */ + if (cpu_isar_feature(aa64_nmi, cpu)) { + cs->nmi_support =3D true; + define_arm_cp_regs(cpu, gicv3_cpuif_gicv3_nmi_reginfo); + } + /* * The CPU implementation specifies the number of supported * bits of physical priority. For backwards compatibility diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 1ef29d0256a..94030550d5a 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -116,6 +116,7 @@ gicv3_cpuif_set_irqs(uint32_t cpuid, int fiqlevel, int = irqlevel) "GICv3 CPU i/f gicv3_icc_generate_sgi(uint32_t cpuid, int irq, int irm, uint32_t aff, uin= t32_t targetlist) "GICv3 CPU i/f 0x%x generating SGI %d IRM %d target affin= ity 0x%xxx targetlist 0x%x" gicv3_icc_iar0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR0 read cpu 0= x%x value 0x%" PRIx64 gicv3_icc_iar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR1 read cpu 0= x%x value 0x%" PRIx64 +gicv3_icc_nmiar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_NMIAR1 read c= pu 0x%x value 0x%" PRIx64 gicv3_icc_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_EOIR%= d write cpu 0x%x value 0x%" PRIx64 gicv3_icc_hppir0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR0 read c= pu 0x%x value 0x%" PRIx64 gicv3_icc_hppir1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR1 read c= pu 0x%x value 0x%" PRIx64 --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041832; cv=none; d=zohomail.com; s=zohoarc; b=PVjMN263piVyoa/yu+VvJkEDm/O2oFe0FlI3jCfBcxpcY4hC2u59L/XEMJzY2FLMZz+Qw+nFR9IL3GjFcGD5Jj8igN4HOI7QL5h4G9LKL9nd76zlv45djyPW+hC1U3Pb1+enkoOBbFbqY/ucWHb/d8In+W+8QaKARagUJ4w8zmg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041832; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=XwmIfh7Bnnr9WxqJhGLFJuhVzK85Ho+AZb7h0Ddr584=; b=etr6YCcXCR9rX/WzUqdQD92meq/mOmcgvVd91x6srwgaOtA3g8fsoANNcruDug8Ieo+p0OfT5TsrOmmxtUZnKN8kMWg5879n7cVXKTVg1x5Ar6rELaBgb7x6yUjdKwGJSf35dmfaVeRpmVc2j0uMrZwxDxfVRLToXDkEncbDb0g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041832412957.0951640814078; Thu, 25 Apr 2024 03:43:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWa-00026y-Gk; Thu, 25 Apr 2024 06:40:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWV-00021x-9A for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:15 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWR-0007Ci-TG for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:14 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-34b64b7728cso704470f8f.0 for ; Thu, 25 Apr 2024 03:40:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041610; x=1714646410; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=XwmIfh7Bnnr9WxqJhGLFJuhVzK85Ho+AZb7h0Ddr584=; b=nl8OhEsOy8oJgLY6ZUB0b8Xr49uIO6fefuvNofu+6a1zhwWFRxQEfslDJ4QDumwa9y QUjFLNjFRKCCUIrIL3BYIGU+M4dyYqtprs4h8Z8oq1BykrNALmZb3Q3aWjsjlFaBoI8f C0ufJmDxWOSL3Dz1cg4X13hh0vJZ43aLxxNUlR94kO/xi52irYiQl24+fvQuXeImFYjP +X9hSCBYknEyrpMx5aVPLeJ8FqUM6MzN1ZlwkNLmZhoGkcze9PC7Pb+QYBAowed3UVfW t2y23FVaO8qk62detgG1wFRmMpFU4teTsIQzvOQF+wCppFMpbypu1tPxZHB3i5hWwI+T sc1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041610; x=1714646410; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XwmIfh7Bnnr9WxqJhGLFJuhVzK85Ho+AZb7h0Ddr584=; b=XCRRNCGHKa/KDj/2lLM3HQzBVFgEa/eocxzl8WbD/yBs4WAeeIAhLS7TYoKdbseILC z3IW0MSLcboBJgxUVN1ftwivr77PUFHiirWYfm41HLdPDsVPAX37u7gBIqBbJZpDNRtd 4iIWib5f7sHp16CNC4ZlMztTceHP+FNRrXqIkHiMm0hJy7oT17XkeLnjvqSFJdK7KXTZ CMBcw/OTGuRzfSfgbRv/UQ/WvnUMxU/nRYraptUtP4r7N7wWKdfxCQqBBenaDZhCuZ6z tvGyeMeEJb4X5thJxYdfyiR+gOsC2HNJTQgFTzINbu1jz+wHUsKFWXE5QZMT1xm6ScLR 2BdQ== X-Gm-Message-State: AOJu0YxS8Du/U/6CNE7W0FTmGUrLQTEYGA7trreTWtyB/SH8XSgb7zYe 2xWvdufaUKEImqLPMiWdVSVs9CcWxpXhz9o4ochEUj9LX4sT359wHehfMIU3ctPV0H+G47ZN9b+ X X-Google-Smtp-Source: AGHT+IGk12LX/Up5VpiaR/RUoZFqIDjPlRGn8NpaPJfMyzDD7CnSxrZarab2y/qq6d96KO4SwYKpoQ== X-Received: by 2002:a05:6000:e09:b0:33e:bdea:629e with SMTP id dx9-20020a0560000e0900b0033ebdea629emr3142725wrb.37.1714041610229; Thu, 25 Apr 2024 03:40:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/37] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read() Date: Thu, 25 Apr 2024 11:39:40 +0100 Message-Id: <20240425103958.3237225-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041833605100001 Content-Type: text/plain; charset="utf-8" Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit. If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1= .NMI bit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit should be set or clear according to the Non-maskable property. And the RPR priority should also update the NMI bit according to the APR priority NMI b= it. By the way, add gicv3_icv_nmiar1_read trace event. If the hpp irq is a NMI, the icv iar read should return 1022 and trap for NMI again Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson [PMM: use cs->nmi_support instead of cs->gic->nmi_support] Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-20-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- hw/intc/gicv3_internal.h | 4 ++ hw/intc/arm_gicv3_cpuif.c | 105 +++++++++++++++++++++++++++++++++----- hw/intc/trace-events | 1 + 3 files changed, 98 insertions(+), 12 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 81200eb90e3..bc9f518fe86 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -246,6 +246,7 @@ FIELD(GICR_VPENDBASER, VALID, 63, 1) #define ICH_LR_EL2_PRIORITY_SHIFT 48 #define ICH_LR_EL2_PRIORITY_LENGTH 8 #define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT) +#define ICH_LR_EL2_NMI (1ULL << 59) #define ICH_LR_EL2_GROUP (1ULL << 60) #define ICH_LR_EL2_HW (1ULL << 61) #define ICH_LR_EL2_STATE_SHIFT 62 @@ -277,6 +278,9 @@ FIELD(GICR_VPENDBASER, VALID, 63, 1) #define ICH_VTR_EL2_PREBITS_SHIFT 26 #define ICH_VTR_EL2_PRIBITS_SHIFT 29 =20 +#define ICV_AP1R_EL1_NMI (1ULL << 63) +#define ICV_RPR_EL1_NMI (1ULL << 63) + /* ITS Registers */ =20 FIELD(GITS_BASER, SIZE, 0, 8) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 715909d0f7d..b1f6c16ffef 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -158,6 +158,10 @@ static int ich_highest_active_virt_prio(GICv3CPUState = *cs) int i; int aprmax =3D ich_num_aprs(cs); =20 + if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) { + return 0x0; + } + for (i =3D 0; i < aprmax; i++) { uint32_t apr =3D cs->ich_apr[GICV3_G0][i] | cs->ich_apr[GICV3_G1NS][i]; @@ -192,6 +196,7 @@ static int hppvi_index(GICv3CPUState *cs) * correct behaviour. */ int prio =3D 0xff; + bool nmi =3D false; =20 if (!(cs->ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) { /* Both groups disabled, definitely nothing to do */ @@ -200,6 +205,7 @@ static int hppvi_index(GICv3CPUState *cs) =20 for (i =3D 0; i < cs->num_list_regs; i++) { uint64_t lr =3D cs->ich_lr_el2[i]; + bool thisnmi; int thisprio; =20 if (ich_lr_state(lr) !=3D ICH_LR_EL2_STATE_PENDING) { @@ -218,10 +224,12 @@ static int hppvi_index(GICv3CPUState *cs) } } =20 + thisnmi =3D lr & ICH_LR_EL2_NMI; thisprio =3D ich_lr_prio(lr); =20 - if (thisprio < prio) { + if ((thisprio < prio) || ((thisprio =3D=3D prio) && (thisnmi & (!n= mi)))) { prio =3D thisprio; + nmi =3D thisnmi; idx =3D i; } } @@ -290,6 +298,7 @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uin= t64_t lr) * equivalent of these checks. */ int grp; + bool is_nmi; uint32_t mask, prio, rprio, vpmr; =20 if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) { @@ -302,10 +311,11 @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, u= int64_t lr) */ =20 prio =3D ich_lr_prio(lr); + is_nmi =3D lr & ICH_LR_EL2_NMI; vpmr =3D extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, ICH_VMCR_EL2_VPMR_LENGTH); =20 - if (prio >=3D vpmr) { + if (!is_nmi && prio >=3D vpmr) { /* Priority mask masks this interrupt */ return false; } @@ -327,6 +337,11 @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, ui= nt64_t lr) return true; } =20 + if ((prio & mask) =3D=3D (rprio & mask) && is_nmi && + !(cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI)) { + return true; + } + return false; } =20 @@ -551,7 +566,11 @@ static void icv_ap_write(CPUARMState *env, const ARMCP= RegInfo *ri, =20 trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), v= alue); =20 - cs->ich_apr[grp][regno] =3D value & 0xFFFFFFFFU; + if (cs->nmi_support) { + cs->ich_apr[grp][regno] =3D value & (0xFFFFFFFFU | ICV_AP1R_EL1_NM= I); + } else { + cs->ich_apr[grp][regno] =3D value & 0xFFFFFFFFU; + } =20 gicv3_cpuif_virt_irq_fiq_update(cs); return; @@ -698,7 +717,11 @@ static void icv_ctlr_write(CPUARMState *env, const ARM= CPRegInfo *ri, static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) { GICv3CPUState *cs =3D icc_cs_from_env(env); - int prio =3D ich_highest_active_virt_prio(cs); + uint64_t prio =3D ich_highest_active_virt_prio(cs); + + if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) { + prio |=3D ICV_RPR_EL1_NMI; + } =20 trace_gicv3_icv_rpr_read(gicv3_redist_affid(cs), prio); return prio; @@ -737,13 +760,19 @@ static void icv_activate_irq(GICv3CPUState *cs, int i= dx, int grp) */ uint32_t mask =3D icv_gprio_mask(cs, grp); int prio =3D ich_lr_prio(cs->ich_lr_el2[idx]) & mask; + bool nmi =3D cs->ich_lr_el2[idx] & ICH_LR_EL2_NMI; int aprbit =3D prio >> (8 - cs->vprebits); int regno =3D aprbit / 32; int regbit =3D aprbit % 32; =20 cs->ich_lr_el2[idx] &=3D ~ICH_LR_EL2_STATE_PENDING_BIT; cs->ich_lr_el2[idx] |=3D ICH_LR_EL2_STATE_ACTIVE_BIT; - cs->ich_apr[grp][regno] |=3D (1 << regbit); + + if (nmi) { + cs->ich_apr[grp][regno] |=3D ICV_AP1R_EL1_NMI; + } else { + cs->ich_apr[grp][regno] |=3D (1 << regbit); + } } =20 static void icv_activate_vlpi(GICv3CPUState *cs) @@ -764,6 +793,7 @@ static uint64_t icv_iar_read(CPUARMState *env, const AR= MCPRegInfo *ri) int grp =3D ri->crm =3D=3D 8 ? GICV3_G0 : GICV3_G1NS; int idx =3D hppvi_index(cs); uint64_t intid =3D INTID_SPURIOUS; + int el =3D arm_current_el(env); =20 if (idx =3D=3D HPPVI_INDEX_VLPI) { if (cs->hppvlpi.grp =3D=3D grp && icv_hppvlpi_can_preempt(cs)) { @@ -773,11 +803,16 @@ static uint64_t icv_iar_read(CPUARMState *env, const = ARMCPRegInfo *ri) } else if (idx >=3D 0) { uint64_t lr =3D cs->ich_lr_el2[idx]; int thisgrp =3D (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; + bool nmi =3D env->cp15.sctlr_el[el] & SCTLR_NMI && lr & ICH_LR_EL2= _NMI; =20 if (thisgrp =3D=3D grp && icv_hppi_can_preempt(cs, lr)) { intid =3D ich_lr_vintid(lr); if (!gicv3_intid_is_special(intid)) { - icv_activate_irq(cs, idx, grp); + if (!nmi) { + icv_activate_irq(cs, idx, grp); + } else { + intid =3D INTID_NMI; + } } else { /* Interrupt goes from Pending to Invalid */ cs->ich_lr_el2[idx] &=3D ~ICH_LR_EL2_STATE_PENDING_BIT; @@ -798,8 +833,37 @@ static uint64_t icv_iar_read(CPUARMState *env, const A= RMCPRegInfo *ri) =20 static uint64_t icv_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri) { - /* todo */ + GICv3CPUState *cs =3D icc_cs_from_env(env); + int idx =3D hppvi_index(cs); uint64_t intid =3D INTID_SPURIOUS; + + if (idx >=3D 0 && idx !=3D HPPVI_INDEX_VLPI) { + uint64_t lr =3D cs->ich_lr_el2[idx]; + int thisgrp =3D (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; + + if ((thisgrp =3D=3D GICV3_G1NS) && icv_hppi_can_preempt(cs, lr)) { + intid =3D ich_lr_vintid(lr); + if (!gicv3_intid_is_special(intid)) { + if (lr & ICH_LR_EL2_NMI) { + icv_activate_irq(cs, idx, GICV3_G1NS); + } else { + intid =3D INTID_SPURIOUS; + } + } else { + /* Interrupt goes from Pending to Invalid */ + cs->ich_lr_el2[idx] &=3D ~ICH_LR_EL2_STATE_PENDING_BIT; + /* + * We will now return the (bogus) ID from the list registe= r, + * as per the pseudocode. + */ + } + } + } + + trace_gicv3_icv_nmiar1_read(gicv3_redist_affid(cs), intid); + + gicv3_cpuif_virt_update(cs); + return intid; } =20 @@ -1424,7 +1488,7 @@ static void icv_increment_eoicount(GICv3CPUState *cs) ICH_HCR_EL2_EOICOUNT_LENGTH, eoicount + 1); } =20 -static int icv_drop_prio(GICv3CPUState *cs) +static int icv_drop_prio(GICv3CPUState *cs, bool *nmi) { /* Drop the priority of the currently active virtual interrupt * (favouring group 0 if there is a set active bit at @@ -1446,6 +1510,12 @@ static int icv_drop_prio(GICv3CPUState *cs) continue; } =20 + if (i =3D=3D 0 && cs->nmi_support && (*papr1 & ICV_AP1R_EL1_NMI)) { + *papr1 &=3D (~ICV_AP1R_EL1_NMI); + *nmi =3D true; + return 0xff; + } + /* We can't just use the bit-twiddling hack icc_drop_prio() does * because we need to return the bit number we cleared so * it can be compared against the list register's priority field. @@ -1505,6 +1575,7 @@ static void icv_eoir_write(CPUARMState *env, const AR= MCPRegInfo *ri, int irq =3D value & 0xffffff; int grp =3D ri->crm =3D=3D 8 ? GICV3_G0 : GICV3_G1NS; int idx, dropprio; + bool nmi =3D false; =20 trace_gicv3_icv_eoir_write(ri->crm =3D=3D 8 ? 0 : 1, gicv3_redist_affid(cs), value); @@ -1517,8 +1588,8 @@ static void icv_eoir_write(CPUARMState *env, const AR= MCPRegInfo *ri, * error checks" (because that lets us avoid scanning the AP * registers twice). */ - dropprio =3D icv_drop_prio(cs); - if (dropprio =3D=3D 0xff) { + dropprio =3D icv_drop_prio(cs, &nmi); + if (dropprio =3D=3D 0xff && !nmi) { /* No active interrupt. It is CONSTRAINED UNPREDICTABLE * whether the list registers are checked in this * situation; we choose not to. @@ -1540,8 +1611,9 @@ static void icv_eoir_write(CPUARMState *env, const AR= MCPRegInfo *ri, uint64_t lr =3D cs->ich_lr_el2[idx]; int thisgrp =3D (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; int lr_gprio =3D ich_lr_prio(lr) & icv_gprio_mask(cs, grp); + bool thisnmi =3D lr & ICH_LR_EL2_NMI; =20 - if (thisgrp =3D=3D grp && lr_gprio =3D=3D dropprio) { + if (thisgrp =3D=3D grp && (lr_gprio =3D=3D dropprio || (thisnmi & = nmi))) { if (!icv_eoi_split(env, cs) || irq >=3D GICV3_LPI_INTID_START)= { /* * Priority drop and deactivate not split: deactivate irq = now. @@ -2627,7 +2699,11 @@ static void ich_ap_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), v= alue); =20 - cs->ich_apr[grp][regno] =3D value & 0xFFFFFFFFU; + if (cs->nmi_support) { + cs->ich_apr[grp][regno] =3D value & (0xFFFFFFFFU | ICV_AP1R_EL1_NM= I); + } else { + cs->ich_apr[grp][regno] =3D value & 0xFFFFFFFFU; + } gicv3_cpuif_virt_irq_fiq_update(cs); } =20 @@ -2744,6 +2820,11 @@ static void ich_lr_write(CPUARMState *env, const ARM= CPRegInfo *ri, 8 - cs->vpribits, 0); } =20 + /* Enforce RES0 bit in NMI field when FEAT_GICv3_NMI is not implemente= d */ + if (!cs->nmi_support) { + value &=3D ~ICH_LR_EL2_NMI; + } + cs->ich_lr_el2[regno] =3D value; gicv3_cpuif_virt_update(cs); } diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 94030550d5a..47340b5bc13 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -152,6 +152,7 @@ gicv3_icv_rpr_read(uint32_t cpu, uint64_t val) "GICv3 I= CV_RPR read cpu 0x%x valu gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR= %d read cpu 0x%x value 0x%" PRIx64 gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu 0= x%x value 0x%" PRIx64 gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d r= ead cpu 0x%x value 0x%" PRIx64 +gicv3_icv_nmiar1_read(uint32_t cpu, uint64_t val) "GICv3 ICV_NMIAR1 read c= pu 0x%x value 0x%" PRIx64 gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%= d write cpu 0x%x value 0x%" PRIx64 gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int hppvlpi, int grp, int= prio) "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d grp %d p= rio %d" gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GIC= v3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d" --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041705; cv=none; d=zohomail.com; s=zohoarc; b=OH9cBl3n6sBPs4U/WvGlkzrT59qYeIB8rx7O/EDwKqgZxNi07MxQ6va+JWL2zGXg0hJZuzHhc2Bu0bIS7R7yqw9JgTxE2IwURkeUSNei50OGC+yFKRlhIkVWOP0mwnUoinxg+A82IQVC34CYoADx6enrSpd9Dz9Wlue14mL+gGo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041705; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=TcVIi1Iki/Qk61vaJOYOc4vy8G4AM5CFxMYdxYS702I=; b=UlSjjxlGSSAT29NyXlkf2Vh3/2YYWBkzl+JYpchBAJcnZcPJ1BC7EQBWTaLGlbuB6rEP66nV2JQgHvSKjNw2XRnsH/OSj+tdUp+FGP0mpxW7FXsjALjKRP7JvxOJQCSQz4BkRs/ob9P/vidK8cb0IJLu+gOhSg9vEBcQyOfwMS0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041705269356.6103570504497; Thu, 25 Apr 2024 03:41:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWc-0002Gz-N2; Thu, 25 Apr 2024 06:40:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWV-00021v-6r for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:15 -0400 Received: from mail-lj1-x232.google.com ([2a00:1450:4864:20::232]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWS-0007Cu-FZ for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:14 -0400 Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2ddc2ea2091so7426381fa.1 for ; Thu, 25 Apr 2024 03:40:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041611; x=1714646411; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TcVIi1Iki/Qk61vaJOYOc4vy8G4AM5CFxMYdxYS702I=; b=P+5csmjlMROUsDSESrcVVFNoB0E+N0bEwrfZ43vy0RQEGzNtUG1Uv0cFOjCTM+E+1t AQdgLqEuPkS64gpyxEVXbzxZA70D6FvMvl3nGXkEUtvKS94m2s9dQqbsSQa+XTbtD5sg dCa6HT3IEiMhekPWEd1P2NsjrjSbnaN8V8CTblHhY+Mbv+aRFXBmuGofoZXNTbfxait2 bbHwboDVraVeglNSnSuICcSqclOIVMsy5g4u4cOLN2pC6pNCspzM3E2VwVR1EznThIPq s6XcapzDGO69MDIYE1dXuh07PY4unP07f2cVpXt6q+iGi9SADKF5cnHevyGkyaq2wG1I MEBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041611; x=1714646411; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TcVIi1Iki/Qk61vaJOYOc4vy8G4AM5CFxMYdxYS702I=; b=cNNymXMoChNyO0ineBUD9Bt9NdMdLKYpdA+Gg/lPqm+ECIBwIvLv8BO5B5KAWzdhGh kEhHy0JhTEGXek6M8YOpm+2mhjeYJMSKpmnzUzxmJM9jnUtX5S5fW8H0QTSLCIijnjYm 3Ovj8tmL7d8hilX0MyPKRqdlYui9GPGuayQqPAFUnUCxqsEktwOudMIHGMmsNw1bnf1O DmkJLvk3YGqPAADr4MN0tphA3/Z26y6ySxfvofC2jCGSbqGPfGvdM9x5PlG+ZkL/LdxB yGpLIj+CfajQGCL3/k1wn/JmQWtEyhVyVWJU9SiymoBzYQfayC95lfsMc0NkmLLMQZxs 6HaA== X-Gm-Message-State: AOJu0YxDDSjC01Q66QBwVzdZxfKwRWgBN4bl8RB+NR9Num+mValhEjuu GK6XkgebNC5AcJ/xjKVOClQmklURCQF+V8E5DW7gbpldbY7UN+3ELsvofd0O2Gx1fj+7QWsRIwy N X-Google-Smtp-Source: AGHT+IEXtggfNVRWgg18ufH+640YVZHhUbKX20Jfm1rsiqKcXMaZ2Nn7ovev3rqMClavSXPA9GXYnw== X-Received: by 2002:a2e:8846:0:b0:2d4:1fa4:9eb8 with SMTP id z6-20020a2e8846000000b002d41fa49eb8mr3636830ljj.40.1714041610725; Thu, 25 Apr 2024 03:40:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/37] hw/intc/arm_gicv3: Implement NMI interrupt priority Date: Thu, 25 Apr 2024 11:39:41 +0100 Message-Id: <20240425103958.3237225-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041707219100003 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI priority is higher than 0x80, otherwise it is higher than 0x0. And save the interrupt non-maskable property in hppi.nmi to deliver NMI exception. Since both GICR and GICD can deliver NMI, it is both necessary to check whether the pending irq is NMI in gicv3_redist_update_noirqset and gicv3_update_noirqset. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-21-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3.c | 67 +++++++++++++++++++++++++++++++++----- hw/intc/arm_gicv3_common.c | 3 ++ hw/intc/arm_gicv3_redist.c | 3 ++ 3 files changed, 64 insertions(+), 9 deletions(-) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 0b8f79a1227..58e18fff54f 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -21,7 +21,7 @@ #include "hw/intc/arm_gicv3.h" #include "gicv3_internal.h" =20 -static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio) +static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio, bool nmi) { /* Return true if this IRQ at this priority should take * precedence over the current recorded highest priority @@ -30,14 +30,23 @@ static bool irqbetter(GICv3CPUState *cs, int irq, uint8= _t prio) * is the same as this one (a property which the calling code * relies on). */ - if (prio < cs->hppi.prio) { - return true; + if (prio !=3D cs->hppi.prio) { + return prio < cs->hppi.prio; } + + /* + * The same priority IRQ with non-maskable property should signal to + * the CPU as it have the priority higher than the labelled 0x80 or 0x= 00. + */ + if (nmi !=3D cs->hppi.nmi) { + return nmi; + } + /* If multiple pending interrupts have the same priority then it is an * IMPDEF choice which of them to signal to the CPU. We choose to * signal the one with the lowest interrupt number. */ - if (prio =3D=3D cs->hppi.prio && irq <=3D cs->hppi.irq) { + if (irq <=3D cs->hppi.irq) { return true; } return false; @@ -129,6 +138,40 @@ static uint32_t gicr_int_pending(GICv3CPUState *cs) return pend; } =20 +static bool gicv3_get_priority(GICv3CPUState *cs, bool is_redist, int irq, + uint8_t *prio) +{ + uint32_t nmi =3D 0x0; + + if (is_redist) { + nmi =3D extract32(cs->gicr_inmir0, irq, 1); + } else { + nmi =3D *gic_bmp_ptr32(cs->gic->nmi, irq); + nmi =3D nmi & (1 << (irq & 0x1f)); + } + + if (nmi) { + /* DS =3D 0 & Non-secure NMI */ + if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && + ((is_redist && extract32(cs->gicr_igroupr0, irq, 1)) || + (!is_redist && gicv3_gicd_group_test(cs->gic, irq)))) { + *prio =3D 0x80; + } else { + *prio =3D 0x0; + } + + return true; + } + + if (is_redist) { + *prio =3D cs->gicr_ipriorityr[irq]; + } else { + *prio =3D cs->gic->gicd_ipriority[irq]; + } + + return false; +} + /* Update the interrupt status after state in a redistributor * or CPU interface has changed, but don't tell the CPU i/f. */ @@ -141,6 +184,7 @@ static void gicv3_redist_update_noirqset(GICv3CPUState = *cs) uint8_t prio; int i; uint32_t pend; + bool nmi =3D false; =20 /* Find out which redistributor interrupts are eligible to be * signaled to the CPU interface. @@ -152,10 +196,11 @@ static void gicv3_redist_update_noirqset(GICv3CPUStat= e *cs) if (!(pend & (1 << i))) { continue; } - prio =3D cs->gicr_ipriorityr[i]; - if (irqbetter(cs, i, prio)) { + nmi =3D gicv3_get_priority(cs, true, i, &prio); + if (irqbetter(cs, i, prio, nmi)) { cs->hppi.irq =3D i; cs->hppi.prio =3D prio; + cs->hppi.nmi =3D nmi; seenbetter =3D true; } } @@ -168,9 +213,10 @@ static void gicv3_redist_update_noirqset(GICv3CPUState= *cs) if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable && (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) && (cs->hpplpi.prio !=3D 0xff)) { - if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) { + if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio, cs->hpplpi.nmi)= ) { cs->hppi.irq =3D cs->hpplpi.irq; cs->hppi.prio =3D cs->hpplpi.prio; + cs->hppi.nmi =3D cs->hpplpi.nmi; cs->hppi.grp =3D cs->hpplpi.grp; seenbetter =3D true; } @@ -213,6 +259,7 @@ static void gicv3_update_noirqset(GICv3State *s, int st= art, int len) int i; uint8_t prio; uint32_t pend =3D 0; + bool nmi =3D false; =20 assert(start >=3D GIC_INTERNAL); assert(len > 0); @@ -240,10 +287,11 @@ static void gicv3_update_noirqset(GICv3State *s, int = start, int len) */ continue; } - prio =3D s->gicd_ipriority[i]; - if (irqbetter(cs, i, prio)) { + nmi =3D gicv3_get_priority(cs, false, i, &prio); + if (irqbetter(cs, i, prio, nmi)) { cs->hppi.irq =3D i; cs->hppi.prio =3D prio; + cs->hppi.nmi =3D nmi; cs->seenbetter =3D true; } } @@ -293,6 +341,7 @@ void gicv3_full_update_noirqset(GICv3State *s) =20 for (i =3D 0; i < s->num_cpu; i++) { s->cpu[i].hppi.prio =3D 0xff; + s->cpu[i].hppi.nmi =3D false; } =20 /* Note that we can guarantee that these functions will not diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 9810558b076..207f8417e1f 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -536,8 +536,11 @@ static void arm_gicv3_common_reset_hold(Object *obj) memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr)); =20 cs->hppi.prio =3D 0xff; + cs->hppi.nmi =3D false; cs->hpplpi.prio =3D 0xff; + cs->hpplpi.nmi =3D false; cs->hppvlpi.prio =3D 0xff; + cs->hppvlpi.nmi =3D false; =20 /* State in the CPU interface must *not* be reset here, because it * is part of the CPU's reset domain, not the GIC device's. diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index ed1f9d1e444..90b238fac0b 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -120,6 +120,7 @@ static void update_for_one_lpi(GICv3CPUState *cs, int i= rq, ((prio =3D=3D hpp->prio) && (irq <=3D hpp->irq))) { hpp->irq =3D irq; hpp->prio =3D prio; + hpp->nmi =3D false; /* LPIs and vLPIs are always non-secure Grp1 interrupts */ hpp->grp =3D GICV3_G1NS; } @@ -156,6 +157,7 @@ static void update_for_all_lpis(GICv3CPUState *cs, uint= 64_t ptbase, int i, bit; =20 hpp->prio =3D 0xff; + hpp->nmi =3D false; =20 for (i =3D GICV3_LPI_INTID_START / 8; i < pendt_size / 8; i++) { address_space_read(as, ptbase + i, MEMTXATTRS_UNSPECIFIED, &pend, = 1); @@ -241,6 +243,7 @@ static void gicv3_redist_update_vlpi_only(GICv3CPUState= *cs) =20 if (!FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, VALID)) { cs->hppvlpi.prio =3D 0xff; + cs->hppvlpi.nmi =3D false; return; } =20 --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714042032; cv=none; d=zohomail.com; s=zohoarc; b=WacBnsYfvJHmo/vqHbdJgOjXXUjKwNckysfoeGVSo8j9NH6nxe1JSYepNpmyvcLvSRnqXUpmI/fgP3XsBwp0Dat2atm+tDZRYwdqb1eO+sB3InfujLL9GFfvlR0r/n3AR+vE0ntlIdrM4l3W+5MUJuFrlsx6UygPtyweTdZS0So= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714042032; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041611; x=1714646411; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HzNnGVxNUANHnRTDrHNeQGZ2Bf5NCH/o+ElhlaY0jvE=; b=X7YD3+CqbVef9fC3374VB/Rx3QdmIrJbW1nNw38cHI154CKJCSAMI/44d77MoUZSsI fDdlpuaq7iTkVQTRS0RMWc7rzC4VrK9Hq6vt5TiEO8b2uP1cWArEoAVTMW6WJb++Oh0u arNIfNQsC8psoUndiqS5Yb4hHQsKUkgmHdKwAKT7ffL7mpOcGOhdcsYeQXnLv7RK51Qg 4bnjo1sr7h1Gc8vpmPuuFYfGKGq726QfWrrGmzBih1v8hgzsI4gyZ1aR4EYuGf68XcIv U3jGhj101KbVuI/0511iGAs8ASU24IZ5z8XE26bE9tJkYGKQnHSctfHx58ZDou8inaoa WzBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041611; x=1714646411; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HzNnGVxNUANHnRTDrHNeQGZ2Bf5NCH/o+ElhlaY0jvE=; b=D2D/WGua2xLaiZuxOR34CPZjRvPYExKcl1kpnQ1J1lLWsFOOAA9GJ/CAz/ny5SlI1k NsGadIf9EBqIPkTGuPaxZUGgvK3gNc4h5rdnwLDRLOALgGRUD+jlkpveP6WNoQA/l0gq /hbd+GKQ1Pqz+N0MTvdwYSlKXr9xNYWoiftLbRI0ppYJkt1j5TIt7qEQ9m2ApHcweaHI EdbWOGMyUf4VdV7nlaO1s+7ORRF1Ou3ktVwBIxrc7mtJcq/bkIwDKQwB85vfQkhnSV8Y AXT4gKMQPyke59pG3Da9KnxGgqq6ACXdpvW8un9xseSCccfzn+wm9Z1T0jiyG9ekGJGG 9qtA== X-Gm-Message-State: AOJu0YwCq22PXlYsEWxD7XJcUfArbA5tt4TNRC+PWTbmbCE5sXasGkZm 9tYlZVeGtnrm9QTLhlE44yfi527n7XKuHawNzPB7nJRJyR9A17/w54bz0FX60QSnbpnWDM1SI+J 2 X-Google-Smtp-Source: AGHT+IEGJV7UKxEtu29OHIA5wLqftBJSybiXFExMUydWnPyMqds8cdVkMeavcAzP9D5E7grrBQLW5A== X-Received: by 2002:adf:f384:0:b0:34a:e6aa:bc01 with SMTP id m4-20020adff384000000b0034ae6aabc01mr3990814wro.5.1714041611185; Thu, 25 Apr 2024 03:40:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/37] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() Date: Thu, 25 Apr 2024 11:39:42 +0100 Message-Id: <20240425103958.3237225-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714042034205100003 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan In CPU Interface, if the IRQ has the non-maskable property, report NMI to the corresponding PE. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-22-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index b1f6c16ffef..2cf232d099c 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1038,6 +1038,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs) /* Tell the CPU about its highest priority pending interrupt */ int irqlevel =3D 0; int fiqlevel =3D 0; + int nmilevel =3D 0; ARMCPU *cpu =3D ARM_CPU(cs->cpu); CPUARMState *env =3D &cpu->env; =20 @@ -1076,6 +1077,8 @@ void gicv3_cpuif_update(GICv3CPUState *cs) =20 if (isfiq) { fiqlevel =3D 1; + } else if (cs->hppi.nmi) { + nmilevel =3D 1; } else { irqlevel =3D 1; } @@ -1085,6 +1088,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs) =20 qemu_set_irq(cs->parent_fiq, fiqlevel); qemu_set_irq(cs->parent_irq, irqlevel); + qemu_set_irq(cs->parent_nmi, nmilevel); } =20 static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041911; cv=none; d=zohomail.com; s=zohoarc; b=lL3SzxX42PW3NwTLSux3NprcO9RI6buQm4u347Jk/JRabo10rY/Mg/R5jtHPirPSqwvZ0gECNUu2cg81rGVGxfAcyMMtqsRWSEmWREfhsWfD7+bDbqwPSzkGOZiQWj4ErhNKGIzwKZP4ZG5HuyVJ51huBTG0Je1wX3OBat2lL6k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041911; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=0tEoEynUn/Blzafott1YrsfCl8+TNo9nbqDoRZ2ImKI=; b=luw5gQHnCQfGtYMPekBkE76SIgE7pT35t9I958JA6l1wR/VL0BVjnKbJktHXEShA1WbvuCe6QMDbzFgwNIoa/SJYakgTwis832gmT01KsRuosAz1nSl/RWq9yUgHBbw/j9Vk+1o518Tdkjcd+JyuuNr3+gEJuB74d9l4nCBn1js= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041911666976.2015803307077; Thu, 25 Apr 2024 03:45:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWb-00028D-0F; Thu, 25 Apr 2024 06:40:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWW-00022P-2K for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:16 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWT-0007DF-4i for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:15 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-41a72f3a20dso5214235e9.0 for ; Thu, 25 Apr 2024 03:40:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041611; x=1714646411; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0tEoEynUn/Blzafott1YrsfCl8+TNo9nbqDoRZ2ImKI=; b=GnwWQCiSt30pKDvUa+OPs5eQeBsLtIJm00FASUyiKqw19/HnB8jseaFOm+yvSrzxzU C1DgKwR5MpsDuNGC9r2YeQUloCOfIKW9P+ERRzIfg1c+R+Ypiiy3FbkXfsOPThpAa6nu 3nrKaJnV2VLmzq3MfmdU7tEdf2/QQPFnWaTizP7GOs2J3hkUGY6EHlhfOcx2Uaoll8TH dafgPkBQug2MFIjpG8i5l9cbtaBPkGJsOcVhQUTZX1X+5bk+ygE2cPQhOBC5cNZFylm3 TZFqzkhwzbJnIe7CaA8n2I/IQOyomGF9topcIPXSXVzFNVLKeA1lJs8NhbTMDTzDJx13 NERA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041611; x=1714646411; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0tEoEynUn/Blzafott1YrsfCl8+TNo9nbqDoRZ2ImKI=; b=f8Boo4yy1UfUP612q7m4/4BBwAMstLbdtjplpwOhVmB85phuqCymIQ++rAijKoCgC7 gGvwiUjidwMg+rsMeA/pRY2/a/eG7CFxv3OML3Ad/6B0aM+edoGK99uZeI5DxyE6HfBm 4muZhEld2FqwMQXOBF6WZ5XlOUPSifHBFTK0BVgyPOGsNfxVFk40afoCLIkso8GX9kA3 i5vPXRQiXcCoxPR7C44xS1eRU9V/4GIhNd0sT9UDisc1CCy6EOhnHctQF8TNs9Epzjt3 Uey2IXXQgMtfgsvZeARlIu0Xjkz11Agh91TagKZmwyfjxpluluu+2pmFqOFWZaDSmXu5 zCHw== X-Gm-Message-State: AOJu0Yw9jKjoO5rBkYAt/UBErpVRmorbJ61QRjYr5PDPYpPxv11xojVo cEGtLcD+XQRziucawLJ8qDKNNtBREtAqe/SHLkcEAxpzPtVpWxk7QzWB/knGsg/EJlC0bJoPKy+ L X-Google-Smtp-Source: AGHT+IHX9ybYHLCatXSYHResAm69x5YnuuHYhGqCcJt54CeTU4kQ9sCDJzfWfWFERZ5f9GuFiYLT3g== X-Received: by 2002:a7b:c406:0:b0:418:2a57:380c with SMTP id k6-20020a7bc406000000b004182a57380cmr4339476wmi.26.1714041611583; Thu, 25 Apr 2024 03:40:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/37] hw/intc/arm_gicv3: Report the VINMI interrupt Date: Thu, 25 Apr 2024 11:39:43 +0100 Message-Id: <20240425103958.3237225-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041913768100005 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan In vCPU Interface, if the vIRQ has the non-maskable property, report vINMI to the corresponding vPE. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-23-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 2cf232d099c..bdb13b00e98 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -481,6 +481,7 @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs) int idx; int irqlevel =3D 0; int fiqlevel =3D 0; + int nmilevel =3D 0; =20 idx =3D hppvi_index(cs); trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx, @@ -498,9 +499,17 @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs) uint64_t lr =3D cs->ich_lr_el2[idx]; =20 if (icv_hppi_can_preempt(cs, lr)) { - /* Virtual interrupts are simple: G0 are always FIQ, and G1 IR= Q */ + /* + * Virtual interrupts are simple: G0 are always FIQ, and G1 are + * IRQ or NMI which depends on the ICH_LR_EL2.NMI to have + * non-maskable property. + */ if (lr & ICH_LR_EL2_GROUP) { - irqlevel =3D 1; + if (lr & ICH_LR_EL2_NMI) { + nmilevel =3D 1; + } else { + irqlevel =3D 1; + } } else { fiqlevel =3D 1; } @@ -510,6 +519,7 @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs) trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, irql= evel); qemu_set_irq(cs->parent_vfiq, fiqlevel); qemu_set_irq(cs->parent_virq, irqlevel); + qemu_set_irq(cs->parent_vnmi, nmilevel); } =20 static void gicv3_cpuif_virt_update(GICv3CPUState *cs) --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041886; cv=none; d=zohomail.com; s=zohoarc; b=VgJAj6caqMUFcohBbRKC6wQGKgV1mSp7V7zvIczflIKUCnXo9lrkWi2OVxvdSmE/lm2M/DPCy/QJfDpa3ZofDMFosAHIpCuV7jQH112vqNOwcl53Apfc9moPRu2GBQ/YsIEis2LBQC0/sTvuilrN/NRJZL+DkTiJH50ofE2duro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041886; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=JV5XMEidgBDiNWN22aPz5h+5c0+tMvdllGUtHuIZpHI=; b=bDiucs49wBoR78efecW4rEU5rrfU9HtKecUjcqPwYYFrSJxC07gNso48EQA2Q7TvLT3ydbK1BWpKjbCG+sECNGKWM8OGVs7f6jlpWtjq81HTqiIqbjHI4fs6j+8htaXe68Y2IyqeW1/7tAujZgOrjnxF+Uj651m63AjDnW9N0tg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17140418862561015.0542968243334; Thu, 25 Apr 2024 03:44:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWe-0002Lb-CC; Thu, 25 Apr 2024 06:40:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWW-00022g-HH for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:16 -0400 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWT-0007DV-Tz for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:15 -0400 Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-516d2600569so963440e87.0 for ; Thu, 25 Apr 2024 03:40:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041612; x=1714646412; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JV5XMEidgBDiNWN22aPz5h+5c0+tMvdllGUtHuIZpHI=; b=irGiofG4r9+aaPM6cQW6bYoyQhKJ1EvmoY+rw+q25K0bQCSXD8apycWfRxmbNTOx2B /k30983yTE771pW3NJI4Zdid1ZoRdhRoJEoOFHRPhQzdHaIz12QOLvm15+KeP8V5YOXI vDzhQem6SdXi9GZpRbk33iYUiCCMPQ0gtyi501XRCBPNwhiGjEnhsOf9xCjM8FK7a+VA 5IJVPkEVG3z+xco10LmECME4rfarW6BfTd6sEHqU+DScPbK+LtqeAZlYM6MCMAdAVXjQ 76CmI+h5hYSD9CUmE8liA2CL1j9kOesJoCeX+sSfaHAWd9NK/KPc5YIDeB811iMX1UZo /UOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041612; x=1714646412; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JV5XMEidgBDiNWN22aPz5h+5c0+tMvdllGUtHuIZpHI=; b=Qz1qNq9V2JtBs2panBd1gL8IONJaQfLmR/cS2RFN0XUSdRjJGPc95GAsPXkVm9Mb48 6efw+YC1pVaFel6S12ASRHZ/AzcPOr4Cn6Hx0YcpSSWe9J6nMQoeua/PnvQe6VXO8EAI IflY1Teq9og/ypbW4noaDW00AgTKASualPfwQWnwcLXBEF5amaInaa76pGRaEiC0e7Kw zoHbFXq8n9IKpn0YXoBozn/RaYwdL95iKj2j8LUS01qWmzRh6mmHip69LEv19mw5M09R TXLt1M0QloYl758AdffejKRPcX05GHbspPr3tVajjkIia/tY6bGs4NoFgu0jpKa961P0 SZeA== X-Gm-Message-State: AOJu0YzHz58hS+8hgCVNhj4EqWceR54CmQj58TG9E/p8fXVLJKI3BPhQ pBuClKILYoFb6Oi356JKLbnSmwcLAasItBjtznPp0QFIFmBhKdjNmjl+x9sjqYSd1TwS9tVMtfZ 4 X-Google-Smtp-Source: AGHT+IFVXlkurRzX9LA2OG+QRP2l+UxVnaULQ9lEaBmu3LH7/fpwgHOnxiqYwUB2K7Zf0QCA0FHzyw== X-Received: by 2002:a05:6512:406:b0:516:d2b9:d112 with SMTP id u6-20020a056512040600b00516d2b9d112mr3657626lfk.40.1714041612022; Thu, 25 Apr 2024 03:40:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/37] target/arm: Add FEAT_NMI to max Date: Thu, 25 Apr 2024 11:39:44 +0100 Message-Id: <20240425103958.3237225-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041887706100003 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan Enable FEAT_NMI on the 'max' CPU. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240407081733.3231820-24-ruanjinjie@huawei.com Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 2a7bbb82dc4..a9ae7ede9fc 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -64,6 +64,7 @@ the following architecture extensions: - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE3 (MTE Asymmetric Fault Handling) +- FEAT_NMI (Non-maskable Interrupt) - FEAT_NV (Nested Virtualization) - FEAT_NV2 (Enhanced nested virtualization support) - FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 9f7a9f3d2cc..62c4663512b 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1175,6 +1175,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041995; cv=none; d=zohomail.com; s=zohoarc; b=LtRgJVfAJFAVOzdUN0mDwTtnwafcnI6iuDS0f4HSme+bSnVX5ZUxKe/tYrYlE2r+jW7XLNOxwr0G7egXnijMEbdvBDmW52e2aI7/H6lhcP57dZRQynF+FJcmfkamcflNgd2/NyvVaHREO3DDR0q9nbCaRYiRpnwDPw+ljjjJAQ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041995; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=PQpS8WwkI3zNhylYTqxyPFLwAk0dCYZh37pbQidxx4Q=; b=W5I/GI7EHnM2zSULVYwIQtelO6EYMtO6PE8XqydByT9odwBXlOzAyOPL3IVibrkbkKBahjsVByCWQBreFmR2C+sLkIUlboVsoqvyX82Dz6SXESKUFAGtmVfPr+HxCr2RSbVENe9CIV4DC7uECXUvEDlriAjxV36SYtnVEvV6FbY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041995630218.73059777229355; Thu, 25 Apr 2024 03:46:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWb-0002CL-RC; Thu, 25 Apr 2024 06:40:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWX-00022s-2v for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:17 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWU-0007Dn-UX for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:16 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-418e4cd2196so6706175e9.1 for ; Thu, 25 Apr 2024 03:40:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041612; x=1714646412; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=PQpS8WwkI3zNhylYTqxyPFLwAk0dCYZh37pbQidxx4Q=; b=VD1kTuu7OVmNkNEt8g7AQlQH2zH9mYpQGBqlmWS97OVPmMyBEN08pTGxnG+2zZAAEk ZExSbOy/hCf4YSswDhr7H96HaOGBnF2oQGVu9cPAfcvRnGOKknPYUBnq8kCpri0yYuIG 0Vot1yA4lL2eYCB/f8sQ8TuX4GVU9mwcaaw6aaPODDq70BGz1VbQBoghH5RF05nqs4D7 w4Qyb40MA8i6akGTdGFZkHnE9l6rdgio0TGVOxlUtL72nFOsq2lMNAYF0Ba2bvjz4clJ EkzMyzTRZIwzf4Nnx6zrpGG+Ltiit1RpPYiX0GPwFHNVHcSV0oy0ugid7KG6qBcwoyQs X3HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041612; x=1714646412; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PQpS8WwkI3zNhylYTqxyPFLwAk0dCYZh37pbQidxx4Q=; b=JX7EW7UcczsAaZsfg7Fv47k3izz4EMAZ7ja6GZ6+092oiaZ5ulwVgySqz5VZcoQQqS wANkwil/Nx6YZ2HiI7by1/EPbV6+rhG04XL9iceCBUAW4HDBiQSkQOf4pOijbNs/rGiE t7Yvvj9TvLauGKEB3D3nOsiJgYMyGPDIZYXyKqNSeJTT8bNPGrYKBVulRiX8J8TRIben a9HQdB7BO3V9XC9xaq+nD3/WAfAN8U5wwZLJXrDHsX6pyxVmXxitaPflENVZZoOr9MNM 0JD/MBqjCljvIdpKAbeUnDKF3N92XE00tDT2EbF5ozjpV46zBzAwQUrC/lSs2u5Wb9xQ FnBw== X-Gm-Message-State: AOJu0Yx84i42R57AXoc2/nJmt481g2LiJbTSTiTtXXc0kfHeXSi4J7y5 aMVxPvO+TKRCJpOxHAfkQ+xyv1cZcuK/a2HiHBIjOI2FH8zLqq6lHWAKtaukOBtfQb/OB+e9Rv6 W X-Google-Smtp-Source: AGHT+IGgkQMxhnQkQ/6ydHVOfuoavQgQUGmIQaZgiYIIcFTtS3VCp2QlpC1xgNg+f4Xj8E31eYu9gA== X-Received: by 2002:a05:600c:1c83:b0:41a:e995:b915 with SMTP id k3-20020a05600c1c8300b0041ae995b915mr4174322wms.1.1714041612495; Thu, 25 Apr 2024 03:40:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/37] hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI Date: Thu, 25 Apr 2024 11:39:45 +0100 Message-Id: <20240425103958.3237225-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041995978100003 Content-Type: text/plain; charset="utf-8" From: Jinjie Ruan If the CPU implements FEAT_NMI, then turn on the NMI support in the GICv3 too. It's permitted to have a configuration with FEAT_NMI in the CPU (and thus NMI support in the CPU interfaces too) but no NMI support in the distributor and redistributor, but this isn't a very useful setup as it's close to having no NMI support at all. We don't need to gate the enabling of NMI in the GIC behind a machine version property, because none of our current CPUs implement FEAT_NMI, and '-cpu max' is not something we maintain migration compatibility across versions for. So we can always enable the GIC NMI support when the CPU has it. Neither hvf nor KVM support NMI in the GIC yet, so we don't enable it unless we're using TCG. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Message-id: 20240407081733.3231820-25-ruanjinjie@huawei.com [PMM: Update comment and commit message] Suggested-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c4b03b09c27..3c93c0c0a61 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -729,6 +729,20 @@ static void create_v2m(VirtMachineState *vms) vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; } =20 +/* + * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too. + * It's permitted to have a configuration with NMI in the CPU (and thus the + * GICv3 CPU interface) but not in the distributor/redistributors, but it's + * not very useful. + */ +static bool gicv3_nmi_present(VirtMachineState *vms) +{ + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(0)); + + return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) && + (vms->gic_version !=3D VIRT_GIC_VERSION_2); +} + static void create_gic(VirtMachineState *vms, MemoryRegion *mem) { MachineState *ms =3D MACHINE(vms); @@ -802,6 +816,11 @@ static void create_gic(VirtMachineState *vms, MemoryRe= gion *mem) vms->virt); } } + + if (gicv3_nmi_present(vms)) { + qdev_prop_set_bit(vms->gic, "has-nmi", true); + } + gicbusdev =3D SYS_BUS_DEVICE(vms->gic); sysbus_realize_and_unref(gicbusdev, &error_fatal); sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041640; cv=none; d=zohomail.com; s=zohoarc; b=G/kzsHprO0+kKaSd4Gp/q7oHf4BvYbNVH1bQtn0WoqA8JTnb+wf1ABcHmPFhSo42TfHbBMPMm32UyqqywGCMcssPljlb0k57m8YN+tYZIXVYX0+6yfKLkHFW7D8Ygq+/DiWr3fadIf5r7BjUYfwEELWOkwZp8YZvOxoAgF4h4HA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041640; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DC9SqOM/M/fO+YfMesu8LY8qeYkZJ02Q4hHEAc7RbS4=; b=OkFbWBNPClM2UbKpwk2QJ6tcc0LzYDA267zn79pSH9yMu3Befq5ZXF1hDmVjUs5+98rqiR7ZMrxkcttV2/ttujWOxsAhBFgCEA08DTeJyzgvGnNKybDWo4XSclM1e/KlEYUozY87BFez7nKb4RY1goc6H53Iihd98GNY55vAbT0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041640068844.4524599415815; Thu, 25 Apr 2024 03:40:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWa-000277-Mm; Thu, 25 Apr 2024 06:40:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWW-00022m-KF for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:16 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWU-0007Dh-QI for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:16 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-41b6254a47cso1268565e9.3 for ; Thu, 25 Apr 2024 03:40:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041613; x=1714646413; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DC9SqOM/M/fO+YfMesu8LY8qeYkZJ02Q4hHEAc7RbS4=; b=Qi4WUPJJiHHmhe51nvauQDjTLKTJaOJU6OwMzEgqwR2cr6VwmkL4B7UsUzij8Hd3V+ wHfPjpu6Eilh0ijoImC8DG5OzkHFAdRJvAiGZ7xqX7kF/Czqu4g72dwGdW5XXmiGx+Ss NFN7mGQzBh5DcuCw08Z9TSJCykQSl74ZDFwxblWjf1R4maCeKxupEtWtjgol/D4dMVWH h0mj/Ohyc1lPz/bK0TFL26iE82PdL/2EMRH0FquNM2uL7e2lEGk+W4n9FvHQHgbnLYU7 ZS2CSfCF7/kjiGhaFisrnYNDtltgc/f3MlDXvcELcAJJff1mycV34oyp84rr+OV1xytM xQYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041613; x=1714646413; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DC9SqOM/M/fO+YfMesu8LY8qeYkZJ02Q4hHEAc7RbS4=; b=a3YTWjCzNXhcIuTyiTBx+rQrv0BKoMB7u/o24uM21mYPXG/HHQFJVTYHUwsnUqC/+a Rbh1KN9GiHLYDenm46RU+bCGTU2nt8R2fMPYqz1m01mRf9lxHi+ceXi94LFBhRLt9435 4F86s6eSjw5Eewt/rm9vLVesv/pVhs+LDYPx/1u3kKmPUKrkmjaIjPCmHn2e/HXOlUeK //Ij9R2Thw6BCS8BtffnPBeRlCBJiziRR7O4pubmSyRzMzr9TekLkAWtaXS+2o5TlaBQ Wj3DaC8Tz4NW1NCp43BTWKZC+hIqnAxd04T+H6infIho01XcApRsedlXDlgINr3yiwvA Kg1g== X-Gm-Message-State: AOJu0Yx1Jdm/thJS2/eGB9QH+6Cx1QIQ6jP/IafbhEX34cdC9v1GWbGI WWmHP4H/Mt3y/ZV8SkXZQbQQzjyl7TQ8NDWtmEu4wc63HUnWzFJ18gR7mV4vLvNa+Kjn1jCdzD0 s X-Google-Smtp-Source: AGHT+IEUVCA6B5iR4LoelrOcCZ5jaF36bsfDYTwDO3EZfOtDJfYwLX+od6GF1oUhChTuPd2/A6ng+w== X-Received: by 2002:a05:6000:d87:b0:348:c2c7:9f13 with SMTP id dv7-20020a0560000d8700b00348c2c79f13mr4099675wrb.65.1714041613014; Thu, 25 Apr 2024 03:40:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/37] hw/dma: avoid apparent overflow in soc_dma_set_request Date: Thu, 25 Apr 2024 11:39:46 +0100 Message-Id: <20240425103958.3237225-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041641003100003 Content-Type: text/plain; charset="utf-8" From: Anastasia Belova In soc_dma_set_request() we try to set a bit in a uint64_t, but we do it with "1 << ch->num", which can't set any bits past 31; any use for a channel number of 32 or more would fail due to integer overflow. This doesn't happen in practice for our current use of this code, because the worst case is when we call soc_dma_init() with an argument of 32 for the number of channels, and QEMU builds with -fwrapv so the shift into the sign bit is well-defined. However, it's obviously not the intended behaviour of the code. Add casts to force the shift to be done as 64-bit arithmetic, allowing up to 64 channels. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: afbb5194d4 ("Handle on-chip DMA controllers in one place, convert OM= AP DMA to use it.") Signed-off-by: Anastasia Belova Message-id: 20240409115301.21829-1-abelova@astralinux.ru [PMM: Edit commit message to clarify that this doesn't actually bite us in our current usage of this code.] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/dma/soc_dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/dma/soc_dma.c b/hw/dma/soc_dma.c index 3a430057f54..d5c52b804f8 100644 --- a/hw/dma/soc_dma.c +++ b/hw/dma/soc_dma.c @@ -209,9 +209,9 @@ void soc_dma_set_request(struct soc_dma_ch_s *ch, int l= evel) dma->enabled_count +=3D level - ch->enable; =20 if (level) - dma->ch_enable_mask |=3D 1 << ch->num; + dma->ch_enable_mask |=3D (uint64_t)1 << ch->num; else - dma->ch_enable_mask &=3D ~(1 << ch->num); + dma->ch_enable_mask &=3D ~((uint64_t)1 << ch->num); =20 if (level !=3D ch->enable) { soc_dma_ch_freq_update(dma); --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041744; cv=none; d=zohomail.com; s=zohoarc; b=V9sy3eYpqWT3K7VY7dKZdQ2lXJi7riqG0cOEn6vmJXVC6td4R3PEqVYFYcyBsHiNrxzGCF37Eqx9MHSOLnEIKyFkHHykHofv5Z+2bU3CxK40yJTCMIO4oZ+HXzYFsiLwNchN6/Whl3Yg16dur2pjnX6y8+HdWoF9iNjkfYf/da0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041744; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=35oYYuwi+Br4xakq5nYHN4Yw6o3yTK6J3eUx77p4G0k=; b=Di7gaxogMpJ84ZdztnBw5QS7OpkT1H3MbQrmwonGJ9laWLeNdXC2ek59ITjKl/L2ylAFo5L0DLBl7qMwII6JXathObyL0Xm228g+zZ6aMngotERczz1595Z0NvAVOifjk4zwrE5ON+pQDYa8ZsHuPg6SsyTBhNaimtPaXLKaw7s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041744849283.12018510605765; Thu, 25 Apr 2024 03:42:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWd-0002JX-IU; Thu, 25 Apr 2024 06:40:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWZ-00023o-2D for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:19 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWV-0007Dm-1E for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:18 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-344047ac7e4so1079319f8f.0 for ; Thu, 25 Apr 2024 03:40:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041613; x=1714646413; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=35oYYuwi+Br4xakq5nYHN4Yw6o3yTK6J3eUx77p4G0k=; b=DkDei1sAXB/nljgjwWmicshlqifO0Xh/ZTeZGx7XJmOBEPZqyh/r9djp4IGnRjrhl4 We7YEEGX32gGxxRJOEDpC7GprQXLCR190zV+c96ssdv8QyZ0ziQ3SfJlPaxMqgjjt6eC 6B/PbECG9i7/iF2odG67BCb4kU9kZmu/OyAXKMA42p5tlCORZ9HjPbiBi/OyDOGUerZ8 8PEmL3F5Tq15LJtMpDTn1dQMlzY5L6EsMWC05ntQWq6DPtZ77jF9CAFVsqgfzNYW22dX LV35GICIguPKKQpNJUlsFfsCT8/f35qUmwor1SNx+yvCEEyylaWUwIJj/WIKZuHe2gn+ L/dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041613; x=1714646413; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=35oYYuwi+Br4xakq5nYHN4Yw6o3yTK6J3eUx77p4G0k=; b=sKT8Mn0RLo8UWoP7GWdvdtftdngDQ72TlMr3wxW9EyOS6j9BxH5t9XpCgj6141vLSn gcxFhSM0/2uYwEux2UFvuucyS5cpCR/SOrCHi9KuRcWgs8BsLASnqRuAAf3B/1CjWy2i smJmg6sCoGP+fL8aq13cgLWJbQG2y5dWTq12cmIzd7CRpEHLvEkRlV4TSktFWoa6kd4f yMX8dgHgTIfvVA63GyeLNisrJnuMefghRInHlf6LWr0xtWeRNPoMvKGUgxH90qsEJV2u +pPXBy47PI23vvH6KbfQ2DiVjZHR5z+VEq0TrvK4jPiecJhtdz5lcgkzupYiq9jGY7kI aiFA== X-Gm-Message-State: AOJu0YwfGTVoT/xuR1ACYdRVLRE2jBIL/rCCqs4I2hzTW6wNUNtg7mC+ rFHDqbZynMEUyJ+zDMzO2JAhPb/mo8IPFk8kyLA0ia7Uo6P1oyQw49nNnpUIjYWK9h+QQHsvQdY 2 X-Google-Smtp-Source: AGHT+IGfF+KPxpkk+hJ2NRT5wQslXygN22dz7N57UWmI0wITdBFgVpe00zF52qxFfFbyWmOjbRt9FA== X-Received: by 2002:a5d:52c8:0:b0:346:a39f:6b69 with SMTP id r8-20020a5d52c8000000b00346a39f6b69mr1632299wrv.24.1714041613507; Thu, 25 Apr 2024 03:40:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/37] linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code Date: Thu, 25 Apr 2024 11:39:47 +0100 Message-Id: <20240425103958.3237225-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041745368100001 Ever since the bFLT format support was added in 2006, there has been a chunk of code in the file guarded by CONFIG_BINFMT_SHARED_FLAT which is supposedly for shared library support. This is not enabled and it's not possible to enable it, because if you do you'll run into the "#error needs checking" in the calc_reloc() function. Similarly, CONFIG_BINFMT_ZFLAT exists but can't be enabled because of an "#error code needs checking" in load_flat_file(). This code is obviously unfinished and has never been used; nobody in the intervening 18 years has complained about this or fixed it, so just delete the dead code. If anybody ever wants the feature they can always pull it out of git, or (perhaps better) write it from scratch based on the current Linux bFLT loader rather than the one of 18 years ago. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20240411115313.680433-1-peter.maydell@linaro.org --- linux-user/flat.h | 5 +- linux-user/flatload.c | 293 ++---------------------------------------- 2 files changed, 11 insertions(+), 287 deletions(-) diff --git a/linux-user/flat.h b/linux-user/flat.h index ed518e2013b..e374b73e268 100644 --- a/linux-user/flat.h +++ b/linux-user/flat.h @@ -12,11 +12,8 @@ =20 #define FLAT_VERSION 0x00000004L =20 -#ifdef CONFIG_BINFMT_SHARED_FLAT -#define MAX_SHARED_LIBS (4) -#else +/* QEMU doesn't support bflt shared libraries */ #define MAX_SHARED_LIBS (1) -#endif =20 /* * To make everything easier to port and manage cross platform diff --git a/linux-user/flatload.c b/linux-user/flatload.c index 5b62aa0a2be..04d8138d12e 100644 --- a/linux-user/flatload.c +++ b/linux-user/flatload.c @@ -29,8 +29,6 @@ * JAN/99 -- coded full program relocation (gerg@snapgear.com) */ =20 -/* ??? ZFLAT and shared library support is currently disabled. */ - /*************************************************************************= ***/ =20 #include "qemu/osdep.h" @@ -64,10 +62,6 @@ struct lib_info { short loaded; /* Has this library been loaded? */ }; =20 -#ifdef CONFIG_BINFMT_SHARED_FLAT -static int load_flat_shared_library(int id, struct lib_info *p); -#endif - struct linux_binprm; =20 /*************************************************************************= ***/ @@ -108,153 +102,6 @@ static int target_pread(int fd, abi_ulong ptr, abi_ul= ong len, unlock_user(buf, ptr, len); return ret; } -/*************************************************************************= ***/ - -#ifdef CONFIG_BINFMT_ZFLAT - -#include - -#define LBUFSIZE 4000 - -/* gzip flag byte */ -#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */ -#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip fi= le */ -#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */ -#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ -#define COMMENT 0x10 /* bit 4 set: file comment present */ -#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ -#define RESERVED 0xC0 /* bit 6,7: reserved */ - -static int decompress_exec( - struct linux_binprm *bprm, - unsigned long offset, - char *dst, - long len, - int fd) -{ - unsigned char *buf; - z_stream strm; - loff_t fpos; - int ret, retval; - - DBG_FLT("decompress_exec(offset=3D%x,buf=3D%x,len=3D%x)\n",(int)offset, (= int)dst, (int)len); - - memset(&strm, 0, sizeof(strm)); - strm.workspace =3D kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL); - if (strm.workspace =3D=3D NULL) { - DBG_FLT("binfmt_flat: no memory for decompress workspace\n"); - return -ENOMEM; - } - buf =3D kmalloc(LBUFSIZE, GFP_KERNEL); - if (buf =3D=3D NULL) { - DBG_FLT("binfmt_flat: no memory for read buffer\n"); - retval =3D -ENOMEM; - goto out_free; - } - - /* Read in first chunk of data and parse gzip header. */ - fpos =3D offset; - ret =3D bprm->file->f_op->read(bprm->file, buf, LBUFSIZE, &fpos); - - strm.next_in =3D buf; - strm.avail_in =3D ret; - strm.total_in =3D 0; - - retval =3D -ENOEXEC; - - /* Check minimum size -- gzip header */ - if (ret < 10) { - DBG_FLT("binfmt_flat: file too small?\n"); - goto out_free_buf; - } - - /* Check gzip magic number */ - if ((buf[0] !=3D 037) || ((buf[1] !=3D 0213) && (buf[1] !=3D 0236))) { - DBG_FLT("binfmt_flat: unknown compression magic?\n"); - goto out_free_buf; - } - - /* Check gzip method */ - if (buf[2] !=3D 8) { - DBG_FLT("binfmt_flat: unknown compression method?\n"); - goto out_free_buf; - } - /* Check gzip flags */ - if ((buf[3] & ENCRYPTED) || (buf[3] & CONTINUATION) || - (buf[3] & RESERVED)) { - DBG_FLT("binfmt_flat: unknown flags?\n"); - goto out_free_buf; - } - - ret =3D 10; - if (buf[3] & EXTRA_FIELD) { - ret +=3D 2 + buf[10] + (buf[11] << 8); - if (unlikely(LBUFSIZE =3D=3D ret)) { - DBG_FLT("binfmt_flat: buffer overflow (EXTRA)?\n"); - goto out_free_buf; - } - } - if (buf[3] & ORIG_NAME) { - for (; ret < LBUFSIZE && (buf[ret] !=3D 0); ret++) - ; - if (unlikely(LBUFSIZE =3D=3D ret)) { - DBG_FLT("binfmt_flat: buffer overflow (ORIG_NAME)?\n"); - goto out_free_buf; - } - } - if (buf[3] & COMMENT) { - for (; ret < LBUFSIZE && (buf[ret] !=3D 0); ret++) - ; - if (unlikely(LBUFSIZE =3D=3D ret)) { - DBG_FLT("binfmt_flat: buffer overflow (COMMENT)?\n"); - goto out_free_buf; - } - } - - strm.next_in +=3D ret; - strm.avail_in -=3D ret; - - strm.next_out =3D dst; - strm.avail_out =3D len; - strm.total_out =3D 0; - - if (zlib_inflateInit2(&strm, -MAX_WBITS) !=3D Z_OK) { - DBG_FLT("binfmt_flat: zlib init failed?\n"); - goto out_free_buf; - } - - while ((ret =3D zlib_inflate(&strm, Z_NO_FLUSH)) =3D=3D Z_OK) { - ret =3D bprm->file->f_op->read(bprm->file, buf, LBUFSIZE, &fpos); - if (ret <=3D 0) - break; - if (is_error(ret)) { - break; - } - len -=3D ret; - - strm.next_in =3D buf; - strm.avail_in =3D ret; - strm.total_in =3D 0; - } - - if (ret < 0) { - DBG_FLT("binfmt_flat: decompression failed (%d), %s\n", - ret, strm.msg); - goto out_zlib; - } - - retval =3D 0; -out_zlib: - zlib_inflateEnd(&strm); -out_free_buf: - kfree(buf); -out_free: - kfree(strm.workspace); -out: - return retval; -} - -#endif /* CONFIG_BINFMT_ZFLAT */ =20 /*************************************************************************= ***/ =20 @@ -268,40 +115,7 @@ calc_reloc(abi_ulong r, struct lib_info *p, int curid,= int internalp) abi_ulong text_len; abi_ulong start_code; =20 -#ifdef CONFIG_BINFMT_SHARED_FLAT -#error needs checking - if (r =3D=3D 0) - id =3D curid; /* Relocs of 0 are always self referring */ - else { - id =3D (r >> 24) & 0xff; /* Find ID for this reloc */ - r &=3D 0x00ffffff; /* Trim ID off here */ - } - if (id >=3D MAX_SHARED_LIBS) { - fprintf(stderr, "BINFMT_FLAT: reference 0x%x to shared library %d\= n", - (unsigned) r, id); - goto failed; - } - if (curid !=3D id) { - if (internalp) { - fprintf(stderr, "BINFMT_FLAT: reloc address 0x%x not " - "in same module (%d !=3D %d)\n", - (unsigned) r, curid, id); - goto failed; - } else if (!p[id].loaded && is_error(load_flat_shared_library(id, = p))) { - fprintf(stderr, "BINFMT_FLAT: failed to load library %d\n", id= ); - goto failed; - } - /* Check versioning information (i.e. time stamps) */ - if (p[id].build_date && p[curid].build_date - && p[curid].build_date < p[id].build_date) { - fprintf(stderr, "BINFMT_FLAT: library %d is younger than %d\n", - id, curid); - goto failed; - } - } -#else id =3D 0; -#endif =20 start_brk =3D p[id].start_brk; start_data =3D p[id].start_data; @@ -425,12 +239,10 @@ static int load_flat_file(struct linux_binprm * bprm, if (rev =3D=3D OLD_FLAT_VERSION && flat_old_ram_flag(flags)) flags =3D FLAT_FLAG_RAM; =20 -#ifndef CONFIG_BINFMT_ZFLAT if (flags & (FLAT_FLAG_GZIP|FLAT_FLAG_GZDATA)) { - fprintf(stderr, "Support for ZFLAT executables is not enabled\n"); + fprintf(stderr, "ZFLAT executables are not supported\n"); return -ENOEXEC; } -#endif =20 /* * calculate the extra space we need to map in @@ -483,17 +295,9 @@ static int load_flat_file(struct linux_binprm * bprm, (int)(data_len + bss_len + stack_len), (int)datapo= s); =20 fpos =3D ntohl(hdr->data_start); -#ifdef CONFIG_BINFMT_ZFLAT - if (flags & FLAT_FLAG_GZDATA) { - result =3D decompress_exec(bprm, fpos, (char *) datapos, - data_len + (relocs * sizeof(abi_ulong= ))) - } else -#endif - { - result =3D target_pread(bprm->src.fd, datapos, - data_len + (relocs * sizeof(abi_ulong)), - fpos); - } + result =3D target_pread(bprm->src.fd, datapos, + data_len + (relocs * sizeof(abi_ulong)), + fpos); if (result < 0) { fprintf(stderr, "Unable to read data+bss\n"); return result; @@ -515,38 +319,12 @@ static int load_flat_file(struct linux_binprm * bprm, datapos =3D realdatastart + indx_len; reloc =3D (textpos + ntohl(hdr->reloc_start) + indx_len); =20 -#ifdef CONFIG_BINFMT_ZFLAT -#error code needs checking - /* - * load it all in and treat it like a RAM load from now on - */ - if (flags & FLAT_FLAG_GZIP) { - result =3D decompress_exec(bprm, sizeof (struct flat_hdr), - (((char *) textpos) + sizeof (struct flat= _hdr)), - (text_len + data_len + (relocs * sizeof(u= nsigned long)) - - sizeof (struct flat_hdr)), - 0); - memmove((void *) datapos, (void *) realdatastart, - data_len + (relocs * sizeof(unsigned long)= )); - } else if (flags & FLAT_FLAG_GZDATA) { - fpos =3D 0; - result =3D bprm->file->f_op->read(bprm->file, - (char *) textpos, text_len, &fpos); - if (!is_error(result)) { - result =3D decompress_exec(bprm, text_len, (char *= ) datapos, - data_len + (relocs * sizeof(unsig= ned long)), 0); - } - } - else -#endif - { - result =3D target_pread(bprm->src.fd, textpos, - text_len, 0); - if (result >=3D 0) { - result =3D target_pread(bprm->src.fd, datapos, - data_len + (relocs * sizeof(abi_ulong)), - ntohl(hdr->data_start)); - } + result =3D target_pread(bprm->src.fd, textpos, + text_len, 0); + if (result >=3D 0) { + result =3D target_pread(bprm->src.fd, datapos, + data_len + (relocs * sizeof(abi_ulong)), + ntohl(hdr->data_start)); } if (result < 0) { fprintf(stderr, "Unable to read code+data+bss\n"); @@ -678,44 +456,6 @@ static int load_flat_file(struct linux_binprm * bprm, =20 =20 /*************************************************************************= ***/ -#ifdef CONFIG_BINFMT_SHARED_FLAT - -/* - * Load a shared library into memory. The library gets its own data - * segment (including bss) but not argv/argc/environ. - */ - -static int load_flat_shared_library(int id, struct lib_info *libs) -{ - struct linux_binprm bprm; - int res; - char buf[16]; - - /* Create the file name */ - sprintf(buf, "/lib/lib%d.so", id); - - /* Open the file up */ - bprm.filename =3D buf; - bprm.file =3D open_exec(bprm.filename); - res =3D PTR_ERR(bprm.file); - if (IS_ERR(bprm.file)) - return res; - - res =3D prepare_binprm(&bprm); - - if (!is_error(res)) { - res =3D load_flat_file(&bprm, libs, id, NULL); - } - if (bprm.file) { - allow_write_access(bprm.file); - fput(bprm.file); - bprm.file =3D NULL; - } - return(res); -} - -#endif /* CONFIG_BINFMT_SHARED_FLAT */ - int load_flt_binary(struct linux_binprm *bprm, struct image_info *info) { struct lib_info libinfo[MAX_SHARED_LIBS]; @@ -793,19 +533,6 @@ int load_flt_binary(struct linux_binprm *bprm, struct = image_info *info) */ start_addr =3D libinfo[0].entry; =20 -#ifdef CONFIG_BINFMT_SHARED_FLAT -#error here - for (i =3D MAX_SHARED_LIBS-1; i>0; i--) { - if (libinfo[i].loaded) { - /* Push previous first to call address */ - --sp; - if (put_user_ual(start_addr, sp)) - return -EFAULT; - start_addr =3D libinfo[i].entry; - } - } -#endif - /* Stash our initial stack pointer into the mm structure */ info->start_code =3D libinfo[0].start_code; info->end_code =3D libinfo[0].start_code + libinfo[0].text_len; --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041699; cv=none; d=zohomail.com; s=zohoarc; b=XYGhI2giXGoEK1d6qxmcQTbsr3wS+Y0wXwQpg2m/vZSmmEtnQagsZv9/BHivATbXTJsGt2pzKQAZSnXd+dXEiFd3gGKHtPE2ZYyGK4TwokDkjPQK4pkClAq7Bc1Fq23l1XFMgku6z7Y8HbBecNUbrCQ77E+z9ltZTM83Bh16osk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041699; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=AMYxQWHy5jEXXCF6WIQ+tbnHt/CyfwoIHxTcgJbKUq8=; b=fDlvWNLzYyRd0yLvVJWSRAbLXdjJT/NsSmO1TIGyc6kIjTUvRK9UJgYUmTcaJ/421y0jKKnjUtUTdwIoLau05DyISevreYAIFqWlTQaZDLmpX7x6WteJoDwK2M1xCCn1/R286WsbcAmWWULf8umBumyVdwXrJ6iLAWYj3U9oeh4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041699854919.3544464464853; Thu, 25 Apr 2024 03:41:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWc-0002EF-AP; Thu, 25 Apr 2024 06:40:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWX-000235-HC for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:17 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWV-0007Ds-FT for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:17 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-34b3374ae22so806296f8f.0 for ; Thu, 25 Apr 2024 03:40:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041614; x=1714646414; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=AMYxQWHy5jEXXCF6WIQ+tbnHt/CyfwoIHxTcgJbKUq8=; b=LJ95vDO1mf4Z5f0OZy1hGXtbZNHXhcxT/KZSiZWh5PO+jrIY5CtWhmM1XCqSnPOVZz tu5K+/KKjF6JPsR+PqzJ3ZP3lck1tMiTaHFr48/l2Sx0iOcA09Vg2JjLHDaa7+X5Ektj LuGIkiFcbiip/i533WdbWb6I808tLgbJNEwQJD0ssEF3M0uWSlhxqKCjHbKbhma5JaMv SsVSJHfuLx4eTsCldVA+L0VJ56vyKDBnfI4qlE6UbmHaTF6dgjPRrH9NVTXocYp0aaaa XfCqK/jaWU4lAnXHLycQ0aqA1hxOyMLvSTq6b5cUM1hQUDTRBCythyjVj+0cd5k2+4Jc ezog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041614; x=1714646414; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AMYxQWHy5jEXXCF6WIQ+tbnHt/CyfwoIHxTcgJbKUq8=; b=FV3nmbHkFyxYlo0JOZMBc0YkdlQrL1ggBWZKq/QMN/2UPbjhJ82aOY+86QtATozFIb rLzhDKG7nOKUSeq3EboMSzFaegVorRMG/5H32cSJkP3UsW2u9EOk6CVFyv+CUXbq8w0z pCUO+jMqubN43fJl6djMmTF/sBM/3ktMVZhhMIy79N1jX87u74PO26hNjXhsuN1QNfde p2nnxfd0QfYOBkzdFiwA81SIv0JVapxTyQwHdNBoAbSCfPN+lcF/ZIxwUy8H1Zf9Zlsr rTXpW4V9YxbqJs5f8agPQkLEb0WCmsOdRIAdHFa5RvBH0hrSf8IDZf3l6jZ3/f1hWFOs RNLw== X-Gm-Message-State: AOJu0YxtlM0EcF1H6YguGAquW6MeEknPQqe+SSAJADjKjivQpgG99GU9 hk4VDjCU7aM+8GWa9DmC+fMj6/qZkmoKetaftT61dwTsKLb0G3zJfMAioV2BDpqUQ20LPTrtW2p l X-Google-Smtp-Source: AGHT+IHC3B9r6BAmcmuzdkAiOsnAbf7VH2QjRphyVF1OKN+Q2k5hrvE5Nh2R5gC+0Vx5Id6Kxticiw== X-Received: by 2002:adf:e101:0:b0:34a:4f1c:3269 with SMTP id t1-20020adfe101000000b0034a4f1c3269mr4319379wrz.0.1714041613951; Thu, 25 Apr 2024 03:40:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/37] hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr Date: Thu, 25 Apr 2024 11:39:48 +0100 Message-Id: <20240425103958.3237225-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041701419100003 The npcm7xx_clk and npcm7xx_gcr device reset methods look at the ResetType argument and only handle RESET_TYPE_COLD, producing a warning if another reset type is passed. This is different from how every other three-phase-reset method we have works, and makes it difficult to add new reset types. A better pattern is "assume that any reset type you don't know about should be handled like RESET_TYPE_COLD"; switch these devices to do that. Then adding a new reset type will only need to touch those devices where its behaviour really needs to be different from the standard cold reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Luc Michel Message-id: 20240412160809.1260625-2-peter.maydell@linaro.org --- hw/misc/npcm7xx_clk.c | 13 +++---------- hw/misc/npcm7xx_gcr.c | 12 ++++-------- 2 files changed, 7 insertions(+), 18 deletions(-) diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c index ac1622c38aa..2098c85ee01 100644 --- a/hw/misc/npcm7xx_clk.c +++ b/hw/misc/npcm7xx_clk.c @@ -873,20 +873,13 @@ static void npcm7xx_clk_enter_reset(Object *obj, Rese= tType type) =20 QEMU_BUILD_BUG_ON(sizeof(s->regs) !=3D sizeof(cold_reset_values)); =20 - switch (type) { - case RESET_TYPE_COLD: - memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); - s->ref_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - npcm7xx_clk_update_all_clocks(s); - return; - } - + memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); + s->ref_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + npcm7xx_clk_update_all_clocks(s); /* * A small number of registers need to be reset on a core domain reset, * but no such reset type exists yet. */ - qemu_log_mask(LOG_UNIMP, "%s: reset type %d not implemented.", - __func__, type); } =20 static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s) diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c index 9252f9d1488..c4c4e246d7e 100644 --- a/hw/misc/npcm7xx_gcr.c +++ b/hw/misc/npcm7xx_gcr.c @@ -159,14 +159,10 @@ static void npcm7xx_gcr_enter_reset(Object *obj, Rese= tType type) =20 QEMU_BUILD_BUG_ON(sizeof(s->regs) !=3D sizeof(cold_reset_values)); =20 - switch (type) { - case RESET_TYPE_COLD: - memcpy(s->regs, cold_reset_values, sizeof(s->regs)); - s->regs[NPCM7XX_GCR_PWRON] =3D s->reset_pwron; - s->regs[NPCM7XX_GCR_MDLR] =3D s->reset_mdlr; - s->regs[NPCM7XX_GCR_INTCR3] =3D s->reset_intcr3; - break; - } + memcpy(s->regs, cold_reset_values, sizeof(s->regs)); + s->regs[NPCM7XX_GCR_PWRON] =3D s->reset_pwron; + s->regs[NPCM7XX_GCR_MDLR] =3D s->reset_mdlr; + s->regs[NPCM7XX_GCR_INTCR3] =3D s->reset_intcr3; } =20 static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp) --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041999; cv=none; d=zohomail.com; s=zohoarc; b=AJe85sN6j/j/dLZPl61Niiym6UltStBQltw0Kycamzf1VcjTMXl3FlYxVb8nmM13Eg5ZnbaevUZj6VVulvR2pHmot7t+QfdvtrgupBg8/nRgN744Bl7CmmNEnzpIH8Kd6DacuwCLr5zU9p/+14sUJ9aAr5SxPfgR56VNWVaF0+Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041999; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=VCI8k2+9/ICoqj/E8reGAYIBlYDi3yFxDCuQaY0oqJg=; b=nRNhnLMygQ1W5Iypy0baavHNo41sFLsq2ZgymIug7H8PNmORTt8zHqj/JY4pRm6l1NTqO7BibhwkSFnepUExBBLYAeX5a8Bm6PeF2+26/g9sGFg8bw/VSN/2RWXS2tiPEqnqnApsVIRv8SCuSpFe2X6g8p9luH1JKbxVtvxPn1c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041999749906.1169218222847; Thu, 25 Apr 2024 03:46:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWf-0002Oz-BP; Thu, 25 Apr 2024 06:40:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWX-00023N-S4 for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:17 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWV-0007E0-Pd for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:17 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-34b1e35155aso940123f8f.3 for ; Thu, 25 Apr 2024 03:40:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041614; x=1714646414; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VCI8k2+9/ICoqj/E8reGAYIBlYDi3yFxDCuQaY0oqJg=; b=oWtVe8kqOKvx1mb1CUVGSPYmsElUzI+sUjuUbP/0XJ68Qknwhhyqo/zHCd2YV+YFeF AdCP03z7mUTvOxR91N10tJXQ8yDBtuZvcV2YqgU3ZWTkus1fYiF4ODrD6VysEhWK/xkc rjeNGjLL6QcZFmD/94HdBJegXwmuc7cdovd5RX8tzUNWN3UgS/8b2MVWugKkLxsIeOIC QlDm8gDrdLT/KEPjlrIS7oMFC1l1nVgHJsoCI8mMbH95+4H+P4NOs+9/5PEt8aLkFXFn PSxKirUfxGXfT/K/6xNuplWQittjrqCwuGfV58nQl8qrCFI85Bgw4YyvnbqO2NxqlmBN 4YQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041614; x=1714646414; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VCI8k2+9/ICoqj/E8reGAYIBlYDi3yFxDCuQaY0oqJg=; b=wGG4KZSvSRXvkI2TEpxF597Ii4dbB8ElSem5bI7s2nIhL0dUv1KbRWFPtLASFEDQ5f l6coq6Mwkg/7r2CCeny70ZdwsvNuu6lsSo/17o1vpQsmis2qf+agQQwwMaOUIAyMebm4 AD4eAOhT60Ugtk7gYVx7bTtHOGpCTX3RWFaNUY2ndnRsnL0H3dkFwJxovRlEvsfUnILD CWq/TbpnIdW9efrY/DlzKDPscL7XHDSNMYArHBDb9qA7tES7+ALwIBv4ndKCYZlC2cqV ZikNLXdLdfko1th6tCumnzoycXXAnFl5p2rN+oKn/dWNUujFOmdJB6PnlhclZt5ItevF 804Q== X-Gm-Message-State: AOJu0Yx5RT0shAr0ySaWkslf6qggWrAzQyyZMgMTv49BhW/yyisgA4s6 +zgSX0X/6Iv7XQMCwQ28fhTwrzJvAP0xVFNU/hCfeL4rA1oY2eWhkI4kke2TA/PtlrXJE57748X O X-Google-Smtp-Source: AGHT+IFF54hDTgIQrz26/ZQmWmX6FYAO8P7vcp0OmfXBS4q25tJSnB1vU3Rkzm+lPZDoKV5GnGiG3w== X-Received: by 2002:a5d:4746:0:b0:349:f83f:9ebf with SMTP id o6-20020a5d4746000000b00349f83f9ebfmr4958412wrs.5.1714041614439; Thu, 25 Apr 2024 03:40:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/37] allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset Date: Thu, 25 Apr 2024 11:39:49 +0100 Message-Id: <20240425103958.3237225-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041999975100037 Content-Type: text/plain; charset="utf-8" Rather than directly calling the device's implementation of its 'hold' reset phase, call device_cold_reset(). This means we don't have to adjust this callsite when we add another argument to the function signature for the hold and exit reset methods. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Message-id: 20240412160809.1260625-3-peter.maydell@linaro.org --- hw/i2c/allwinner-i2c.c | 3 +-- hw/sensor/adm1272.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c index 8abcc39a5c2..96c20c86372 100644 --- a/hw/i2c/allwinner-i2c.c +++ b/hw/i2c/allwinner-i2c.c @@ -385,8 +385,7 @@ static void allwinner_i2c_write(void *opaque, hwaddr of= fset, break; case TWI_SRST_REG: if (((value & TWI_SRST_MASK) =3D=3D 0) && (s->srst & TWI_SRST_MASK= )) { - /* Perform reset */ - allwinner_i2c_reset_hold(OBJECT(s)); + device_cold_reset(DEVICE(s)); } s->srst =3D value & TWI_SRST_MASK; break; diff --git a/hw/sensor/adm1272.c b/hw/sensor/adm1272.c index 1f7c8abb838..a19557ec9ea 100644 --- a/hw/sensor/adm1272.c +++ b/hw/sensor/adm1272.c @@ -386,7 +386,7 @@ static int adm1272_write_data(PMBusDevice *pmdev, const= uint8_t *buf, break; =20 case ADM1272_MFR_POWER_CYCLE: - adm1272_exit_reset((Object *)s); + device_cold_reset(DEVICE(s)); break; =20 case ADM1272_HYSTERESIS_LOW: --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041762; cv=none; d=zohomail.com; s=zohoarc; b=SKAF/W9iFUhX7g3hHoayeRo9uhFgJfZSDg/YtHNBLb4uah+3LtYaapNPax5GCTxJ8YFQeGhvZfBbwiL7Q+S7FTBzjlDgjFcKNo4Zk1b08h08jkK0n0DthxrS2NYvpt4WANsc7ZfjRbhR1OneAUF257RLyCWHIcXxkY42Fs3N8y8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041762; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=IZveBcQ/I3Ep99MpkKq6qvJrHhr8FNS0mASz7sTHHrA=; b=oB6+/4iqlp/wtH0ewKlcvIGjdoQeRy5AY5BZ2HS2WVcQPCCmXOI1i59q6g64nQhtX3vXRWyUObNYavU//w23rGuLiI6vf+Ay33ntEtKzY1SCpmEf3LwXxUiwLHzRKis4xQDjQ/ebfriYTs2Z9mYkiZCXV6ALMG3KnEU/22stdfs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041762229565.5667707972607; Thu, 25 Apr 2024 03:42:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWe-0002Mt-Ny; Thu, 25 Apr 2024 06:40:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWa-00026V-0m for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:20 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWW-0007EJ-Mx for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:19 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-34a4772d5easo741358f8f.0 for ; Thu, 25 Apr 2024 03:40:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041615; x=1714646415; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IZveBcQ/I3Ep99MpkKq6qvJrHhr8FNS0mASz7sTHHrA=; b=CLAFJ662SqhQqARHFMWY5C8BzeVQ9FLTIKr1RGR3radWYd1NB3M085WAbArXU/80+F cGDA5yjIO8DaEglxtHf0a7PBz1uDB3ELOMPBirxftBLr4DAIM+FPnkBitPoojVF89Rd+ EXhU3ENiucjuCP/Wt2nbcTl7jlO5bVHK48/Od6UxQqj4lVoXBpqPOnzErDt+s20WC9iY gzCycF+jsHw65oPXRHkEZcjqkCx7wOoTqiZD48ViwnosTYGgCVlmiEkV6buqhTJ9qnob p3LTUgRV8p+2DiEBl6UeMLL+GXBXEAjbCnXzmwQ71NfyZL2Dr3Qr+rEF96AoV7JnlfCo Mu4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041615; x=1714646415; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IZveBcQ/I3Ep99MpkKq6qvJrHhr8FNS0mASz7sTHHrA=; b=JM+Ei237Oz/EnEChHJLHWjKlv2xL7ebv13rBq1um7eKzu1mrPHFiYTyxx+0qUEVY/i Hit9b/hXAW5FXtZqIv/yVwEIerdkL+0JjDLPEcgIp4guraJZZEOoQVC9ofnCs5NO8Ot1 G3w/6v5MOpdsCeyb5BwOpqYQskKkQjytjoQTTjjjY7JMWOVXWZ/20j7aTd2Z7/G06L+B MqyN7mtpNtLPa6OaLyYdsBgcUvirGEFOny3EnPEdhV3CXCuEfp4fRmAFQL/5FHUF3XZJ Z7+s8GMxXhYQf0uhQiDruZBIttaY6T+1GS6xh6aBr8d+Q41+XQ1VaCjjK7K/Ccb8UFKW OKeg== X-Gm-Message-State: AOJu0YwxP+TihJbdrZTUf1cRKCGl8c0BVn20Sc1xECk7Puo8lBr+/ADM BOm2kH/AWAf001NDux60nHKQ1GWyAKAxTmoK4/iXgxwSQwMoR+IWSjGL35Cly3qtdoWesBv9QQp m X-Google-Smtp-Source: AGHT+IFJlr5Dzu3wMiMHn0mT3eYQrVzr0daLa+ORokaf1E6CrsWOmVbd4HAkeBO90iPrW8MRQTBa2w== X-Received: by 2002:adf:e8c7:0:b0:343:c6d1:280d with SMTP id k7-20020adfe8c7000000b00343c6d1280dmr3560511wrn.21.1714041614901; Thu, 25 Apr 2024 03:40:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/37] scripts/coccinelle: New script to add ResetType to hold and exit phases Date: Thu, 25 Apr 2024 11:39:50 +0100 Message-Id: <20240425103958.3237225-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041763414100003 Content-Type: text/plain; charset="utf-8" We pass a ResetType argument to the Resettable class enter phase method, but we don't pass it to hold and exit, even though the callsites have it readily available. This means that if a device cared about the ResetType it would need to record it in the enter phase method to use later on. We should pass the type to all three of the phase methods to avoid having to do that. This coccinelle script adds the ResetType argument to the hold and exit phases of the Resettable interface. The first part of the script (rules holdfn_assigned, holdfn_defined, exitfn_assigned, exitfn_defined) update implementations of the interface within device models, both to change the signature of their method implementations and to pass on the reset type when they invoke reset on some other device. The second part of the script is various special cases: * method callsites in resettable_phase_hold(), resettable_phase_exit() and device_phases_reset() * updating the typedefs for the methods * isl_pmbus_vr.c has some code where one device's reset method directly calls the implementation of a different device's method Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Message-id: 20240412160809.1260625-4-peter.maydell@linaro.org --- scripts/coccinelle/reset-type.cocci | 133 ++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 scripts/coccinelle/reset-type.cocci diff --git a/scripts/coccinelle/reset-type.cocci b/scripts/coccinelle/reset= -type.cocci new file mode 100644 index 00000000000..14abdd7bd0c --- /dev/null +++ b/scripts/coccinelle/reset-type.cocci @@ -0,0 +1,133 @@ +// Convert device code using three-phase reset to add a ResetType +// argument to implementations of ResettableHoldPhase and +// ResettableEnterPhase methods. +// +// Copyright Linaro Ltd 2024 +// SPDX-License-Identifier: GPL-2.0-or-later +// +// for dir in include hw target; do \ +// spatch --macro-file scripts/cocci-macro-file.h \ +// --sp-file scripts/coccinelle/reset-type.cocci \ +// --keep-comments --smpl-spacing --in-place --include-headers \ +// --dir $dir; done +// +// This coccinelle script aims to produce a complete change that needs +// no human interaction, so as well as the generic "update device +// implementations of the hold and exit phase methods" it includes +// the special-case transformations needed for the core code and for +// one device model that does something a bit nonstandard. Those +// special cases are at the end of the file. + +// Look for where we use a function as a ResettableHoldPhase method, +// either by directly assigning it to phases.hold or by calling +// resettable_class_set_parent_phases, and remember the function name. +@ holdfn_assigned @ +identifier enterfn, holdfn, exitfn; +identifier rc; +expression e; +@@ +ResettableClass *rc; +... +( + rc->phases.hold =3D holdfn; +| + resettable_class_set_parent_phases(rc, enterfn, holdfn, exitfn, e); +) + +// Look for the definition of the function we found in holdfn_assigned, +// and add the new argument. If the function calls a hold function +// itself (probably chaining to the parent class reset) then add the +// new argument there too. +@ holdfn_defined @ +identifier holdfn_assigned.holdfn; +typedef Object; +identifier obj; +expression parent; +@@ +-holdfn(Object *obj) ++holdfn(Object *obj, ResetType type) +{ + <... +- parent.hold(obj) ++ parent.hold(obj, type) + ...> +} + +// Similarly for ResettableExitPhase. +@ exitfn_assigned @ +identifier enterfn, holdfn, exitfn; +identifier rc; +expression e; +@@ +ResettableClass *rc; +... +( + rc->phases.exit =3D exitfn; +| + resettable_class_set_parent_phases(rc, enterfn, holdfn, exitfn, e); +) +@ exitfn_defined @ +identifier exitfn_assigned.exitfn; +typedef Object; +identifier obj; +expression parent; +@@ +-exitfn(Object *obj) ++exitfn(Object *obj, ResetType type) +{ + <... +- parent.exit(obj) ++ parent.exit(obj, type) + ...> +} + +// SPECIAL CASES ONLY BELOW HERE +// We use a python scripted constraint on the position of the match +// to ensure that they only match in a particular function. See +// https://public-inbox.org/git/alpine.DEB.2.21.1808240652370.2344@hadrien/ +// which recommends this as the way to do "match only in this function". + +// Special case: isl_pmbus_vr.c has some reset methods calling others dire= ctly +@ isl_pmbus_vr @ +identifier obj; +@@ +- isl_pmbus_vr_exit_reset(obj); ++ isl_pmbus_vr_exit_reset(obj, type); + +// Special case: device_phases_reset() needs to pass RESET_TYPE_COLD +@ device_phases_reset_hold @ +expression obj; +identifier rc; +identifier phase; +position p : script:python() { p[0].current_element =3D=3D "device_phases_= reset" }; +@@ +- rc->phases.phase(obj)@p ++ rc->phases.phase(obj, RESET_TYPE_COLD) + +// Special case: in resettable_phase_hold() and resettable_phase_exit() +// we need to pass through the ResetType argument to the method being call= ed +@ resettable_phase_hold @ +expression obj; +identifier rc; +position p : script:python() { p[0].current_element =3D=3D "resettable_pha= se_hold" }; +@@ +- rc->phases.hold(obj)@p ++ rc->phases.hold(obj, type) +@ resettable_phase_exit @ +expression obj; +identifier rc; +position p : script:python() { p[0].current_element =3D=3D "resettable_pha= se_exit" }; +@@ +- rc->phases.exit(obj)@p ++ rc->phases.exit(obj, type) +// Special case: the typedefs for the methods need to declare the new argu= ment +@ phase_typedef_hold @ +identifier obj; +@@ +- typedef void (*ResettableHoldPhase)(Object *obj); ++ typedef void (*ResettableHoldPhase)(Object *obj, ResetType type); +@ phase_typedef_exit @ +identifier obj; +@@ +- typedef void (*ResettableExitPhase)(Object *obj); ++ typedef void (*ResettableExitPhase)(Object *obj, ResetType type); --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041772; cv=none; d=zohomail.com; s=zohoarc; b=jkMF+pEhouEm19ic+ZM2GdhWiUckQDL81UZgYdp8yFXkENIs3ZE+Dapm3h5N3txAmwPhJzaYyy9y5vPkKupJ7mXcO33IA2WLcZMC5w65JGRKFFAFop7vzYvmhNH4No/hG4U+8Y7ucLeTCE0AZ34Km22RGnUjdfmYwWb3SmJ8U2I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041772; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=usqTyuhd4ZHCj44xCBnwXB6CC08SjV0kVyVlX55Byrw=; b=OitAinX+Hsq6WHlt/haQ+6qfTeBGRASHAuCtC/+vKp3QSrCIFfmq5Qh+Kz+fmfnJyqX5kF/rXrkljm6/yAOwvJRMI/haRQEjsy73Dw8ucIvw+8CsGjDCfXjF3k4UFpEKz+j1+hAdEgwDIJSfY/TqUPPdkXvwRQARUf622qkMNCY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714041772335182.6907305960607; Thu, 25 Apr 2024 03:42:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWg-0002Rd-VU; Thu, 25 Apr 2024 06:40:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWd-0002KF-L0 for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:23 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWY-0007Eq-8c for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:23 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-34c1a17da03so250243f8f.0 for ; Thu, 25 Apr 2024 03:40:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041616; x=1714646416; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=usqTyuhd4ZHCj44xCBnwXB6CC08SjV0kVyVlX55Byrw=; b=SMkglc6IVfPL+ZxS3e+Llcd7sJXMrCVipEsbwGLitRMth6bTlP7vswN68e3Wu3nMgJ eANAHSZXDaTXKQpSrA6hy1d02W9pPIgPKis7O5/dQxw2u/w18Mz5vYhhgx8gQMrELnwl pqSH7gWtmORWelrghXIRfIC3VTFYpBw24U1rwP1EzBLMPp6mde+8/V6wY58lGLDUdhd3 EkHreh5QJx0cNHLiKJbqvePqnFMd01HRxZzSqh1+b9tVr08ADz4ZOewN5Gn2KwuNR+9z rizD9Xy6AGOSdaAiX0wX0NkXQV+CNUMHrSSeaNhKEP+zWF0ZqavajvXLpTUxzLcW2XhX eqFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041616; x=1714646416; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=usqTyuhd4ZHCj44xCBnwXB6CC08SjV0kVyVlX55Byrw=; b=IYvW4lg/BWGqpm2cU8CnD7Yl066NlHFdPrATg2GX+HJ9alBCFXLSFo1o31RKcyG6Tp IoeBxigcxoXTJHxtYdqlzlYeIG4S4e7iXwBMY5sNIM7A453MBFM0AJlykx/N+DkA0mgp wCVKd3ShP18QIo3yor2m8/ucj/h3/zLw+7/D8VA5F1Yr8Xl2zlrr5yfU+6Sq8dgB8rFH 4zyD8rInbe+vWi+bzrJ6ROs3xSUwJzG4GSX6O+vWQY1DM+ohfPGX9m+u1sgdUa5dI1aZ Z+BCcEmAyRJfRNwjSrfGdJqrKW8+VEbifgKza3pqlnyZmyne2tn0s3Ft6RLsC1h8/jaQ 0pcQ== X-Gm-Message-State: AOJu0YzOtsXEiXEY/gxcNPvBeOY9Yh4q+fmnhVJkaiEuOK2tDsjOOfAq 1tS5uyaGLPkcOjKV3lJ+RjDz0T/cz2HW2x+TkKUtdDsoDa/E5+tm/DIncuF6ftVYH7daM/QKDEL R X-Google-Smtp-Source: AGHT+IFuXsKMysiACY6ev8AXd257IldyDwXoKTifS3m8s7rbybU0XHqxlKCELSlI/h1QK3yitBbyAw== X-Received: by 2002:a05:6000:1e88:b0:34c:1c1e:a322 with SMTP id dd8-20020a0560001e8800b0034c1c1ea322mr984003wrb.22.1714041615516; Thu, 25 Apr 2024 03:40:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/37] hw, target: Add ResetType argument to hold and exit phase methods Date: Thu, 25 Apr 2024 11:39:51 +0100 Message-Id: <20240425103958.3237225-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041773542100001 Content-Type: text/plain; charset="utf-8" We pass a ResetType argument to the Resettable class enter phase method, but we don't pass it to hold and exit, even though the callsites have it readily available. This means that if a device cared about the ResetType it would need to record it in the enter phase method to use later on. Pass the type to all three of the phase methods to avoid having to do that. Commit created with for dir in hw target include; do \ spatch --macro-file scripts/cocci-macro-file.h \ --sp-file scripts/coccinelle/reset-type.cocci \ --keep-comments --smpl-spacing --in-place \ --include-headers --dir $dir; done and no manual edits. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Message-id: 20240412160809.1260625-5-peter.maydell@linaro.org --- include/hw/resettable.h | 4 ++-- hw/adc/npcm7xx_adc.c | 2 +- hw/arm/pxa2xx_pic.c | 2 +- hw/arm/smmu-common.c | 2 +- hw/arm/smmuv3.c | 4 ++-- hw/arm/stellaris.c | 10 +++++----- hw/audio/asc.c | 2 +- hw/char/cadence_uart.c | 2 +- hw/char/sifive_uart.c | 2 +- hw/core/cpu-common.c | 2 +- hw/core/qdev.c | 4 ++-- hw/core/reset.c | 2 +- hw/core/resettable.c | 4 ++-- hw/display/virtio-vga.c | 4 ++-- hw/gpio/npcm7xx_gpio.c | 2 +- hw/gpio/pl061.c | 2 +- hw/gpio/stm32l4x5_gpio.c | 2 +- hw/hyperv/vmbus.c | 2 +- hw/i2c/allwinner-i2c.c | 2 +- hw/i2c/npcm7xx_smbus.c | 2 +- hw/input/adb.c | 2 +- hw/input/ps2.c | 12 ++++++------ hw/intc/arm_gic_common.c | 2 +- hw/intc/arm_gic_kvm.c | 4 ++-- hw/intc/arm_gicv3_common.c | 2 +- hw/intc/arm_gicv3_its.c | 4 ++-- hw/intc/arm_gicv3_its_common.c | 2 +- hw/intc/arm_gicv3_its_kvm.c | 4 ++-- hw/intc/arm_gicv3_kvm.c | 4 ++-- hw/intc/xics.c | 2 +- hw/m68k/q800-glue.c | 2 +- hw/misc/djmemc.c | 2 +- hw/misc/iosb.c | 2 +- hw/misc/mac_via.c | 8 ++++---- hw/misc/macio/cuda.c | 4 ++-- hw/misc/macio/pmu.c | 4 ++-- hw/misc/mos6522.c | 2 +- hw/misc/npcm7xx_mft.c | 2 +- hw/misc/npcm7xx_pwm.c | 2 +- hw/misc/stm32l4x5_exti.c | 2 +- hw/misc/stm32l4x5_rcc.c | 10 +++++----- hw/misc/stm32l4x5_syscfg.c | 2 +- hw/misc/xlnx-versal-cframe-reg.c | 2 +- hw/misc/xlnx-versal-crl.c | 2 +- hw/misc/xlnx-versal-pmc-iou-slcr.c | 2 +- hw/misc/xlnx-versal-trng.c | 2 +- hw/misc/xlnx-versal-xramc.c | 2 +- hw/misc/xlnx-zynqmp-apu-ctrl.c | 2 +- hw/misc/xlnx-zynqmp-crf.c | 2 +- hw/misc/zynq_slcr.c | 4 ++-- hw/net/can/xlnx-zynqmp-can.c | 2 +- hw/net/e1000.c | 2 +- hw/net/e1000e.c | 2 +- hw/net/igb.c | 2 +- hw/net/igbvf.c | 2 +- hw/nvram/xlnx-bbram.c | 2 +- hw/nvram/xlnx-versal-efuse-ctrl.c | 2 +- hw/nvram/xlnx-zynqmp-efuse.c | 2 +- hw/pci-bridge/cxl_root_port.c | 4 ++-- hw/pci-bridge/pcie_root_port.c | 2 +- hw/pci-host/bonito.c | 2 +- hw/pci-host/pnv_phb.c | 4 ++-- hw/pci-host/pnv_phb3_msi.c | 4 ++-- hw/pci/pci.c | 4 ++-- hw/rtc/mc146818rtc.c | 2 +- hw/s390x/css-bridge.c | 2 +- hw/sensor/adm1266.c | 2 +- hw/sensor/adm1272.c | 2 +- hw/sensor/isl_pmbus_vr.c | 10 +++++----- hw/sensor/max31785.c | 2 +- hw/sensor/max34451.c | 2 +- hw/ssi/npcm7xx_fiu.c | 2 +- hw/timer/etraxfs_timer.c | 2 +- hw/timer/npcm7xx_timer.c | 2 +- hw/usb/hcd-dwc2.c | 8 ++++---- hw/usb/xlnx-versal-usb2-ctrl-regs.c | 2 +- hw/virtio/virtio-pci.c | 2 +- target/arm/cpu.c | 4 ++-- target/avr/cpu.c | 4 ++-- target/cris/cpu.c | 4 ++-- target/hexagon/cpu.c | 4 ++-- target/i386/cpu.c | 4 ++-- target/loongarch/cpu.c | 4 ++-- target/m68k/cpu.c | 4 ++-- target/microblaze/cpu.c | 4 ++-- target/mips/cpu.c | 4 ++-- target/openrisc/cpu.c | 4 ++-- target/ppc/cpu_init.c | 4 ++-- target/riscv/cpu.c | 4 ++-- target/rx/cpu.c | 4 ++-- target/sh4/cpu.c | 4 ++-- target/sparc/cpu.c | 4 ++-- target/tricore/cpu.c | 4 ++-- target/xtensa/cpu.c | 4 ++-- 94 files changed, 150 insertions(+), 150 deletions(-) diff --git a/include/hw/resettable.h b/include/hw/resettable.h index bdcd1276b69..3161e471c9b 100644 --- a/include/hw/resettable.h +++ b/include/hw/resettable.h @@ -103,8 +103,8 @@ typedef enum ResetType { * the callback. */ typedef void (*ResettableEnterPhase)(Object *obj, ResetType type); -typedef void (*ResettableHoldPhase)(Object *obj); -typedef void (*ResettableExitPhase)(Object *obj); +typedef void (*ResettableHoldPhase)(Object *obj, ResetType type); +typedef void (*ResettableExitPhase)(Object *obj, ResetType type); typedef ResettableState * (*ResettableGetState)(Object *obj); typedef void (*ResettableTrFunction)(Object *obj); typedef ResettableTrFunction (*ResettableGetTrFunction)(Object *obj); diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c index c6647eec6d7..de8469dae4f 100644 --- a/hw/adc/npcm7xx_adc.c +++ b/hw/adc/npcm7xx_adc.c @@ -218,7 +218,7 @@ static void npcm7xx_adc_enter_reset(Object *obj, ResetT= ype type) npcm7xx_adc_reset(s); } =20 -static void npcm7xx_adc_hold_reset(Object *obj) +static void npcm7xx_adc_hold_reset(Object *obj, ResetType type) { NPCM7xxADCState *s =3D NPCM7XX_ADC(obj); =20 diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index f54546cd4df..34c5555dba9 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -272,7 +272,7 @@ static int pxa2xx_pic_post_load(void *opaque, int versi= on_id) return 0; } =20 -static void pxa2xx_pic_reset_hold(Object *obj) +static void pxa2xx_pic_reset_hold(Object *obj, ResetType type) { PXA2xxPICState *s =3D PXA2XX_PIC(obj); =20 diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index c4b540656c1..1ce706bf94b 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -682,7 +682,7 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) } } =20 -static void smmu_base_reset_hold(Object *obj) +static void smmu_base_reset_hold(Object *obj, ResetType type) { SMMUState *s =3D ARM_SMMU(obj); =20 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 9eb56a70f39..2d1e0d55ec2 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1727,13 +1727,13 @@ static void smmu_init_irq(SMMUv3State *s, SysBusDev= ice *dev) } } =20 -static void smmu_reset_hold(Object *obj) +static void smmu_reset_hold(Object *obj, ResetType type) { SMMUv3State *s =3D ARM_SMMUV3(obj); SMMUv3Class *c =3D ARM_SMMUV3_GET_CLASS(s); =20 if (c->parent_phases.hold) { - c->parent_phases.hold(obj); + c->parent_phases.hold(obj, type); } =20 smmuv3_init_regs(s); diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index a2f998bf9e2..376746251e6 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -394,7 +394,7 @@ static void stellaris_sys_reset_enter(Object *obj, Rese= tType type) s->dcgc[0] =3D 1; } =20 -static void stellaris_sys_reset_hold(Object *obj) +static void stellaris_sys_reset_hold(Object *obj, ResetType type) { ssys_state *s =3D STELLARIS_SYS(obj); =20 @@ -402,7 +402,7 @@ static void stellaris_sys_reset_hold(Object *obj) ssys_calculate_system_clock(s, true); } =20 -static void stellaris_sys_reset_exit(Object *obj) +static void stellaris_sys_reset_exit(Object *obj, ResetType type) { } =20 @@ -618,7 +618,7 @@ static void stellaris_i2c_reset_enter(Object *obj, Rese= tType type) i2c_end_transfer(s->bus); } =20 -static void stellaris_i2c_reset_hold(Object *obj) +static void stellaris_i2c_reset_hold(Object *obj, ResetType type) { stellaris_i2c_state *s =3D STELLARIS_I2C(obj); =20 @@ -631,7 +631,7 @@ static void stellaris_i2c_reset_hold(Object *obj) s->mcr =3D 0; } =20 -static void stellaris_i2c_reset_exit(Object *obj) +static void stellaris_i2c_reset_exit(Object *obj, ResetType type) { stellaris_i2c_state *s =3D STELLARIS_I2C(obj); =20 @@ -787,7 +787,7 @@ static void stellaris_adc_trigger(void *opaque, int irq= , int level) } } =20 -static void stellaris_adc_reset_hold(Object *obj) +static void stellaris_adc_reset_hold(Object *obj, ResetType type) { StellarisADCState *s =3D STELLARIS_ADC(obj); int n; diff --git a/hw/audio/asc.c b/hw/audio/asc.c index 87b56243262..805416372c2 100644 --- a/hw/audio/asc.c +++ b/hw/audio/asc.c @@ -610,7 +610,7 @@ static void asc_fifo_init(ASCFIFOState *fs, int index) g_free(name); } =20 -static void asc_reset_hold(Object *obj) +static void asc_reset_hold(Object *obj, ResetType type) { ASCState *s =3D ASC(obj); =20 diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index db31d7cc859..77d9a2a221f 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -525,7 +525,7 @@ static void cadence_uart_reset_init(Object *obj, ResetT= ype type) s->r[R_TTRIG] =3D 0x00000020; } =20 -static void cadence_uart_reset_hold(Object *obj) +static void cadence_uart_reset_hold(Object *obj, ResetType type) { CadenceUARTState *s =3D CADENCE_UART(obj); =20 diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index e8716c42523..7fc6787f690 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -214,7 +214,7 @@ static void sifive_uart_reset_enter(Object *obj, ResetT= ype type) s->rx_fifo_len =3D 0; } =20 -static void sifive_uart_reset_hold(Object *obj) +static void sifive_uart_reset_hold(Object *obj, ResetType type) { SiFiveUARTState *s =3D SIFIVE_UART(obj); qemu_irq_lower(s->irq); diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 4bd9c70a83f..a72d48d9e17 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -113,7 +113,7 @@ void cpu_reset(CPUState *cpu) trace_cpu_reset(cpu->cpu_index); } =20 -static void cpu_common_reset_hold(Object *obj) +static void cpu_common_reset_hold(Object *obj, ResetType type) { CPUState *cpu =3D CPU(obj); CPUClass *cc =3D CPU_GET_CLASS(cpu); diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 00efaf1bd10..f3a996f57de 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -760,10 +760,10 @@ static void device_phases_reset(DeviceState *dev) rc->phases.enter(OBJECT(dev), RESET_TYPE_COLD); } if (rc->phases.hold) { - rc->phases.hold(OBJECT(dev)); + rc->phases.hold(OBJECT(dev), RESET_TYPE_COLD); } if (rc->phases.exit) { - rc->phases.exit(OBJECT(dev)); + rc->phases.exit(OBJECT(dev), RESET_TYPE_COLD); } } =20 diff --git a/hw/core/reset.c b/hw/core/reset.c index d50da7e3041..f9fef45e050 100644 --- a/hw/core/reset.c +++ b/hw/core/reset.c @@ -73,7 +73,7 @@ static ResettableState *legacy_reset_get_state(Object *ob= j) return &lr->reset_state; } =20 -static void legacy_reset_hold(Object *obj) +static void legacy_reset_hold(Object *obj, ResetType type) { LegacyReset *lr =3D LEGACY_RESET(obj); =20 diff --git a/hw/core/resettable.c b/hw/core/resettable.c index c3df75c6ba8..bebf7f10b26 100644 --- a/hw/core/resettable.c +++ b/hw/core/resettable.c @@ -181,7 +181,7 @@ static void resettable_phase_hold(Object *obj, void *op= aque, ResetType type) trace_resettable_transitional_function(obj, obj_typename); tr_func(obj); } else if (rc->phases.hold) { - rc->phases.hold(obj); + rc->phases.hold(obj, type); } } trace_resettable_phase_hold_end(obj, obj_typename, s->count); @@ -204,7 +204,7 @@ static void resettable_phase_exit(Object *obj, void *op= aque, ResetType type) if (--s->count =3D=3D 0) { trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.e= xit); if (rc->phases.exit && !resettable_get_tr_func(rc, obj)) { - rc->phases.exit(obj); + rc->phases.exit(obj, type); } } s->exit_phase_in_progress =3D false; diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c index 94d3353f540..276f315108b 100644 --- a/hw/display/virtio-vga.c +++ b/hw/display/virtio-vga.c @@ -180,14 +180,14 @@ static void virtio_vga_base_realize(VirtIOPCIProxy *v= pci_dev, Error **errp) } } =20 -static void virtio_vga_base_reset_hold(Object *obj) +static void virtio_vga_base_reset_hold(Object *obj, ResetType type) { VirtIOVGABaseClass *klass =3D VIRTIO_VGA_BASE_GET_CLASS(obj); VirtIOVGABase *vvga =3D VIRTIO_VGA_BASE(obj); =20 /* reset virtio-gpu */ if (klass->parent_phases.hold) { - klass->parent_phases.hold(obj); + klass->parent_phases.hold(obj, type); } =20 /* reset vga */ diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c index 6e70ac1f24b..ba19b9ebad3 100644 --- a/hw/gpio/npcm7xx_gpio.c +++ b/hw/gpio/npcm7xx_gpio.c @@ -352,7 +352,7 @@ static void npcm7xx_gpio_enter_reset(Object *obj, Reset= Type type) s->regs[NPCM7XX_GPIO_ODSC] =3D s->reset_odsc; } =20 -static void npcm7xx_gpio_hold_reset(Object *obj) +static void npcm7xx_gpio_hold_reset(Object *obj, ResetType type) { NPCM7xxGPIOState *s =3D NPCM7XX_GPIO(obj); =20 diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 86f23836553..d5838b8e98d 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -484,7 +484,7 @@ static void pl061_enter_reset(Object *obj, ResetType ty= pe) s->amsel =3D 0; } =20 -static void pl061_hold_reset(Object *obj) +static void pl061_hold_reset(Object *obj, ResetType type) { PL061State *s =3D PL061(obj); int i, level; diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c index 63b8763e9d3..71bf5fddb2a 100644 --- a/hw/gpio/stm32l4x5_gpio.c +++ b/hw/gpio/stm32l4x5_gpio.c @@ -70,7 +70,7 @@ static bool is_push_pull(Stm32l4x5GpioState *s, unsigned = pin) return extract32(s->otyper, pin, 1) =3D=3D 0; } =20 -static void stm32l4x5_gpio_reset_hold(Object *obj) +static void stm32l4x5_gpio_reset_hold(Object *obj, ResetType type) { Stm32l4x5GpioState *s =3D STM32L4X5_GPIO(obj); =20 diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c index f33afeeea27..490d805d298 100644 --- a/hw/hyperv/vmbus.c +++ b/hw/hyperv/vmbus.c @@ -2453,7 +2453,7 @@ static void vmbus_unrealize(BusState *bus) qemu_mutex_destroy(&vmbus->rx_queue_lock); } =20 -static void vmbus_reset_hold(Object *obj) +static void vmbus_reset_hold(Object *obj, ResetType type) { vmbus_deinit(VMBUS(obj)); } diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c index 96c20c86372..16f1d6d40e7 100644 --- a/hw/i2c/allwinner-i2c.c +++ b/hw/i2c/allwinner-i2c.c @@ -170,7 +170,7 @@ static inline bool allwinner_i2c_interrupt_is_enabled(A= WI2CState *s) return s->cntr & TWI_CNTR_INT_EN; } =20 -static void allwinner_i2c_reset_hold(Object *obj) +static void allwinner_i2c_reset_hold(Object *obj, ResetType type) { AWI2CState *s =3D AW_I2C(obj); =20 diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c index 0ea3083bb6e..22d68fc67dd 100644 --- a/hw/i2c/npcm7xx_smbus.c +++ b/hw/i2c/npcm7xx_smbus.c @@ -1022,7 +1022,7 @@ static void npcm7xx_smbus_enter_reset(Object *obj, Re= setType type) s->rx_cur =3D 0; } =20 -static void npcm7xx_smbus_hold_reset(Object *obj) +static void npcm7xx_smbus_hold_reset(Object *obj, ResetType type) { NPCM7xxSMBusState *s =3D NPCM7XX_SMBUS(obj); =20 diff --git a/hw/input/adb.c b/hw/input/adb.c index 98f39b4281a..aff7130fd0f 100644 --- a/hw/input/adb.c +++ b/hw/input/adb.c @@ -231,7 +231,7 @@ static const VMStateDescription vmstate_adb_bus =3D { } }; =20 -static void adb_bus_reset_hold(Object *obj) +static void adb_bus_reset_hold(Object *obj, ResetType type) { ADBBusState *adb_bus =3D ADB_BUS(obj); =20 diff --git a/hw/input/ps2.c b/hw/input/ps2.c index 00b695a0b97..d6f834443dd 100644 --- a/hw/input/ps2.c +++ b/hw/input/ps2.c @@ -1007,7 +1007,7 @@ void ps2_write_mouse(PS2MouseState *s, int val) } } =20 -static void ps2_reset_hold(Object *obj) +static void ps2_reset_hold(Object *obj, ResetType type) { PS2State *s =3D PS2_DEVICE(obj); =20 @@ -1015,7 +1015,7 @@ static void ps2_reset_hold(Object *obj) ps2_reset_queue(s); } =20 -static void ps2_reset_exit(Object *obj) +static void ps2_reset_exit(Object *obj, ResetType type) { PS2State *s =3D PS2_DEVICE(obj); =20 @@ -1048,7 +1048,7 @@ static void ps2_common_post_load(PS2State *s) q->cwptr =3D ccount ? (q->rptr + ccount) & (PS2_BUFFER_SIZE - 1) : -1; } =20 -static void ps2_kbd_reset_hold(Object *obj) +static void ps2_kbd_reset_hold(Object *obj, ResetType type) { PS2DeviceClass *ps2dc =3D PS2_DEVICE_GET_CLASS(obj); PS2KbdState *s =3D PS2_KBD_DEVICE(obj); @@ -1056,7 +1056,7 @@ static void ps2_kbd_reset_hold(Object *obj) trace_ps2_kbd_reset(s); =20 if (ps2dc->parent_phases.hold) { - ps2dc->parent_phases.hold(obj); + ps2dc->parent_phases.hold(obj, type); } =20 s->scan_enabled =3D 1; @@ -1065,7 +1065,7 @@ static void ps2_kbd_reset_hold(Object *obj) s->modifiers =3D 0; } =20 -static void ps2_mouse_reset_hold(Object *obj) +static void ps2_mouse_reset_hold(Object *obj, ResetType type) { PS2DeviceClass *ps2dc =3D PS2_DEVICE_GET_CLASS(obj); PS2MouseState *s =3D PS2_MOUSE_DEVICE(obj); @@ -1073,7 +1073,7 @@ static void ps2_mouse_reset_hold(Object *obj) trace_ps2_mouse_reset(s); =20 if (ps2dc->parent_phases.hold) { - ps2dc->parent_phases.hold(obj); + ps2dc->parent_phases.hold(obj, type); } =20 s->mouse_status =3D 0; diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 94c173cb071..53fb2c4e2d3 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -263,7 +263,7 @@ static inline void arm_gic_common_reset_irq_state(GICSt= ate *s, int cidx, } } =20 -static void arm_gic_common_reset_hold(Object *obj) +static void arm_gic_common_reset_hold(Object *obj, ResetType type) { GICState *s =3D ARM_GIC_COMMON(obj); int i, j; diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index e0d9e512a37..53defee7d59 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -473,13 +473,13 @@ static void kvm_arm_gic_get(GICState *s) } } =20 -static void kvm_arm_gic_reset_hold(Object *obj) +static void kvm_arm_gic_reset_hold(Object *obj, ResetType type) { GICState *s =3D ARM_GIC_COMMON(obj); KVMARMGICClass *kgc =3D KVM_ARM_GIC_GET_CLASS(s); =20 if (kgc->parent_phases.hold) { - kgc->parent_phases.hold(obj); + kgc->parent_phases.hold(obj, type); } =20 if (kvm_arm_gic_can_save_restore(s)) { diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 207f8417e1f..bd50a1b0795 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -495,7 +495,7 @@ static void arm_gicv3_finalize(Object *obj) g_free(s->redist_region_count); } =20 -static void arm_gicv3_common_reset_hold(Object *obj) +static void arm_gicv3_common_reset_hold(Object *obj, ResetType type) { GICv3State *s =3D ARM_GICV3_COMMON(obj); int i; diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 52e9aca9c65..bf31158470e 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1950,13 +1950,13 @@ static void gicv3_arm_its_realize(DeviceState *dev,= Error **errp) } } =20 -static void gicv3_its_reset_hold(Object *obj) +static void gicv3_its_reset_hold(Object *obj, ResetType type) { GICv3ITSState *s =3D ARM_GICV3_ITS_COMMON(obj); GICv3ITSClass *c =3D ARM_GICV3_ITS_GET_CLASS(s); =20 if (c->parent_phases.hold) { - c->parent_phases.hold(obj); + c->parent_phases.hold(obj, type); } =20 /* Quiescent bit reset to 1 */ diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c index 331d6b93cc1..0b97362cd21 100644 --- a/hw/intc/arm_gicv3_its_common.c +++ b/hw/intc/arm_gicv3_its_common.c @@ -123,7 +123,7 @@ void gicv3_its_init_mmio(GICv3ITSState *s, const Memory= RegionOps *ops, msi_nonbroken =3D true; } =20 -static void gicv3_its_common_reset_hold(Object *obj) +static void gicv3_its_common_reset_hold(Object *obj, ResetType type) { GICv3ITSState *s =3D ARM_GICV3_ITS_COMMON(obj); =20 diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 3befc960db2..35539c099fc 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -197,14 +197,14 @@ static void kvm_arm_its_post_load(GICv3ITSState *s) GITS_CTLR, &s->ctlr, true, &error_abort); } =20 -static void kvm_arm_its_reset_hold(Object *obj) +static void kvm_arm_its_reset_hold(Object *obj, ResetType type) { GICv3ITSState *s =3D ARM_GICV3_ITS_COMMON(obj); KVMARMITSClass *c =3D KVM_ARM_ITS_GET_CLASS(s); int i; =20 if (c->parent_phases.hold) { - c->parent_phases.hold(obj); + c->parent_phases.hold(obj, type); } =20 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 00a383079b9..9ea6b8e2189 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -703,7 +703,7 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const= ARMCPRegInfo *ri) c->icc_ctlr_el1[GICV3_S] =3D c->icc_ctlr_el1[GICV3_NS]; } =20 -static void kvm_arm_gicv3_reset_hold(Object *obj) +static void kvm_arm_gicv3_reset_hold(Object *obj, ResetType type) { GICv3State *s =3D ARM_GICV3_COMMON(obj); KVMARMGICv3Class *kgc =3D KVM_ARM_GICV3_GET_CLASS(s); @@ -711,7 +711,7 @@ static void kvm_arm_gicv3_reset_hold(Object *obj) DPRINTF("Reset\n"); =20 if (kgc->parent_phases.hold) { - kgc->parent_phases.hold(obj); + kgc->parent_phases.hold(obj, type); } =20 if (s->migration_blocker) { diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 700abfa7a62..9b3b7abaea2 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -579,7 +579,7 @@ static void ics_reset_irq(ICSIRQState *irq) irq->saved_priority =3D 0xff; } =20 -static void ics_reset_hold(Object *obj) +static void ics_reset_hold(Object *obj, ResetType type) { ICSState *ics =3D ICS(obj); g_autofree uint8_t *flags =3D g_malloc(ics->nr_irqs); diff --git a/hw/m68k/q800-glue.c b/hw/m68k/q800-glue.c index b5a7713863f..e2ae7c32011 100644 --- a/hw/m68k/q800-glue.c +++ b/hw/m68k/q800-glue.c @@ -175,7 +175,7 @@ static void glue_nmi_release(void *opaque) GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 0); } =20 -static void glue_reset_hold(Object *obj) +static void glue_reset_hold(Object *obj, ResetType type) { GLUEState *s =3D GLUE(obj); =20 diff --git a/hw/misc/djmemc.c b/hw/misc/djmemc.c index 9b69656c3a8..96d5efb5e3a 100644 --- a/hw/misc/djmemc.c +++ b/hw/misc/djmemc.c @@ -96,7 +96,7 @@ static void djmemc_init(Object *obj) sysbus_init_mmio(sbd, &s->mem_regs); } =20 -static void djmemc_reset_hold(Object *obj) +static void djmemc_reset_hold(Object *obj, ResetType type) { DJMEMCState *s =3D DJMEMC(obj); =20 diff --git a/hw/misc/iosb.c b/hw/misc/iosb.c index e20305e8013..31927eaedb4 100644 --- a/hw/misc/iosb.c +++ b/hw/misc/iosb.c @@ -81,7 +81,7 @@ static const MemoryRegionOps iosb_mmio_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void iosb_reset_hold(Object *obj) +static void iosb_reset_hold(Object *obj, ResetType type) { IOSBState *s =3D IOSB(obj); =20 diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index db6142b5f41..652395b84fc 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -1203,7 +1203,7 @@ static int via1_post_load(void *opaque, int version_i= d) } =20 /* VIA 1 */ -static void mos6522_q800_via1_reset_hold(Object *obj) +static void mos6522_q800_via1_reset_hold(Object *obj, ResetType type) { MOS6522Q800VIA1State *v1s =3D MOS6522_Q800_VIA1(obj); MOS6522State *ms =3D MOS6522(v1s); @@ -1211,7 +1211,7 @@ static void mos6522_q800_via1_reset_hold(Object *obj) ADBBusState *adb_bus =3D &v1s->adb_bus; =20 if (mdc->parent_phases.hold) { - mdc->parent_phases.hold(obj); + mdc->parent_phases.hold(obj, type); } =20 ms->timers[0].frequency =3D VIA_TIMER_FREQ; @@ -1359,13 +1359,13 @@ static void mos6522_q800_via2_portB_write(MOS6522St= ate *s) } } =20 -static void mos6522_q800_via2_reset_hold(Object *obj) +static void mos6522_q800_via2_reset_hold(Object *obj, ResetType type) { MOS6522State *ms =3D MOS6522(obj); MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(ms); =20 if (mdc->parent_phases.hold) { - mdc->parent_phases.hold(obj); + mdc->parent_phases.hold(obj, type); } =20 ms->timers[0].frequency =3D VIA_TIMER_FREQ; diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 41934e2cf8e..beab0ffb13f 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -586,13 +586,13 @@ static void mos6522_cuda_portB_write(MOS6522State *s) cuda_update(cs); } =20 -static void mos6522_cuda_reset_hold(Object *obj) +static void mos6522_cuda_reset_hold(Object *obj, ResetType type) { MOS6522State *ms =3D MOS6522(obj); MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(ms); =20 if (mdc->parent_phases.hold) { - mdc->parent_phases.hold(obj); + mdc->parent_phases.hold(obj, type); } =20 ms->timers[0].frequency =3D CUDA_TIMER_FREQ; diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index e40c51bf529..238da58eade 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -792,7 +792,7 @@ static void mos6522_pmu_portB_write(MOS6522State *s) pmu_update(ps); } =20 -static void mos6522_pmu_reset_hold(Object *obj) +static void mos6522_pmu_reset_hold(Object *obj, ResetType type) { MOS6522State *ms =3D MOS6522(obj); MOS6522PMUState *mps =3D container_of(ms, MOS6522PMUState, parent_obj); @@ -800,7 +800,7 @@ static void mos6522_pmu_reset_hold(Object *obj) MOS6522DeviceClass *mdc =3D MOS6522_GET_CLASS(ms); =20 if (mdc->parent_phases.hold) { - mdc->parent_phases.hold(obj); + mdc->parent_phases.hold(obj, type); } =20 ms->timers[0].frequency =3D VIA_TIMER_FREQ; diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index e3fe87c20ca..515f62e687d 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -642,7 +642,7 @@ const VMStateDescription vmstate_mos6522 =3D { } }; =20 -static void mos6522_reset_hold(Object *obj) +static void mos6522_reset_hold(Object *obj, ResetType type) { MOS6522State *s =3D MOS6522(obj); =20 diff --git a/hw/misc/npcm7xx_mft.c b/hw/misc/npcm7xx_mft.c index 9a848584e18..9fcc69fe5c5 100644 --- a/hw/misc/npcm7xx_mft.c +++ b/hw/misc/npcm7xx_mft.c @@ -467,7 +467,7 @@ static void npcm7xx_mft_enter_reset(Object *obj, ResetT= ype type) npcm7xx_mft_reset(s); } =20 -static void npcm7xx_mft_hold_reset(Object *obj) +static void npcm7xx_mft_hold_reset(Object *obj, ResetType type) { NPCM7xxMFTState *s =3D NPCM7XX_MFT(obj); =20 diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c index fca2dd2e5af..f7f77e30a22 100644 --- a/hw/misc/npcm7xx_pwm.c +++ b/hw/misc/npcm7xx_pwm.c @@ -468,7 +468,7 @@ static void npcm7xx_pwm_enter_reset(Object *obj, ResetT= ype type) s->piir =3D 0x00000000; } =20 -static void npcm7xx_pwm_hold_reset(Object *obj) +static void npcm7xx_pwm_hold_reset(Object *obj, ResetType type) { NPCM7xxPWMState *s =3D NPCM7XX_PWM(obj); int i; diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c index 9fd859160d4..a090dbd366f 100644 --- a/hw/misc/stm32l4x5_exti.c +++ b/hw/misc/stm32l4x5_exti.c @@ -77,7 +77,7 @@ static unsigned configurable_mask(unsigned bank) return valid_mask(bank) & ~exti_romask[bank]; } =20 -static void stm32l4x5_exti_reset_hold(Object *obj) +static void stm32l4x5_exti_reset_hold(Object *obj, ResetType type) { Stm32l4x5ExtiState *s =3D STM32L4X5_EXTI(obj); =20 diff --git a/hw/misc/stm32l4x5_rcc.c b/hw/misc/stm32l4x5_rcc.c index ed2dbd9dc3f..417bd5e85f6 100644 --- a/hw/misc/stm32l4x5_rcc.c +++ b/hw/misc/stm32l4x5_rcc.c @@ -113,13 +113,13 @@ static void clock_mux_reset_enter(Object *obj, ResetT= ype type) set_clock_mux_init_info(s, s->id); } =20 -static void clock_mux_reset_hold(Object *obj) +static void clock_mux_reset_hold(Object *obj, ResetType type) { RccClockMuxState *s =3D RCC_CLOCK_MUX(obj); clock_mux_update(s, true); } =20 -static void clock_mux_reset_exit(Object *obj) +static void clock_mux_reset_exit(Object *obj, ResetType type) { RccClockMuxState *s =3D RCC_CLOCK_MUX(obj); clock_mux_update(s, false); @@ -263,13 +263,13 @@ static void pll_reset_enter(Object *obj, ResetType ty= pe) set_pll_init_info(s, s->id); } =20 -static void pll_reset_hold(Object *obj) +static void pll_reset_hold(Object *obj, ResetType type) { RccPllState *s =3D RCC_PLL(obj); pll_update(s, true); } =20 -static void pll_reset_exit(Object *obj) +static void pll_reset_exit(Object *obj, ResetType type) { RccPllState *s =3D RCC_PLL(obj); pll_update(s, false); @@ -907,7 +907,7 @@ static void rcc_update_csr(Stm32l4x5RccState *s) rcc_update_irq(s); } =20 -static void stm32l4x5_rcc_reset_hold(Object *obj) +static void stm32l4x5_rcc_reset_hold(Object *obj, ResetType type) { Stm32l4x5RccState *s =3D STM32L4X5_RCC(obj); s->cr =3D 0x00000063; diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c index 3dafc00b49d..a5a1ce26804 100644 --- a/hw/misc/stm32l4x5_syscfg.c +++ b/hw/misc/stm32l4x5_syscfg.c @@ -65,7 +65,7 @@ =20 #define NUM_LINES_PER_EXTICR_REG 4 =20 -static void stm32l4x5_syscfg_hold_reset(Object *obj) +static void stm32l4x5_syscfg_hold_reset(Object *obj, ResetType type) { Stm32l4x5SyscfgState *s =3D STM32L4X5_SYSCFG(obj); =20 diff --git a/hw/misc/xlnx-versal-cframe-reg.c b/hw/misc/xlnx-versal-cframe-= reg.c index a6ab287b019..3fc838bd54b 100644 --- a/hw/misc/xlnx-versal-cframe-reg.c +++ b/hw/misc/xlnx-versal-cframe-reg.c @@ -542,7 +542,7 @@ static void cframe_reg_reset_enter(Object *obj, ResetTy= pe type) } } =20 -static void cframe_reg_reset_hold(Object *obj) +static void cframe_reg_reset_hold(Object *obj, ResetType type) { XlnxVersalCFrameReg *s =3D XLNX_VERSAL_CFRAME_REG(obj); =20 diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index 1f1762ef163..f143900d5b4 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -311,7 +311,7 @@ static void crl_reset_enter(Object *obj, ResetType type) } } =20 -static void crl_reset_hold(Object *obj) +static void crl_reset_hold(Object *obj, ResetType type) { XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); =20 diff --git a/hw/misc/xlnx-versal-pmc-iou-slcr.c b/hw/misc/xlnx-versal-pmc-i= ou-slcr.c index 60e13a78ab8..e469c04d763 100644 --- a/hw/misc/xlnx-versal-pmc-iou-slcr.c +++ b/hw/misc/xlnx-versal-pmc-iou-slcr.c @@ -1350,7 +1350,7 @@ static void xlnx_versal_pmc_iou_slcr_reset_init(Objec= t *obj, ResetType type) } } =20 -static void xlnx_versal_pmc_iou_slcr_reset_hold(Object *obj) +static void xlnx_versal_pmc_iou_slcr_reset_hold(Object *obj, ResetType typ= e) { XlnxVersalPmcIouSlcr *s =3D XILINX_VERSAL_PMC_IOU_SLCR(obj); =20 diff --git a/hw/misc/xlnx-versal-trng.c b/hw/misc/xlnx-versal-trng.c index 6495188dc74..51eb7600414 100644 --- a/hw/misc/xlnx-versal-trng.c +++ b/hw/misc/xlnx-versal-trng.c @@ -632,7 +632,7 @@ static void trng_unrealize(DeviceState *dev) s->prng =3D NULL; } =20 -static void trng_reset_hold(Object *obj) +static void trng_reset_hold(Object *obj, ResetType type) { trng_reset(XLNX_VERSAL_TRNG(obj)); } diff --git a/hw/misc/xlnx-versal-xramc.c b/hw/misc/xlnx-versal-xramc.c index a5f78c190eb..ad839ce7e9f 100644 --- a/hw/misc/xlnx-versal-xramc.c +++ b/hw/misc/xlnx-versal-xramc.c @@ -137,7 +137,7 @@ static void xram_ctrl_reset_enter(Object *obj, ResetTyp= e type) ARRAY_FIELD_DP32(s->regs, XRAM_IMP, SIZE, s->cfg.encoded_size); } =20 -static void xram_ctrl_reset_hold(Object *obj) +static void xram_ctrl_reset_hold(Object *obj, ResetType type) { XlnxXramCtrl *s =3D XLNX_XRAM_CTRL(obj); =20 diff --git a/hw/misc/xlnx-zynqmp-apu-ctrl.c b/hw/misc/xlnx-zynqmp-apu-ctrl.c index 1d441b41dfe..87e4a140679 100644 --- a/hw/misc/xlnx-zynqmp-apu-ctrl.c +++ b/hw/misc/xlnx-zynqmp-apu-ctrl.c @@ -150,7 +150,7 @@ static void zynqmp_apu_reset_enter(Object *obj, ResetTy= pe type) s->cpu_in_wfi =3D 0; } =20 -static void zynqmp_apu_reset_hold(Object *obj) +static void zynqmp_apu_reset_hold(Object *obj, ResetType type) { XlnxZynqMPAPUCtrl *s =3D XLNX_ZYNQMP_APU_CTRL(obj); =20 diff --git a/hw/misc/xlnx-zynqmp-crf.c b/hw/misc/xlnx-zynqmp-crf.c index a83efb44e31..e5aba56f691 100644 --- a/hw/misc/xlnx-zynqmp-crf.c +++ b/hw/misc/xlnx-zynqmp-crf.c @@ -191,7 +191,7 @@ static void crf_reset_enter(Object *obj, ResetType type) } } =20 -static void crf_reset_hold(Object *obj) +static void crf_reset_hold(Object *obj, ResetType type) { XlnxZynqMPCRF *s =3D XLNX_ZYNQMP_CRF(obj); ir_update_irq(s); diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index d2ac2e77f26..3412ff099ea 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -416,7 +416,7 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) s->regs[R_DDRIOB + 12] =3D 0x00000021; } =20 -static void zynq_slcr_reset_hold(Object *obj) +static void zynq_slcr_reset_hold(Object *obj, ResetType type) { ZynqSLCRState *s =3D ZYNQ_SLCR(obj); =20 @@ -425,7 +425,7 @@ static void zynq_slcr_reset_hold(Object *obj) zynq_slcr_propagate_clocks(s); } =20 -static void zynq_slcr_reset_exit(Object *obj) +static void zynq_slcr_reset_exit(Object *obj, ResetType type) { ZynqSLCRState *s =3D ZYNQ_SLCR(obj); =20 diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c index ca0ce4e8bbf..58f1432bb35 100644 --- a/hw/net/can/xlnx-zynqmp-can.c +++ b/hw/net/can/xlnx-zynqmp-can.c @@ -1006,7 +1006,7 @@ static void xlnx_zynqmp_can_reset_init(Object *obj, R= esetType type) ptimer_transaction_commit(s->can_timer); } =20 -static void xlnx_zynqmp_can_reset_hold(Object *obj) +static void xlnx_zynqmp_can_reset_hold(Object *obj, ResetType type) { XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(obj); unsigned int i; diff --git a/hw/net/e1000.c b/hw/net/e1000.c index 43f3a4a7011..5012b964640 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -373,7 +373,7 @@ static bool e1000_vet_init_need(void *opaque) return chkflag(VET); } =20 -static void e1000_reset_hold(Object *obj) +static void e1000_reset_hold(Object *obj, ResetType type) { E1000State *d =3D E1000(obj); E1000BaseClass *edc =3D E1000_GET_CLASS(d); diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index 7c6f6029518..edc101eaf68 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -513,7 +513,7 @@ static void e1000e_pci_uninit(PCIDevice *pci_dev) msi_uninit(pci_dev); } =20 -static void e1000e_qdev_reset_hold(Object *obj) +static void e1000e_qdev_reset_hold(Object *obj, ResetType type) { E1000EState *s =3D E1000E(obj); =20 diff --git a/hw/net/igb.c b/hw/net/igb.c index 9b37523d6df..1ef6170465f 100644 --- a/hw/net/igb.c +++ b/hw/net/igb.c @@ -486,7 +486,7 @@ static void igb_pci_uninit(PCIDevice *pci_dev) msi_uninit(pci_dev); } =20 -static void igb_qdev_reset_hold(Object *obj) +static void igb_qdev_reset_hold(Object *obj, ResetType type) { IGBState *s =3D IGB(obj); =20 diff --git a/hw/net/igbvf.c b/hw/net/igbvf.c index 94a4e885f20..21a97d4d61d 100644 --- a/hw/net/igbvf.c +++ b/hw/net/igbvf.c @@ -282,7 +282,7 @@ static void igbvf_pci_realize(PCIDevice *dev, Error **e= rrp) pcie_ari_init(dev, 0x150); } =20 -static void igbvf_qdev_reset_hold(Object *obj) +static void igbvf_qdev_reset_hold(Object *obj, ResetType type) { PCIDevice *vf =3D PCI_DEVICE(obj); =20 diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c index 0a71a005c69..09575a77d77 100644 --- a/hw/nvram/xlnx-bbram.c +++ b/hw/nvram/xlnx-bbram.c @@ -417,7 +417,7 @@ static RegisterAccessInfo bbram_ctrl_regs_info[] =3D { } }; =20 -static void bbram_ctrl_reset_hold(Object *obj) +static void bbram_ctrl_reset_hold(Object *obj, ResetType type) { XlnxBBRam *s =3D XLNX_BBRAM(obj); unsigned int i; diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse= -ctrl.c index e4b9e11a3dd..def6fe3302b 100644 --- a/hw/nvram/xlnx-versal-efuse-ctrl.c +++ b/hw/nvram/xlnx-versal-efuse-ctrl.c @@ -658,7 +658,7 @@ static void efuse_ctrl_register_reset(RegisterInfo *reg) register_reset(reg); } =20 -static void efuse_ctrl_reset_hold(Object *obj) +static void efuse_ctrl_reset_hold(Object *obj, ResetType type) { XlnxVersalEFuseCtrl *s =3D XLNX_VERSAL_EFUSE_CTRL(obj); unsigned int i; diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c index ec98456e5d1..2d465f0fc6a 100644 --- a/hw/nvram/xlnx-zynqmp-efuse.c +++ b/hw/nvram/xlnx-zynqmp-efuse.c @@ -770,7 +770,7 @@ static void zynqmp_efuse_register_reset(RegisterInfo *r= eg) register_reset(reg); } =20 -static void zynqmp_efuse_reset_hold(Object *obj) +static void zynqmp_efuse_reset_hold(Object *obj, ResetType type) { XlnxZynqMPEFuse *s =3D XLNX_ZYNQMP_EFUSE(obj); unsigned int i; diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 8a30da602cc..2dd10239bd2 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -186,13 +186,13 @@ static void cxl_rp_realize(DeviceState *dev, Error **= errp) component_bar); } =20 -static void cxl_rp_reset_hold(Object *obj) +static void cxl_rp_reset_hold(Object *obj, ResetType type) { PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(obj); CXLRootPort *crp =3D CXL_ROOT_PORT(obj); =20 if (rpc->parent_phases.hold) { - rpc->parent_phases.hold(obj); + rpc->parent_phases.hold(obj, type); } =20 latch_registers(crp); diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index efd96bf1741..09a34786bc6 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -43,7 +43,7 @@ static void rp_write_config(PCIDevice *d, uint32_t addres= s, pcie_aer_root_write_config(d, address, val, len, root_cmd); } =20 -static void rp_reset_hold(Object *obj) +static void rp_reset_hold(Object *obj, ResetType type) { PCIDevice *d =3D PCI_DEVICE(obj); DeviceState *qdev =3D DEVICE(obj); diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index 1f0c4353484..1516d0074dd 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -590,7 +590,7 @@ static int pci_bonito_map_irq(PCIDevice *pci_dev, int i= rq_num) } } =20 -static void bonito_reset_hold(Object *obj) +static void bonito_reset_hold(Object *obj, ResetType type) { PCIBonitoState *s =3D PCI_BONITO(obj); uint32_t val =3D 0; diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index 157c00782ce..d4c118d4436 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -208,7 +208,7 @@ static void pnv_phb_class_init(ObjectClass *klass, void= *data) dc->user_creatable =3D true; } =20 -static void pnv_phb_root_port_reset_hold(Object *obj) +static void pnv_phb_root_port_reset_hold(Object *obj, ResetType type) { PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(obj); PnvPHBRootPort *phb_rp =3D PNV_PHB_ROOT_PORT(obj); @@ -216,7 +216,7 @@ static void pnv_phb_root_port_reset_hold(Object *obj) uint8_t *conf =3D d->config; =20 if (rpc->parent_phases.hold) { - rpc->parent_phases.hold(obj); + rpc->parent_phases.hold(obj, type); } =20 if (phb_rp->version =3D=3D 3) { diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c index dc8d8637f26..a6d827f903f 100644 --- a/hw/pci-host/pnv_phb3_msi.c +++ b/hw/pci-host/pnv_phb3_msi.c @@ -228,13 +228,13 @@ static void phb3_msi_resend(ICSState *ics) } } =20 -static void phb3_msi_reset_hold(Object *obj) +static void phb3_msi_reset_hold(Object *obj, ResetType type) { Phb3MsiState *msi =3D PHB3_MSI(obj); ICSStateClass *icsc =3D ICS_GET_CLASS(obj); =20 if (icsc->parent_phases.hold) { - icsc->parent_phases.hold(obj); + icsc->parent_phases.hold(obj, type); } =20 memset(msi->rba, 0, sizeof(msi->rba)); diff --git a/hw/pci/pci.c b/hw/pci/pci.c index e7a39cb203a..324c1302d25 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -64,7 +64,7 @@ bool pci_available =3D true; =20 static char *pcibus_get_dev_path(DeviceState *dev); static char *pcibus_get_fw_dev_path(DeviceState *dev); -static void pcibus_reset_hold(Object *obj); +static void pcibus_reset_hold(Object *obj, ResetType type); static bool pcie_has_upstream_port(PCIDevice *dev); =20 static Property pci_props[] =3D { @@ -427,7 +427,7 @@ void pci_device_reset(PCIDevice *dev) * Called via bus_cold_reset on RST# assert, after the devices * have been reset device_cold_reset-ed already. */ -static void pcibus_reset_hold(Object *obj) +static void pcibus_reset_hold(Object *obj, ResetType type) { PCIBus *bus =3D PCI_BUS(obj); int i; diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index f4c18692325..3379f92748b 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -998,7 +998,7 @@ static void rtc_reset_enter(Object *obj, ResetType type) } } =20 -static void rtc_reset_hold(Object *obj) +static void rtc_reset_hold(Object *obj, ResetType type) { MC146818RtcState *s =3D MC146818_RTC(obj); =20 diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c index 34639f21435..8657ff7bf48 100644 --- a/hw/s390x/css-bridge.c +++ b/hw/s390x/css-bridge.c @@ -56,7 +56,7 @@ static void ccw_device_unplug(HotplugHandler *hotplug_dev, qdev_unrealize(dev); } =20 -static void virtual_css_bus_reset_hold(Object *obj) +static void virtual_css_bus_reset_hold(Object *obj, ResetType type) { /* This should actually be modelled via the generic css */ css_reset(); diff --git a/hw/sensor/adm1266.c b/hw/sensor/adm1266.c index 5454b73a639..25b87a72961 100644 --- a/hw/sensor/adm1266.c +++ b/hw/sensor/adm1266.c @@ -76,7 +76,7 @@ static const uint8_t adm1266_ic_device_id[] =3D {0x03, 0x= 41, 0x12, 0x66}; static const uint8_t adm1266_ic_device_rev[] =3D {0x08, 0x01, 0x08, 0x07, = 0x0, 0x0, 0x07, 0x41, 0x30}; =20 -static void adm1266_exit_reset(Object *obj) +static void adm1266_exit_reset(Object *obj, ResetType type) { ADM1266State *s =3D ADM1266(obj); PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); diff --git a/hw/sensor/adm1272.c b/hw/sensor/adm1272.c index a19557ec9ea..3fc1e5d0ad9 100644 --- a/hw/sensor/adm1272.c +++ b/hw/sensor/adm1272.c @@ -185,7 +185,7 @@ static uint32_t adm1272_direct_to_watts(uint16_t value) return pmbus_direct_mode2data(c, value); } =20 -static void adm1272_exit_reset(Object *obj) +static void adm1272_exit_reset(Object *obj, ResetType type) { ADM1272State *s =3D ADM1272(obj); PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); diff --git a/hw/sensor/isl_pmbus_vr.c b/hw/sensor/isl_pmbus_vr.c index e51269f6b83..304a66ea8b0 100644 --- a/hw/sensor/isl_pmbus_vr.c +++ b/hw/sensor/isl_pmbus_vr.c @@ -63,7 +63,7 @@ static void isl_pmbus_vr_set(Object *obj, Visitor *v, con= st char *name, pmbus_check_limits(pmdev); } =20 -static void isl_pmbus_vr_exit_reset(Object *obj) +static void isl_pmbus_vr_exit_reset(Object *obj, ResetType type) { PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); =20 @@ -102,11 +102,11 @@ static void isl_pmbus_vr_exit_reset(Object *obj) } =20 /* The raa228000 uses different direct mode coefficients from most isl dev= ices */ -static void raa228000_exit_reset(Object *obj) +static void raa228000_exit_reset(Object *obj, ResetType type) { PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); =20 - isl_pmbus_vr_exit_reset(obj); + isl_pmbus_vr_exit_reset(obj, type); =20 pmdev->pages[0].read_iout =3D 0; pmdev->pages[0].read_pout =3D 0; @@ -119,13 +119,13 @@ static void raa228000_exit_reset(Object *obj) pmdev->pages[0].read_temperature_3 =3D 0; } =20 -static void isl69259_exit_reset(Object *obj) +static void isl69259_exit_reset(Object *obj, ResetType type) { ISLState *s =3D ISL69260(obj); static const uint8_t ic_device_id[] =3D {0x04, 0x00, 0x81, 0xD2, 0x49,= 0x3c}; g_assert(sizeof(ic_device_id) <=3D sizeof(s->ic_device_id)); =20 - isl_pmbus_vr_exit_reset(obj); + isl_pmbus_vr_exit_reset(obj, type); =20 s->ic_device_id_len =3D sizeof(ic_device_id); memcpy(s->ic_device_id, ic_device_id, sizeof(ic_device_id)); diff --git a/hw/sensor/max31785.c b/hw/sensor/max31785.c index 916ed4d457b..3577a7c2180 100644 --- a/hw/sensor/max31785.c +++ b/hw/sensor/max31785.c @@ -444,7 +444,7 @@ static int max31785_write_data(PMBusDevice *pmdev, cons= t uint8_t *buf, return 0; } =20 -static void max31785_exit_reset(Object *obj) +static void max31785_exit_reset(Object *obj, ResetType type) { PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); MAX31785State *s =3D MAX31785(obj); diff --git a/hw/sensor/max34451.c b/hw/sensor/max34451.c index 031ae53f594..93b53f3db2f 100644 --- a/hw/sensor/max34451.c +++ b/hw/sensor/max34451.c @@ -608,7 +608,7 @@ static inline void *memset_word(void *s, uint16_t c, si= ze_t n) return s; } =20 -static void max34451_exit_reset(Object *obj) +static void max34451_exit_reset(Object *obj, ResetType type) { PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); MAX34451State *s =3D MAX34451(obj); diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c index 81dd972ee8c..119c38c4156 100644 --- a/hw/ssi/npcm7xx_fiu.c +++ b/hw/ssi/npcm7xx_fiu.c @@ -483,7 +483,7 @@ static void npcm7xx_fiu_enter_reset(Object *obj, ResetT= ype type) s->regs[NPCM7XX_FIU_CFG] =3D 0x0000000b; } =20 -static void npcm7xx_fiu_hold_reset(Object *obj) +static void npcm7xx_fiu_hold_reset(Object *obj, ResetType type) { NPCM7xxFIUState *s =3D NPCM7XX_FIU(obj); int i; diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index da7c946af52..dd6d96b0a10 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -357,7 +357,7 @@ static void etraxfs_timer_reset_enter(Object *obj, Rese= tType type) t->rw_intr_mask =3D 0; } =20 -static void etraxfs_timer_reset_hold(Object *obj) +static void etraxfs_timer_reset_hold(Object *obj, ResetType type) { ETRAXTimerState *t =3D ETRAX_TIMER(obj); =20 diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c index 779c6049fab..c55ba022353 100644 --- a/hw/timer/npcm7xx_timer.c +++ b/hw/timer/npcm7xx_timer.c @@ -592,7 +592,7 @@ static void npcm7xx_watchdog_timer_expired(void *opaque) } } =20 -static void npcm7xx_timer_hold_reset(Object *obj) +static void npcm7xx_timer_hold_reset(Object *obj, ResetType type) { NPCM7xxTimerCtrlState *s =3D NPCM7XX_TIMER(obj); int i; diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c index 222eef82a55..8cac9c0a062 100644 --- a/hw/usb/hcd-dwc2.c +++ b/hw/usb/hcd-dwc2.c @@ -1305,7 +1305,7 @@ static void dwc2_reset_enter(Object *obj, ResetType t= ype) } } =20 -static void dwc2_reset_hold(Object *obj) +static void dwc2_reset_hold(Object *obj, ResetType type) { DWC2Class *c =3D DWC2_USB_GET_CLASS(obj); DWC2State *s =3D DWC2_USB(obj); @@ -1313,13 +1313,13 @@ static void dwc2_reset_hold(Object *obj) trace_usb_dwc2_reset_hold(); =20 if (c->parent_phases.hold) { - c->parent_phases.hold(obj); + c->parent_phases.hold(obj, type); } =20 dwc2_update_irq(s); } =20 -static void dwc2_reset_exit(Object *obj) +static void dwc2_reset_exit(Object *obj, ResetType type) { DWC2Class *c =3D DWC2_USB_GET_CLASS(obj); DWC2State *s =3D DWC2_USB(obj); @@ -1327,7 +1327,7 @@ static void dwc2_reset_exit(Object *obj) trace_usb_dwc2_reset_exit(); =20 if (c->parent_phases.exit) { - c->parent_phases.exit(obj); + c->parent_phases.exit(obj, type); } =20 s->hprt0 =3D HPRT0_PWR; diff --git a/hw/usb/xlnx-versal-usb2-ctrl-regs.c b/hw/usb/xlnx-versal-usb2-= ctrl-regs.c index 6fc453817ea..66c793a6021 100644 --- a/hw/usb/xlnx-versal-usb2-ctrl-regs.c +++ b/hw/usb/xlnx-versal-usb2-ctrl-regs.c @@ -153,7 +153,7 @@ static void usb2_ctrl_regs_reset_init(Object *obj, Rese= tType type) } } =20 -static void usb2_ctrl_regs_reset_hold(Object *obj) +static void usb2_ctrl_regs_reset_hold(Object *obj, ResetType type) { VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(obj); =20 diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index cb159fd0785..b1d02f4b3de 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2292,7 +2292,7 @@ static void virtio_pci_reset(DeviceState *qdev) } } =20 -static void virtio_pci_bus_reset_hold(Object *obj) +static void virtio_pci_bus_reset_hold(Object *obj, ResetType type) { PCIDevice *dev =3D PCI_DEVICE(obj); DeviceState *qdev =3D DEVICE(obj); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d2dfd36fd45..a152def2413 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -220,7 +220,7 @@ static void cp_reg_check_reset(gpointer key, gpointer v= alue, gpointer opaque) assert(oldvalue =3D=3D newvalue); } =20 -static void arm_cpu_reset_hold(Object *obj) +static void arm_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); ARMCPU *cpu =3D ARM_CPU(cs); @@ -228,7 +228,7 @@ static void arm_cpu_reset_hold(Object *obj) CPUARMState *env =3D &cpu->env; =20 if (acc->parent_phases.hold) { - acc->parent_phases.hold(obj); + acc->parent_phases.hold(obj, type); } =20 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 45ee1b5f89e..71ce62a4c25 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -66,7 +66,7 @@ static void avr_restore_state_to_opc(CPUState *cs, cpu_env(cs)->pc_w =3D data[0]; } =20 -static void avr_cpu_reset_hold(Object *obj) +static void avr_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); AVRCPU *cpu =3D AVR_CPU(cs); @@ -74,7 +74,7 @@ static void avr_cpu_reset_hold(Object *obj) CPUAVRState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { - mcc->parent_phases.hold(obj); + mcc->parent_phases.hold(obj, type); } =20 env->pc_w =3D 0; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index eb4bddcb7e7..535ec39c730 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -61,7 +61,7 @@ static int cris_cpu_mmu_index(CPUState *cs, bool ifetch) return !!(cpu_env(cs)->pregs[PR_CCS] & U_FLAG); } =20 -static void cris_cpu_reset_hold(Object *obj) +static void cris_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); CRISCPUClass *ccc =3D CRIS_CPU_GET_CLASS(obj); @@ -69,7 +69,7 @@ static void cris_cpu_reset_hold(Object *obj) uint32_t vr; =20 if (ccc->parent_phases.hold) { - ccc->parent_phases.hold(obj); + ccc->parent_phases.hold(obj, type); } =20 vr =3D env->pregs[PR_VR]; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 3a716b9be3c..a56bb4b075c 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -273,14 +273,14 @@ static void hexagon_restore_state_to_opc(CPUState *cs, cpu_env(cs)->gpr[HEX_REG_PC] =3D data[0]; } =20 -static void hexagon_cpu_reset_hold(Object *obj) +static void hexagon_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); HexagonCPUClass *mcc =3D HEXAGON_CPU_GET_CLASS(obj); CPUHexagonState *env =3D cpu_env(cs); =20 if (mcc->parent_phases.hold) { - mcc->parent_phases.hold(obj); + mcc->parent_phases.hold(obj, type); } =20 set_default_nan_mode(1, &env->fp_status); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fd6af0d7632..fa1ea3735d2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6830,7 +6830,7 @@ static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *= env) #endif } =20 -static void x86_cpu_reset_hold(Object *obj) +static void x86_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); X86CPU *cpu =3D X86_CPU(cs); @@ -6841,7 +6841,7 @@ static void x86_cpu_reset_hold(Object *obj) int i; =20 if (xcc->parent_phases.hold) { - xcc->parent_phases.hold(obj); + xcc->parent_phases.hold(obj, type); } =20 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 203a349055c..bac84dca7af 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -495,14 +495,14 @@ static void loongarch_max_initfn(Object *obj) loongarch_la464_initfn(obj); } =20 -static void loongarch_cpu_reset_hold(Object *obj) +static void loongarch_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); LoongArchCPUClass *lacc =3D LOONGARCH_CPU_GET_CLASS(obj); CPULoongArchState *env =3D cpu_env(cs); =20 if (lacc->parent_phases.hold) { - lacc->parent_phases.hold(obj); + lacc->parent_phases.hold(obj, type); } =20 env->fcsr0_mask =3D FCSR0_M1 | FCSR0_M2 | FCSR0_M3; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index df49ff1880c..efd6bbded86 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -71,7 +71,7 @@ static void m68k_unset_feature(CPUM68KState *env, int fea= ture) env->features &=3D ~BIT_ULL(feature); } =20 -static void m68k_cpu_reset_hold(Object *obj) +static void m68k_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); M68kCPUClass *mcc =3D M68K_CPU_GET_CLASS(obj); @@ -80,7 +80,7 @@ static void m68k_cpu_reset_hold(Object *obj) int i; =20 if (mcc->parent_phases.hold) { - mcc->parent_phases.hold(obj); + mcc->parent_phases.hold(obj, type); } =20 memset(env, 0, offsetof(CPUM68KState, end_reset_fields)); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 96c2b71f7f7..f8dc3173fc0 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -181,7 +181,7 @@ static void microblaze_cpu_set_irq(void *opaque, int ir= q, int level) } #endif =20 -static void mb_cpu_reset_hold(Object *obj) +static void mb_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); @@ -189,7 +189,7 @@ static void mb_cpu_reset_hold(Object *obj) CPUMBState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { - mcc->parent_phases.hold(obj); + mcc->parent_phases.hold(obj, type); } =20 memset(env, 0, offsetof(CPUMBState, end_reset_fields)); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 8d8f690a535..bbe01d07dd8 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -185,7 +185,7 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) =20 #include "cpu-defs.c.inc" =20 -static void mips_cpu_reset_hold(Object *obj) +static void mips_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -193,7 +193,7 @@ static void mips_cpu_reset_hold(Object *obj) CPUMIPSState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { - mcc->parent_phases.hold(obj); + mcc->parent_phases.hold(obj, type); } =20 memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 33c45dbf04e..d711035cf59 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -85,14 +85,14 @@ static void openrisc_disas_set_info(CPUState *cpu, disa= ssemble_info *info) info->print_insn =3D print_insn_or1k; } =20 -static void openrisc_cpu_reset_hold(Object *obj) +static void openrisc_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); OpenRISCCPUClass *occ =3D OPENRISC_CPU_GET_CLASS(obj); =20 if (occ->parent_phases.hold) { - occ->parent_phases.hold(obj); + occ->parent_phases.hold(obj, type); } =20 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6241de62ce8..6d82f24c875 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7136,7 +7136,7 @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetc= h) return ppc_env_mmu_index(cpu_env(cs), ifetch); } =20 -static void ppc_cpu_reset_hold(Object *obj) +static void ppc_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -7146,7 +7146,7 @@ static void ppc_cpu_reset_hold(Object *obj) int i; =20 if (pcc->parent_phases.hold) { - pcc->parent_phases.hold(obj); + pcc->parent_phases.hold(obj, type); } =20 msr =3D (target_ulong)0; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 36e3e5fdaf5..eb1a2e7d6d9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -918,7 +918,7 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetc= h) return riscv_env_mmu_index(cpu_env(cs), ifetch); } =20 -static void riscv_cpu_reset_hold(Object *obj) +static void riscv_cpu_reset_hold(Object *obj, ResetType type) { #ifndef CONFIG_USER_ONLY uint8_t iprio; @@ -930,7 +930,7 @@ static void riscv_cpu_reset_hold(Object *obj) CPURISCVState *env =3D &cpu->env; =20 if (mcc->parent_phases.hold) { - mcc->parent_phases.hold(obj); + mcc->parent_phases.hold(obj, type); } #ifndef CONFIG_USER_ONLY env->misa_mxl =3D mcc->misa_mxl_max; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index da673a595d4..e3dfb097225 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -69,7 +69,7 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifunc) return 0; } =20 -static void rx_cpu_reset_hold(Object *obj) +static void rx_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); RXCPUClass *rcc =3D RX_CPU_GET_CLASS(obj); @@ -77,7 +77,7 @@ static void rx_cpu_reset_hold(Object *obj) uint32_t *resetvec; =20 if (rcc->parent_phases.hold) { - rcc->parent_phases.hold(obj); + rcc->parent_phases.hold(obj, type); } =20 memset(env, 0, offsetof(CPURXState, end_reset_fields)); diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 4f5a4a3d985..43e35ec2ca7 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -103,14 +103,14 @@ static int sh4_cpu_mmu_index(CPUState *cs, bool ifetc= h) } } =20 -static void superh_cpu_reset_hold(Object *obj) +static void superh_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); SuperHCPUClass *scc =3D SUPERH_CPU_GET_CLASS(obj); CPUSH4State *env =3D cpu_env(cs); =20 if (scc->parent_phases.hold) { - scc->parent_phases.hold(obj); + scc->parent_phases.hold(obj, type); } =20 memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index e820f50acf6..485d416925b 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -29,14 +29,14 @@ =20 //#define DEBUG_FEATURES =20 -static void sparc_cpu_reset_hold(Object *obj) +static void sparc_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(obj); CPUSPARCState *env =3D cpu_env(cs); =20 if (scc->parent_phases.hold) { - scc->parent_phases.hold(obj); + scc->parent_phases.hold(obj, type); } =20 memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index a9af73aeb58..8f9b72c3a04 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -58,13 +58,13 @@ static void tricore_restore_state_to_opc(CPUState *cs, cpu_env(cs)->PC =3D data[0]; } =20 -static void tricore_cpu_reset_hold(Object *obj) +static void tricore_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); TriCoreCPUClass *tcc =3D TRICORE_CPU_GET_CLASS(obj); =20 if (tcc->parent_phases.hold) { - tcc->parent_phases.hold(obj); + tcc->parent_phases.hold(obj, type); } =20 cpu_state_reset(cpu_env(cs)); diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 875cf843c93..de907cfeb1b 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -93,7 +93,7 @@ bool xtensa_abi_call0(void) } #endif =20 -static void xtensa_cpu_reset_hold(Object *obj) +static void xtensa_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); XtensaCPUClass *xcc =3D XTENSA_CPU_GET_CLASS(obj); @@ -102,7 +102,7 @@ static void xtensa_cpu_reset_hold(Object *obj) XTENSA_OPTION_DFP_COPROCESSOR); =20 if (xcc->parent_phases.hold) { - xcc->parent_phases.hold(obj); + xcc->parent_phases.hold(obj, type); } =20 env->pc =3D env->config->exception_vector[EXC_RESET0 + env->static_vec= tors]; --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041995; cv=none; d=zohomail.com; s=zohoarc; b=TLK6hHLNgHHFHPZ1+m/HyBZdiYdCOo0VcoMu3AdWyqR0dbFF1yhNK0vr+LjsnAxrB/s+ZO6yx/tiFK///PVbV96P3fxXLtlRz9J2jwOEnTi/ojVk+xfV0pJLmv20gdT6j5sD5HBPQ0CbT4DsQ5NXTjc3Dabd7xZeuDKr3TgGZ6k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041616; x=1714646416; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ujr72QtXXZPe8hmblwWvpr0weZcNa/JXY/niqd+OE9Q=; b=fbA/x4RI0/dBbTL2sBbMfybrwOiQUUEoZOSFe7yaqtap2Q75lktQN0bErkt6PFDjP7 aE2ymiJmciCGW9jDIWlR/VDkJSNBT0wcYSdCF9MjpIdVof0zEjSz7xuB0GhUEF8pmX3K V21Vrnll2SzzHJ6XNVZqeZ8OKIMg/4V+kLQEHtwrL4V2zQ5d6xTmVzjFnDfKXcKiW8q2 /KY3XEIU7UeT1CVqeAWaT/w3bbTVRqUNsCZTvqx9Z22X8ziHrG3w88SRKlyU9JjBAHr+ y/W++X0jxtnFgwC/5giBzeYeix+1YvOPvZBPg04prQWIvh566LjZTTZz3Dc2P1/nuJc9 Xr5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041616; x=1714646416; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ujr72QtXXZPe8hmblwWvpr0weZcNa/JXY/niqd+OE9Q=; b=c35FvpCPUf1shbX0SUt2HMGtgW2EeqMMGyq5pO8qr2NZ9O01ji5WaDMFDPxr2EPLlc OzqCILJdcdHG78xbkyDN6n9CRzLKn9eNW1Sjo1DCAnTJr5ZrPkvIsHMLDrjfdTQAHgjy ONphRQRF9oIAkaEGlT4lxex6z7FTJjh6iLFre47sfR+/taiv7kbOhFoSO819sEOkFdb2 qoYldVeg5FGc9ROjjb4HC/gD4ilHw1KywNCgkkUZ5oPURyAaCjX79d5OzqbtGAhlnrQn LIj/eugaPcA6WnP1S506NbZzlA5N2eaRwaYgtt32ynx+zZ2AP7GKagvL68yypDw2cH8N yfDg== X-Gm-Message-State: AOJu0Yyu5+c2vHk981X8SQYuPT9o5RAn6SRg1h2XEXPsAKMEeJ1HrJIB Y2vdRBRbOski8y7S678Lx/DxxFtV3gcDJjrA9cL0Nw7sxnY7MF/59VGM3RPrCcXbCPWUFZ1aXRJ 9 X-Google-Smtp-Source: AGHT+IFfmxajtciwOQoHhDbbckfH1YrlnaHmsj6OvnSk776hVbKEePDMQhqnqzUJkLSRO5dQwQ2s3A== X-Received: by 2002:adf:f508:0:b0:345:be70:191c with SMTP id q8-20020adff508000000b00345be70191cmr4582958wro.37.1714041616582; Thu, 25 Apr 2024 03:40:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/37] docs/devel/reset: Update to new API for hold and exit phase methods Date: Thu, 25 Apr 2024 11:39:52 +0100 Message-Id: <20240425103958.3237225-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041995980100005 Update the reset documentation's example code to match the new API for the hold and exit phase method APIs where they take a ResetType argument. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Luc Michel Message-id: 20240412160809.1260625-6-peter.maydell@linaro.org --- docs/devel/reset.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst index 2ea85e7779b..49baa1ea271 100644 --- a/docs/devel/reset.rst +++ b/docs/devel/reset.rst @@ -150,25 +150,25 @@ in reset. mydev->var =3D 0; } =20 - static void mydev_reset_hold(Object *obj) + static void mydev_reset_hold(Object *obj, ResetType type) { MyDevClass *myclass =3D MYDEV_GET_CLASS(obj); MyDevState *mydev =3D MYDEV(obj); /* call parent class hold phase */ if (myclass->parent_phases.hold) { - myclass->parent_phases.hold(obj); + myclass->parent_phases.hold(obj, type); } /* set an IO */ qemu_set_irq(mydev->irq, 1); } =20 - static void mydev_reset_exit(Object *obj) + static void mydev_reset_exit(Object *obj, ResetType type) { MyDevClass *myclass =3D MYDEV_GET_CLASS(obj); MyDevState *mydev =3D MYDEV(obj); /* call parent class exit phase */ if (myclass->parent_phases.exit) { - myclass->parent_phases.exit(obj); + myclass->parent_phases.exit(obj, type); } /* clear an IO */ qemu_set_irq(mydev->irq, 0); --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714042003; cv=none; d=zohomail.com; s=zohoarc; b=PGjODRhUDBkgnb79ytB7HB2mPns3wWZ9IK7+V60FecDuUWesfejk7XmR/IRXugpJOOuaXk2s7qGp0JF9RBirlUouKAhqIj2VdRwa3mSGMwZBr2JoFl6eX1Iyx2TflyTp7TRsQr3FwzbzeK233QiZaC7HIddLY+1wuui9eT9q9ZA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714042003; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ePrcln4bIoTeYHPaxB8JDKlC6bBG+7XjGQJPBdA/WHo=; b=fBG4i86HSECMjBWTY3865LGOHPTa8DoKRCF8fIFIqeKCnN0/Qw8cFKcqX31dcNxm/WRSTeJjV119fBchj/hUuxaJAFXxr/ANzAWO048x6MyR4+vQmB/Mc6cpqLUIwcuuLX/rf2miZcRMlwwx8F0U7LBfh5x+PdyY02DC4Qhdtdo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1714042003728205.25948866307203; Thu, 25 Apr 2024 03:46:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWe-0002Kw-79; Thu, 25 Apr 2024 06:40:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWb-00029V-1T for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:21 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWY-0007FG-R4 for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:20 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-34a32ba1962so661844f8f.2 for ; Thu, 25 Apr 2024 03:40:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041617; x=1714646417; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ePrcln4bIoTeYHPaxB8JDKlC6bBG+7XjGQJPBdA/WHo=; b=EeZIbk/fyR3NGPPA1oJ+fFFLs/JBSjQSXOB5bx5HhRS5VJw4I2AgwG7zfzFRAgtDGi BJO/UVz5uCV747Fdn/5Ybp9OiWCwZbZCa7EHUiSxQRNJ4JCmKV74/cWPpoJ5oy/GXn5d /jyW/8MB8uo1yD/SGAfKY1AR6EmZIrIaHH81qQN2kL8qLkCWUPLAsZUYy3tJAmprTMBt 3i2ets2X+abIsHcg87vm47wya91lsZjAtgyFt4HZ3W1h6fE0GVX2tyfqZpfeOq+oq3t7 /s/Ws+cAWSJnM6+DcW0q01z/3AfJwawjYbsZOj+rqHPMROeb0gLcQk0yF6TBVX0JasXJ VhOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041617; x=1714646417; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ePrcln4bIoTeYHPaxB8JDKlC6bBG+7XjGQJPBdA/WHo=; b=pQyzVy4QGhDjPFvw7iHixrTMWyiAywxsQAA+6WRFQdq7lEEgVyuTXmEh209TiVNrgD o5frNd6UE6TQbR0hGe9hbkXXu1bXs3lzpnF5R+52oqi3fyUQZSYjNidEPOj4D6tv6Ij7 +CvSOzaeOaEpoVUutSb2eXDZyC620bWi24dEEj4mcXQzpHejX0q+8iMwJfJYE9ojIe0x Zj19C5TyZm3wzKj9NIRxbMvKx58vf8/Ty3g6IZJXowsgZLnPYpGvD6Ff8Pi1s2grRr28 vU+YfxP7Kmw0FcemLoiYDoCIOy2tlYGkdjztm2HAXhd6oE/lwhVPEDPzakQaRgibiHnA 6aiw== X-Gm-Message-State: AOJu0YwsqMP9LcXSKGYVqfAmBVBNoQ9fv9oZkMc+ap0sDXfAxFIRgjeh Ad0xIeFCLg+S8FHQjKSbzNV5B+MP5tcl7w2C00XH61B9FurBUf13a257SmfpOu2gd5ng8cye8O3 5 X-Google-Smtp-Source: AGHT+IFHQY2YOY5WS7z0bCCar5gsEI/6InL3LQEuVf0JAKI3hJa2sPTo6iZwaiZkbGywGWljp/noeQ== X-Received: by 2002:a5d:56ce:0:b0:343:68d6:5636 with SMTP id m14-20020a5d56ce000000b0034368d65636mr3660613wrw.43.1714041617088; Thu, 25 Apr 2024 03:40:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/37] reset: Add RESET_TYPE_SNAPSHOT_LOAD Date: Thu, 25 Apr 2024 11:39:53 +0100 Message-Id: <20240425103958.3237225-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714042004117100001 Some devices and machines need to handle the reset before a vmsave snapshot is loaded differently -- the main user is the handling of RNG seed information, which does not want to put a new RNG seed into a ROM blob when we are doing a snapshot load. Currently this kind of reset handling is supported only for: * TYPE_MACHINE reset methods, which take a ShutdownCause argument * reset functions registered with qemu_register_reset_nosnapshotload To allow a three-phase-reset device to also distinguish "snapshot load" reset from the normal kind, add a new ResetType RESET_TYPE_SNAPSHOT_LOAD. All our existing reset methods ignore the reset type, so we don't need to update any device code. Add the enum type, and make qemu_devices_reset() use the right reset type for the ShutdownCause it is passed. This allows us to get rid of the device_reset_reason global we were using to implement qemu_register_reset_nosnapshotload(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Luc Michel Message-id: 20240412160809.1260625-7-peter.maydell@linaro.org --- docs/devel/reset.rst | 17 ++++++++++++++--- include/hw/resettable.h | 1 + hw/core/reset.c | 15 ++++----------- hw/core/resettable.c | 4 ---- 4 files changed, 19 insertions(+), 18 deletions(-) diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst index 49baa1ea271..9746a4e8a0b 100644 --- a/docs/devel/reset.rst +++ b/docs/devel/reset.rst @@ -27,9 +27,7 @@ instantly reset an object, without keeping it in reset st= ate, just call ``resettable_reset()``. These functions take two parameters: a pointer to = the object to reset and a reset type. =20 -Several types of reset will be supported. For now only cold reset is defin= ed; -others may be added later. The Resettable interface handles reset types wi= th an -enum: +The Resettable interface handles reset types with an enum ``ResetType``: =20 ``RESET_TYPE_COLD`` Cold reset is supported by every resettable object. In QEMU, it means we= reset @@ -37,6 +35,19 @@ enum: from what is a real hardware cold reset. It differs from other resets (l= ike warm or bus resets) which may keep certain parts untouched. =20 +``RESET_TYPE_SNAPSHOT_LOAD`` + This is called for a reset which is being done to put the system into a + clean state prior to loading a snapshot. (This corresponds to a reset + with ``SHUTDOWN_CAUSE_SNAPSHOT_LOAD``.) Almost all devices should treat + this the same as ``RESET_TYPE_COLD``. The main exception is devices which + have some non-deterministic state they want to reinitialize to a differe= nt + value on each cold reset, such as RNG seed information, and which they + must not reinitialize on a snapshot-load reset. + +Devices which implement reset methods must treat any unknown ``ResetType`` +as equivalent to ``RESET_TYPE_COLD``; this will reduce the amount of +existing code we need to change if we add more types in future. + Calling ``resettable_reset()`` is equivalent to calling ``resettable_assert_reset()`` then ``resettable_release_reset()``. It is possible to interleave multiple calls to these three functions. There may diff --git a/include/hw/resettable.h b/include/hw/resettable.h index 3161e471c9b..7e249deb8b5 100644 --- a/include/hw/resettable.h +++ b/include/hw/resettable.h @@ -35,6 +35,7 @@ typedef struct ResettableState ResettableState; */ typedef enum ResetType { RESET_TYPE_COLD, + RESET_TYPE_SNAPSHOT_LOAD, } ResetType; =20 /* diff --git a/hw/core/reset.c b/hw/core/reset.c index f9fef45e050..58dfc8db3dc 100644 --- a/hw/core/reset.c +++ b/hw/core/reset.c @@ -43,13 +43,6 @@ static ResettableContainer *get_root_reset_container(voi= d) return root_reset_container; } =20 -/* - * Reason why the currently in-progress qemu_devices_reset() was called. - * If we made at least SHUTDOWN_CAUSE_SNAPSHOT_LOAD have a corresponding - * ResetType we could perhaps avoid the need for this global. - */ -static ShutdownCause device_reset_reason; - /* * This is an Object which implements Resettable simply to call the * callback function in the hold phase. @@ -77,8 +70,7 @@ static void legacy_reset_hold(Object *obj, ResetType type) { LegacyReset *lr =3D LEGACY_RESET(obj); =20 - if (device_reset_reason =3D=3D SHUTDOWN_CAUSE_SNAPSHOT_LOAD && - lr->skip_on_snapshot_load) { + if (type =3D=3D RESET_TYPE_SNAPSHOT_LOAD && lr->skip_on_snapshot_load)= { return; } lr->func(lr->opaque); @@ -180,8 +172,9 @@ void qemu_unregister_resettable(Object *obj) =20 void qemu_devices_reset(ShutdownCause reason) { - device_reset_reason =3D reason; + ResetType type =3D (reason =3D=3D SHUTDOWN_CAUSE_SNAPSHOT_LOAD) ? + RESET_TYPE_SNAPSHOT_LOAD : RESET_TYPE_COLD; =20 /* Reset the simulation */ - resettable_reset(OBJECT(get_root_reset_container()), RESET_TYPE_COLD); + resettable_reset(OBJECT(get_root_reset_container()), type); } diff --git a/hw/core/resettable.c b/hw/core/resettable.c index bebf7f10b26..6dd3e3dc487 100644 --- a/hw/core/resettable.c +++ b/hw/core/resettable.c @@ -48,8 +48,6 @@ void resettable_reset(Object *obj, ResetType type) =20 void resettable_assert_reset(Object *obj, ResetType type) { - /* TODO: change this assert when adding support for other reset types = */ - assert(type =3D=3D RESET_TYPE_COLD); trace_resettable_reset_assert_begin(obj, type); assert(!enter_phase_in_progress); =20 @@ -64,8 +62,6 @@ void resettable_assert_reset(Object *obj, ResetType type) =20 void resettable_release_reset(Object *obj, ResetType type) { - /* TODO: change this assert when adding support for other reset types = */ - assert(type =3D=3D RESET_TYPE_COLD); trace_resettable_reset_release_begin(obj, type); assert(!enter_phase_in_progress); =20 --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1714041912; cv=none; d=zohomail.com; s=zohoarc; b=B3mXMCSQFL7nRHKxqvnhf/PKypDb35jZOcIJ/aaVzCy2MKNh+A/Zka4I7qPz9O2YgWT9eXuqOHmLWs+ZeczOXTDiB8/qwLQeAYyWRxEL3Uwfk8JHq8QIVEnGblrAxIzxkqPWONrkhsDEn8Jo1mfjIHmlTcC9z9jtOC86jd5XFIg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1714041912; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=NxAhZWpSZOMH6/H4AtnymDqmp17S07x0/1u6vIOiOjQ=; b=EzUqv4igmXKZ90NcYRXTz5XV61YcxZs93jCv+bqSTy50YHVQQfV1LZaf7PL3cbgBqeo5p2wxccV/TASiEf1SUnlNyFzekZkN1Ut36uSYfaP5RGWoW30BCShdZ0eK1L/w+UqlHHCRH8ygPpL6KbMDQXr3zIdJuShm3zW3/2rrIRM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 171404191279727.17609706811288; Thu, 25 Apr 2024 03:45:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rzwWh-0002SO-HI; Thu, 25 Apr 2024 06:40:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rzwWc-0002Fw-Bu for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:22 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rzwWY-0007Fd-V8 for qemu-devel@nongnu.org; Thu, 25 Apr 2024 06:40:22 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-34b1e35155aso940203f8f.3 for ; Thu, 25 Apr 2024 03:40:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041617; x=1714646417; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NxAhZWpSZOMH6/H4AtnymDqmp17S07x0/1u6vIOiOjQ=; b=BhnUhaXke+NZW158d3UdkNzwWNgxA8ydoakXGbz2tOGggZ7XGKfzB9+RGVvb4KsZHY 92RBN7W53B5zNCv+vgGKoXrGnDjDmoQVNhpEEzl87OT6T8zGBz5V2Dg2eD5cuUWtro8+ qwWrC5kfsSHIF6yjEIVqzugyJkRdU9E0M+qDV8EeCLSORtTqpvKGBKHdq4xe/uSFr2Ym Qo4Ii4M9bV0o/55NIPuL4FZIucWeQfaciRLN2GGD1ha0YkIKIomaa4NjulG8wuv4V4nE /X5dPIqXoTBTtMAM+j9+fSQwdR/79QvA4ttB0iDfjS1ifw7WVA+M9zRTDDy0bVzGkilz nM9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041617; x=1714646417; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NxAhZWpSZOMH6/H4AtnymDqmp17S07x0/1u6vIOiOjQ=; b=dU+ddCi9xjzBLb/ummSZ9yVsLHejJc89rDEA328VXeSNoYMUeKcJrh534TiCSk/9dE elPX5LVjwrJqpoBjh3XFtKxKAVHnYzlHZCfP8XvAXxbhLVigDHTp3wQn6gU+5wl2BXN1 /Qz8eB/7Th/Z+GTOfyzSzDZ1hjGviol2nAjqTcAqkgSHzdBMATLeq/8jONdXOYOEmR9V LsadThM3K5XQrP03/75beFsQXm1PJoCw7bRJdEIISlwa0RcHGWsK9Xc4vlx3izzMF72b CeILrA8hAIJuV1mua68nOMXXURCSBfpCuj0s7NORKqb3BWhhScQrxONHBb1axVWepx0h YFqg== X-Gm-Message-State: AOJu0YwZmL+kIF6cb43Y8xmHh+bdJTa31SDE83O0obfnZ+A3vsxHBNRt FJUy+wLSmG8GMFgJxkmBN5IF73v1F5SuDCjLtoGczSziFNTRY8gw2OPpbreS/0ksjfL2pesXZy8 T X-Google-Smtp-Source: AGHT+IFckzwTIjHzT2J/xQT1bBrSH95Yt1SDfWNfLc3Jj8n41xDhJDTEMcQfVtCvahUtx8r6V/OYvw== X-Received: by 2002:a05:6000:d87:b0:348:c2c7:9f13 with SMTP id dv7-20020a0560000d8700b00348c2c79f13mr4099887wrb.65.1714041617542; Thu, 25 Apr 2024 03:40:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/37] hw/char: Implement STM32L4x5 USART skeleton Date: Thu, 25 Apr 2024 11:39:54 +0100 Message-Id: <20240425103958.3237225-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041913807100007 From: Arnaud Minier Add the basic infrastructure (register read/write, type...) to implement the STM32L4x5 USART. Also create different types for the USART, UART and LPUART of the STM32L4x5 to deduplicate code and enable the implementation of different behaviors depending on the type. Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell Message-id: 20240329174402.60382-2-arnaud.minier@telecom-paris.fr [PMM: update to new reset hold method signature; fixed a few checkpatch nits] Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + include/hw/char/stm32l4x5_usart.h | 66 +++++ hw/char/stm32l4x5_usart.c | 396 ++++++++++++++++++++++++++++++ hw/char/Kconfig | 3 + hw/char/meson.build | 1 + hw/char/trace-events | 4 + 6 files changed, 471 insertions(+) create mode 100644 include/hw/char/stm32l4x5_usart.h create mode 100644 hw/char/stm32l4x5_usart.c diff --git a/MAINTAINERS b/MAINTAINERS index 8bb32f4a7e9..d5a51812422 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1115,6 +1115,7 @@ M: In=C3=A8s Varhol L: qemu-arm@nongnu.org S: Maintained F: hw/arm/stm32l4x5_soc.c +F: hw/char/stm32l4x5_usart.c F: hw/misc/stm32l4x5_exti.c F: hw/misc/stm32l4x5_syscfg.c F: hw/misc/stm32l4x5_rcc.c diff --git a/include/hw/char/stm32l4x5_usart.h b/include/hw/char/stm32l4x5_= usart.h new file mode 100644 index 00000000000..8d38a85a6e6 --- /dev/null +++ b/include/hw/char/stm32l4x5_usart.h @@ -0,0 +1,66 @@ +/* + * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitte= r) + * + * Copyright (c) 2023 Arnaud Minier + * Copyright (c) 2023 In=C3=A8s Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart + * by Alistair Francis. + * The reference used is the STMicroElectronics RM0351 Reference manual + * for STM32L4x5 and STM32L4x6 advanced Arm =C2=AE -based 32-bit MCUs. + */ + +#ifndef HW_STM32L4X5_USART_H +#define HW_STM32L4X5_USART_H + +#include "hw/sysbus.h" +#include "chardev/char-fe.h" +#include "qom/object.h" + +#define TYPE_STM32L4X5_USART_BASE "stm32l4x5-usart-base" +#define TYPE_STM32L4X5_USART "stm32l4x5-usart" +#define TYPE_STM32L4X5_UART "stm32l4x5-uart" +#define TYPE_STM32L4X5_LPUART "stm32l4x5-lpuart" +OBJECT_DECLARE_TYPE(Stm32l4x5UsartBaseState, Stm32l4x5UsartBaseClass, + STM32L4X5_USART_BASE) + +typedef enum { + STM32L4x5_USART, + STM32L4x5_UART, + STM32L4x5_LPUART, +} Stm32l4x5UsartType; + +struct Stm32l4x5UsartBaseState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t cr1; + uint32_t cr2; + uint32_t cr3; + uint32_t brr; + uint32_t gtpr; + uint32_t rtor; + /* rqr is write-only */ + uint32_t isr; + /* icr is a clear register */ + uint32_t rdr; + uint32_t tdr; + + Clock *clk; + CharBackend chr; + qemu_irq irq; +}; + +struct Stm32l4x5UsartBaseClass { + SysBusDeviceClass parent_class; + + Stm32l4x5UsartType type; +}; + +#endif /* HW_STM32L4X5_USART_H */ diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c new file mode 100644 index 00000000000..62957ec3e59 --- /dev/null +++ b/hw/char/stm32l4x5_usart.c @@ -0,0 +1,396 @@ +/* + * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitte= r) + * + * Copyright (c) 2023 Arnaud Minier + * Copyright (c) 2023 In=C3=A8s Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart + * by Alistair Francis. + * The reference used is the STMicroElectronics RM0351 Reference manual + * for STM32L4x5 and STM32L4x6 advanced Arm =C2=AE -based 32-bit MCUs. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "chardev/char-fe.h" +#include "chardev/char-serial.h" +#include "migration/vmstate.h" +#include "hw/char/stm32l4x5_usart.h" +#include "hw/clock.h" +#include "hw/irq.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "hw/registerfields.h" +#include "trace.h" + + +REG32(CR1, 0x00) + FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */ + FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */ + FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */ + FIELD(CR1, DEAT, 21, 5) /* Driver Enable assertion time */ + FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */ + FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */ + FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */ + FIELD(CR1, MME, 13, 1) /* Mute mode enable */ + FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */ + FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */ + FIELD(CR1, PCE, 10, 1) /* Parity control enable */ + FIELD(CR1, PS, 9, 1) /* Parity selection */ + FIELD(CR1, PEIE, 8, 1) /* PE interrupt enable */ + FIELD(CR1, TXEIE, 7, 1) /* TXE interrupt enable */ + FIELD(CR1, TCIE, 6, 1) /* Transmission complete interrupt enable */ + FIELD(CR1, RXNEIE, 5, 1) /* RXNE interrupt enable */ + FIELD(CR1, IDLEIE, 4, 1) /* IDLE interrupt enable */ + FIELD(CR1, TE, 3, 1) /* Transmitter enable */ + FIELD(CR1, RE, 2, 1) /* Receiver enable */ + FIELD(CR1, UESM, 1, 1) /* USART enable in Stop mode */ + FIELD(CR1, UE, 0, 1) /* USART enable */ +REG32(CR2, 0x04) + FIELD(CR2, ADD_1, 28, 4) /* ADD[7:4] */ + FIELD(CR2, ADD_0, 24, 1) /* ADD[3:0] */ + FIELD(CR2, RTOEN, 23, 1) /* Receiver timeout enable */ + FIELD(CR2, ABRMOD, 21, 2) /* Auto baud rate mode */ + FIELD(CR2, ABREN, 20, 1) /* Auto baud rate enable */ + FIELD(CR2, MSBFIRST, 19, 1) /* Most significant bit first */ + FIELD(CR2, DATAINV, 18, 1) /* Binary data inversion */ + FIELD(CR2, TXINV, 17, 1) /* TX pin active level inversion */ + FIELD(CR2, RXINV, 16, 1) /* RX pin active level inversion */ + FIELD(CR2, SWAP, 15, 1) /* Swap RX/TX pins */ + FIELD(CR2, LINEN, 14, 1) /* LIN mode enable */ + FIELD(CR2, STOP, 12, 2) /* STOP bits */ + FIELD(CR2, CLKEN, 11, 1) /* Clock enable */ + FIELD(CR2, CPOL, 10, 1) /* Clock polarity */ + FIELD(CR2, CPHA, 9, 1) /* Clock phase */ + FIELD(CR2, LBCL, 8, 1) /* Last bit clock pulse */ + FIELD(CR2, LBDIE, 6, 1) /* LIN break detection interrupt enable */ + FIELD(CR2, LBDL, 5, 1) /* LIN break detection length */ + FIELD(CR2, ADDM7, 4, 1) /* 7-bit / 4-bit Address Detection */ + +REG32(CR3, 0x08) + /* TCBGTIE only on STM32L496xx/4A6xx devices */ + FIELD(CR3, UCESM, 23, 1) /* USART Clock Enable in Stop Mode */ + FIELD(CR3, WUFIE, 22, 1) /* Wakeup from Stop mode interrupt enable */ + FIELD(CR3, WUS, 20, 2) /* Wakeup from Stop mode interrupt flag sel= ection */ + FIELD(CR3, SCARCNT, 17, 3) /* Smartcard auto-retry count */ + FIELD(CR3, DEP, 15, 1) /* Driver enable polarity selection */ + FIELD(CR3, DEM, 14, 1) /* Driver enable mode */ + FIELD(CR3, DDRE, 13, 1) /* DMA Disable on Reception Error */ + FIELD(CR3, OVRDIS, 12, 1) /* Overrun Disable */ + FIELD(CR3, ONEBIT, 11, 1) /* One sample bit method enable */ + FIELD(CR3, CTSIE, 10, 1) /* CTS interrupt enable */ + FIELD(CR3, CTSE, 9, 1) /* CTS enable */ + FIELD(CR3, RTSE, 8, 1) /* RTS enable */ + FIELD(CR3, DMAT, 7, 1) /* DMA enable transmitter */ + FIELD(CR3, DMAR, 6, 1) /* DMA enable receiver */ + FIELD(CR3, SCEN, 5, 1) /* Smartcard mode enable */ + FIELD(CR3, NACK, 4, 1) /* Smartcard NACK enable */ + FIELD(CR3, HDSEL, 3, 1) /* Half-duplex selection */ + FIELD(CR3, IRLP, 2, 1) /* IrDA low-power */ + FIELD(CR3, IREN, 1, 1) /* IrDA mode enable */ + FIELD(CR3, EIE, 0, 1) /* Error interrupt enable */ +REG32(BRR, 0x0C) + FIELD(BRR, BRR, 0, 16) +REG32(GTPR, 0x10) + FIELD(GTPR, GT, 8, 8) /* Guard time value */ + FIELD(GTPR, PSC, 0, 8) /* Prescaler value */ +REG32(RTOR, 0x14) + FIELD(RTOR, BLEN, 24, 8) /* Block Length */ + FIELD(RTOR, RTO, 0, 24) /* Receiver timeout value */ +REG32(RQR, 0x18) + FIELD(RQR, TXFRQ, 4, 1) /* Transmit data flush request */ + FIELD(RQR, RXFRQ, 3, 1) /* Receive data flush request */ + FIELD(RQR, MMRQ, 2, 1) /* Mute mode request */ + FIELD(RQR, SBKRQ, 1, 1) /* Send break request */ + FIELD(RQR, ABBRRQ, 0, 1) /* Auto baud rate request */ +REG32(ISR, 0x1C) + /* TCBGT only for STM32L475xx/476xx/486xx devices */ + FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */ + FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */ + FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */ + FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */ + FIELD(ISR, SBKF, 18, 1) /* Send break flag */ + FIELD(ISR, CMF, 17, 1) /* Character match flag */ + FIELD(ISR, BUSY, 16, 1) /* Busy flag */ + FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */ + FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */ + FIELD(ISR, EOBF, 12, 1) /* End of block flag */ + FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */ + FIELD(ISR, CTS, 10, 1) /* CTS flag */ + FIELD(ISR, CTSIF, 9, 1) /* CTS interrupt flag */ + FIELD(ISR, LBDF, 8, 1) /* LIN break detection flag */ + FIELD(ISR, TXE, 7, 1) /* Transmit data register empty */ + FIELD(ISR, TC, 6, 1) /* Transmission complete */ + FIELD(ISR, RXNE, 5, 1) /* Read data register not empty */ + FIELD(ISR, IDLE, 4, 1) /* Idle line detected */ + FIELD(ISR, ORE, 3, 1) /* Overrun error */ + FIELD(ISR, NF, 2, 1) /* START bit Noise detection flag */ + FIELD(ISR, FE, 1, 1) /* Framing Error */ + FIELD(ISR, PE, 0, 1) /* Parity Error */ +REG32(ICR, 0x20) + FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */ + FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */ + FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */ + FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */ + FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */ + FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */ + /* TCBGTCF only on STM32L496xx/4A6xx devices */ + FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */ + FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */ + FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */ + FIELD(ICR, NCF, 2, 1) /* Noise detected clear flag */ + FIELD(ICR, FECF, 1, 1) /* Framing error clear flag */ + FIELD(ICR, PECF, 0, 1) /* Parity error clear flag */ +REG32(RDR, 0x24) + FIELD(RDR, RDR, 0, 9) +REG32(TDR, 0x28) + FIELD(TDR, TDR, 0, 9) + +static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) +{ + Stm32l4x5UsartBaseState *s =3D STM32L4X5_USART_BASE(obj); + + s->cr1 =3D 0x00000000; + s->cr2 =3D 0x00000000; + s->cr3 =3D 0x00000000; + s->brr =3D 0x00000000; + s->gtpr =3D 0x00000000; + s->rtor =3D 0x00000000; + s->isr =3D 0x020000C0; + s->rdr =3D 0x00000000; + s->tdr =3D 0x00000000; +} + +static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr, + unsigned int size) +{ + Stm32l4x5UsartBaseState *s =3D opaque; + uint64_t retvalue =3D 0; + + switch (addr) { + case A_CR1: + retvalue =3D s->cr1; + break; + case A_CR2: + retvalue =3D s->cr2; + break; + case A_CR3: + retvalue =3D s->cr3; + break; + case A_BRR: + retvalue =3D FIELD_EX32(s->brr, BRR, BRR); + break; + case A_GTPR: + retvalue =3D s->gtpr; + break; + case A_RTOR: + retvalue =3D s->rtor; + break; + case A_RQR: + /* RQR is a write only register */ + retvalue =3D 0x00000000; + break; + case A_ISR: + retvalue =3D s->isr; + break; + case A_ICR: + /* ICR is a clear register */ + retvalue =3D 0x00000000; + break; + case A_RDR: + retvalue =3D FIELD_EX32(s->rdr, RDR, RDR); + /* Reset RXNE flag */ + s->isr &=3D ~R_ISR_RXNE_MASK; + break; + case A_TDR: + retvalue =3D FIELD_EX32(s->tdr, TDR, TDR); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + break; + } + + trace_stm32l4x5_usart_read(addr, retvalue); + + return retvalue; +} + +static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Stm32l4x5UsartBaseState *s =3D opaque; + const uint32_t value =3D val64; + + trace_stm32l4x5_usart_write(addr, value); + + switch (addr) { + case A_CR1: + s->cr1 =3D value; + return; + case A_CR2: + s->cr2 =3D value; + return; + case A_CR3: + s->cr3 =3D value; + return; + case A_BRR: + s->brr =3D value; + return; + case A_GTPR: + s->gtpr =3D value; + return; + case A_RTOR: + s->rtor =3D value; + return; + case A_RQR: + return; + case A_ISR: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: ISR is read only !\n", __func__); + return; + case A_ICR: + /* Clear the status flags */ + s->isr &=3D ~value; + return; + case A_RDR: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: RDR is read only !\n", __func__); + return; + case A_TDR: + s->tdr =3D value; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + } +} + +static const MemoryRegionOps stm32l4x5_usart_base_ops =3D { + .read =3D stm32l4x5_usart_base_read, + .write =3D stm32l4x5_usart_base_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .max_access_size =3D 4, + .min_access_size =3D 4, + .unaligned =3D false + }, + .impl =3D { + .max_access_size =3D 4, + .min_access_size =3D 4, + .unaligned =3D false + }, +}; + +static Property stm32l4x5_usart_base_properties[] =3D { + DEFINE_PROP_CHR("chardev", Stm32l4x5UsartBaseState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void stm32l4x5_usart_base_init(Object *obj) +{ + Stm32l4x5UsartBaseState *s =3D STM32L4X5_USART_BASE(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &stm32l4x5_usart_base_ops, s, + TYPE_STM32L4X5_USART_BASE, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + s->clk =3D qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); +} + +static const VMStateDescription vmstate_stm32l4x5_usart_base =3D { + .name =3D TYPE_STM32L4X5_USART_BASE, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState), + VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState), + VMSTATE_UINT32(cr3, Stm32l4x5UsartBaseState), + VMSTATE_UINT32(brr, Stm32l4x5UsartBaseState), + VMSTATE_UINT32(gtpr, Stm32l4x5UsartBaseState), + VMSTATE_UINT32(rtor, Stm32l4x5UsartBaseState), + VMSTATE_UINT32(isr, Stm32l4x5UsartBaseState), + VMSTATE_UINT32(rdr, Stm32l4x5UsartBaseState), + VMSTATE_UINT32(tdr, Stm32l4x5UsartBaseState), + VMSTATE_CLOCK(clk, Stm32l4x5UsartBaseState), + VMSTATE_END_OF_LIST() + } +}; + + +static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp) +{ + ERRP_GUARD(); + Stm32l4x5UsartBaseState *s =3D STM32L4X5_USART_BASE(dev); + if (!clock_has_source(s->clk)) { + error_setg(errp, "USART clock must be wired up by SoC code"); + return; + } +} + +static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D stm32l4x5_usart_base_reset_hold; + device_class_set_props(dc, stm32l4x5_usart_base_properties); + dc->realize =3D stm32l4x5_usart_base_realize; + dc->vmsd =3D &vmstate_stm32l4x5_usart_base; +} + +static void stm32l4x5_usart_class_init(ObjectClass *oc, void *data) +{ + Stm32l4x5UsartBaseClass *subc =3D STM32L4X5_USART_BASE_CLASS(oc); + + subc->type =3D STM32L4x5_USART; +} + +static void stm32l4x5_uart_class_init(ObjectClass *oc, void *data) +{ + Stm32l4x5UsartBaseClass *subc =3D STM32L4X5_USART_BASE_CLASS(oc); + + subc->type =3D STM32L4x5_UART; +} + +static void stm32l4x5_lpuart_class_init(ObjectClass *oc, void *data) +{ + Stm32l4x5UsartBaseClass *subc =3D STM32L4X5_USART_BASE_CLASS(oc); + + subc->type =3D STM32L4x5_LPUART; +} + +static const TypeInfo stm32l4x5_usart_types[] =3D { + { + .name =3D TYPE_STM32L4X5_USART_BASE, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Stm32l4x5UsartBaseState), + .instance_init =3D stm32l4x5_usart_base_init, + .class_init =3D stm32l4x5_usart_base_class_init, + .abstract =3D true, + }, { + .name =3D TYPE_STM32L4X5_USART, + .parent =3D TYPE_STM32L4X5_USART_BASE, + .class_init =3D stm32l4x5_usart_class_init, + }, { + .name =3D TYPE_STM32L4X5_UART, + .parent =3D TYPE_STM32L4X5_USART_BASE, + .class_init =3D stm32l4x5_uart_class_init, + }, { + .name =3D TYPE_STM32L4X5_LPUART, + .parent =3D TYPE_STM32L4X5_USART_BASE, + .class_init =3D stm32l4x5_lpuart_class_init, + } +}; + +DEFINE_TYPES(stm32l4x5_usart_types) diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 6b6cf2fc1df..4fd74ea8788 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -41,6 +41,9 @@ config VIRTIO_SERIAL config STM32F2XX_USART bool =20 +config STM32L4X5_USART + bool + config CMSDK_APB_UART bool =20 diff --git a/hw/char/meson.build b/hw/char/meson.build index 006d20f1e25..e5b13b69580 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -31,6 +31,7 @@ system_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files(= 'renesas_sci.c')) system_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c')) system_ss.add(when: 'CONFIG_SH_SCI', if_true: files('sh_serial.c')) system_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_us= art.c')) +system_ss.add(when: 'CONFIG_STM32L4X5_USART', if_true: files('stm32l4x5_us= art.c')) system_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc= _mmuart.c')) system_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c')) system_ss.add(when: 'CONFIG_GOLDFISH_TTY', if_true: files('goldfish_tty.c'= )) diff --git a/hw/char/trace-events b/hw/char/trace-events index 7a398c82a57..689bed9e025 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -106,6 +106,10 @@ cadence_uart_baudrate(unsigned baudrate) "baudrate %u" sh_serial_read(char *id, unsigned size, uint64_t offs, uint64_t val) " %s = size %d offs 0x%02" PRIx64 " -> 0x%02" PRIx64 sh_serial_write(char *id, unsigned size, uint64_t offs, uint64_t val) "%s = size %d offs 0x%02" PRIx64 " <- 0x%02" PRIx64 =20 +# stm32l4x5_usart.c +stm32l4x5_usart_read(uint64_t addr, uint32_t data) "USART: Read <0x%" PRIx= 64 "> -> 0x%" PRIx32 "" +stm32l4x5_usart_write(uint64_t addr, uint32_t data) "USART: Write <0x%" PR= Ix64 "> <- 0x%" PRIx32 "" + # xen_console.c xen_console_connect(unsigned int idx, unsigned int ring_ref, unsigned int = port, unsigned int limit) "idx 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041618; x=1714646418; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=aqhmr43kxAUE3aXSGOVdjdHBPZAAakdUFpdCdVtyDcA=; b=p/Vu7unf0XwmPjgo+QOsPHhf9rywL052+KjZ8D6p1cleVl+BRVDjjhRAYDAsLS9Dak I53v4osYNN5wU8wIsZGsoPR1w9FnufKmzTOnMJfuZoF9dzYtC90iteGpzLB246VUWcUs pyqCX3znGcw7q0q5pSnENFwXynklHGHvrTxFW/luU89YAuj19QKvInux8iB5aG+MWL3D Tez+xmoBrhsy2StjUmPGEvPe1wePhL+TF6T+cCA96I65opGzEL4vZ7S1CsDC6ef2+6F1 WntRVgpw4Ru5uGRd8+X7CnE+3AAzLwfHj1Ksbdq6LEIkYJYjBZQUIafE1H+unJ5OZwe+ 6bZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041618; x=1714646418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aqhmr43kxAUE3aXSGOVdjdHBPZAAakdUFpdCdVtyDcA=; b=YKa+H5d8c2qT3rEcooJeb3cS/oRdGlP+hHdiSzBq8wijh0pa19oWRJL9iABYrYv/w1 b7oQZEKBDRntrIKx8awEDlD515vgtQo5psPgXTg26NdF4UYmKzlKig49WZOJFIe5rNMi 0JHNQY4/kGzMln1Rna8zgJ8qmEYqyMWgs/lCM9DfLwS7cvsPCikRWp0N8dmnzJPt3eqQ 2A4icJi7kXRD/fsNtHmE0cwPYo1byARADc3ufLqaiwTZxmvHK3vb5E/UQIzHQdWKE22I ZCf+JFnNwvBp69ZVVIxi29keMHfWyFAnfox0b2AVmD+6q5YVAaKgnD0V8n37xT5I4X86 Z0Kg== X-Gm-Message-State: AOJu0YyGS9hOMBWG7Igze8bfaMoE1mf0dRnXqvOVwo3kmtXbZN+tURYY vC+pEoFpAt+HrpEs0LhwRgjtDPeOWARJUAApNzh5cV55IneZdFlWYpoeo8Yq7T9faN6FVtYGedA 5 X-Google-Smtp-Source: AGHT+IHvLMm6ev0mifo0T/OuAlFFBLGxQ9ir69sBNUS7aPa+DUmWdvufRU0IQX2GSsHqKeohh59sBw== X-Received: by 2002:a05:6000:1243:b0:33e:6ef3:b68e with SMTP id j3-20020a056000124300b0033e6ef3b68emr1623866wrx.34.1714041617962; Thu, 25 Apr 2024 03:40:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/37] hw/char/stm32l4x5_usart: Enable serial read and write Date: Thu, 25 Apr 2024 11:39:55 +0100 Message-Id: <20240425103958.3237225-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041757391100003 From: Arnaud Minier Implement the ability to read and write characters to the usart using the serial port. The character transmission is based on the cmsdk-apb-uart implementation. Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell Message-id: 20240329174402.60382-3-arnaud.minier@telecom-paris.fr [PMM: fixed a few checkpatch nits] Signed-off-by: Peter Maydell --- include/hw/char/stm32l4x5_usart.h | 1 + hw/char/stm32l4x5_usart.c | 143 ++++++++++++++++++++++++++++++ hw/char/trace-events | 7 ++ 3 files changed, 151 insertions(+) diff --git a/include/hw/char/stm32l4x5_usart.h b/include/hw/char/stm32l4x5_= usart.h index 8d38a85a6e6..dd3866682a3 100644 --- a/include/hw/char/stm32l4x5_usart.h +++ b/include/hw/char/stm32l4x5_usart.h @@ -55,6 +55,7 @@ struct Stm32l4x5UsartBaseState { Clock *clk; CharBackend chr; qemu_irq irq; + guint watch_tag; }; =20 struct Stm32l4x5UsartBaseClass { diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index 62957ec3e59..755fc0bb5a3 100644 --- a/hw/char/stm32l4x5_usart.c +++ b/hw/char/stm32l4x5_usart.c @@ -154,6 +154,123 @@ REG32(RDR, 0x24) REG32(TDR, 0x28) FIELD(TDR, TDR, 0, 9) =20 +static void stm32l4x5_update_irq(Stm32l4x5UsartBaseState *s) +{ + if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) = || + ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) = || + ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) = || + ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) = || + ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) = || + ((s->isr & R_ISR_CTSIF_MASK) && (s->cr3 & R_CR3_CTSIE_MASK)) = || + ((s->isr & R_ISR_LBDF_MASK) && (s->cr2 & R_CR2_LBDIE_MASK)) = || + ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK)) = || + ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK)) = || + ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) = || + ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK)) = || + ((s->isr & R_ISR_ORE_MASK) && + ((s->cr1 & R_CR1_RXNEIE_MASK) || (s->cr3 & R_CR3_EIE_MASK))) = || + /* TODO: Handle NF ? */ + ((s->isr & R_ISR_FE_MASK) && (s->cr3 & R_CR3_EIE_MASK)) = || + ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) { + qemu_irq_raise(s->irq); + trace_stm32l4x5_usart_irq_raised(s->isr); + } else { + qemu_irq_lower(s->irq); + trace_stm32l4x5_usart_irq_lowered(); + } +} + +static int stm32l4x5_usart_base_can_receive(void *opaque) +{ + Stm32l4x5UsartBaseState *s =3D opaque; + + if (!(s->isr & R_ISR_RXNE_MASK)) { + return 1; + } + + return 0; +} + +static void stm32l4x5_usart_base_receive(void *opaque, const uint8_t *buf, + int size) +{ + Stm32l4x5UsartBaseState *s =3D opaque; + + if (!((s->cr1 & R_CR1_UE_MASK) && (s->cr1 & R_CR1_RE_MASK))) { + trace_stm32l4x5_usart_receiver_not_enabled( + FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE)); + return; + } + + /* Check if overrun detection is enabled and if there is an overrun */ + if (!(s->cr3 & R_CR3_OVRDIS_MASK) && (s->isr & R_ISR_RXNE_MASK)) { + /* + * A character has been received while + * the previous has not been read =3D Overrun. + */ + s->isr |=3D R_ISR_ORE_MASK; + trace_stm32l4x5_usart_overrun_detected(s->rdr, *buf); + } else { + /* No overrun */ + s->rdr =3D *buf; + s->isr |=3D R_ISR_RXNE_MASK; + trace_stm32l4x5_usart_rx(s->rdr); + } + + stm32l4x5_update_irq(s); +} + +/* + * Try to send tx data, and arrange to be called back later if + * we can't (ie the char backend is busy/blocking). + */ +static gboolean usart_transmit(void *do_not_use, GIOCondition cond, + void *opaque) +{ + Stm32l4x5UsartBaseState *s =3D STM32L4X5_USART_BASE(opaque); + int ret; + /* TODO: Handle 9 bits transmission */ + uint8_t ch =3D s->tdr; + + s->watch_tag =3D 0; + + if (!(s->cr1 & R_CR1_TE_MASK) || (s->isr & R_ISR_TXE_MASK)) { + return G_SOURCE_REMOVE; + } + + ret =3D qemu_chr_fe_write(&s->chr, &ch, 1); + if (ret <=3D 0) { + s->watch_tag =3D qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HU= P, + usart_transmit, s); + if (!s->watch_tag) { + /* + * Most common reason to be here is "no chardev backend": + * just insta-drain the buffer, so the serial output + * goes into a void, rather than blocking the guest. + */ + goto buffer_drained; + } + /* Transmit pending */ + trace_stm32l4x5_usart_tx_pending(); + return G_SOURCE_REMOVE; + } + +buffer_drained: + /* Character successfully sent */ + trace_stm32l4x5_usart_tx(ch); + s->isr |=3D R_ISR_TC_MASK | R_ISR_TXE_MASK; + stm32l4x5_update_irq(s); + return G_SOURCE_REMOVE; +} + +static void usart_cancel_transmit(Stm32l4x5UsartBaseState *s) +{ + if (s->watch_tag) { + g_source_remove(s->watch_tag); + s->watch_tag =3D 0; + } +} + static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) { Stm32l4x5UsartBaseState *s =3D STM32L4X5_USART_BASE(obj); @@ -167,6 +284,22 @@ static void stm32l4x5_usart_base_reset_hold(Object *ob= j, ResetType type) s->isr =3D 0x020000C0; s->rdr =3D 0x00000000; s->tdr =3D 0x00000000; + + usart_cancel_transmit(s); + stm32l4x5_update_irq(s); +} + +static void usart_update_rqr(Stm32l4x5UsartBaseState *s, uint32_t value) +{ + /* TXFRQ */ + /* Reset RXNE flag */ + if (value & R_RQR_RXFRQ_MASK) { + s->isr &=3D ~R_ISR_RXNE_MASK; + } + /* MMRQ */ + /* SBKRQ */ + /* ABRRQ */ + stm32l4x5_update_irq(s); } =20 static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr, @@ -209,6 +342,7 @@ static uint64_t stm32l4x5_usart_base_read(void *opaque,= hwaddr addr, retvalue =3D FIELD_EX32(s->rdr, RDR, RDR); /* Reset RXNE flag */ s->isr &=3D ~R_ISR_RXNE_MASK; + stm32l4x5_update_irq(s); break; case A_TDR: retvalue =3D FIELD_EX32(s->tdr, TDR, TDR); @@ -235,6 +369,7 @@ static void stm32l4x5_usart_base_write(void *opaque, hw= addr addr, switch (addr) { case A_CR1: s->cr1 =3D value; + stm32l4x5_update_irq(s); return; case A_CR2: s->cr2 =3D value; @@ -252,6 +387,7 @@ static void stm32l4x5_usart_base_write(void *opaque, hw= addr addr, s->rtor =3D value; return; case A_RQR: + usart_update_rqr(s, value); return; case A_ISR: qemu_log_mask(LOG_GUEST_ERROR, @@ -260,6 +396,7 @@ static void stm32l4x5_usart_base_write(void *opaque, hw= addr addr, case A_ICR: /* Clear the status flags */ s->isr &=3D ~value; + stm32l4x5_update_irq(s); return; case A_RDR: qemu_log_mask(LOG_GUEST_ERROR, @@ -267,6 +404,8 @@ static void stm32l4x5_usart_base_write(void *opaque, hw= addr addr, return; case A_TDR: s->tdr =3D value; + s->isr &=3D ~R_ISR_TXE_MASK; + usart_transmit(NULL, G_IO_OUT, s); return; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -336,6 +475,10 @@ static void stm32l4x5_usart_base_realize(DeviceState *= dev, Error **errp) error_setg(errp, "USART clock must be wired up by SoC code"); return; } + + qemu_chr_fe_set_handlers(&s->chr, stm32l4x5_usart_base_can_receive, + stm32l4x5_usart_base_receive, NULL, NULL, + s, NULL, true); } =20 static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/trace-events b/hw/char/trace-events index 689bed9e025..f22f0ee2bc5 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -109,6 +109,13 @@ sh_serial_write(char *id, unsigned size, uint64_t offs= , uint64_t val) "%s size % # stm32l4x5_usart.c stm32l4x5_usart_read(uint64_t addr, uint32_t data) "USART: Read <0x%" PRIx= 64 "> -> 0x%" PRIx32 "" stm32l4x5_usart_write(uint64_t addr, uint32_t data) "USART: Write <0x%" PR= Ix64 "> <- 0x%" PRIx32 "" +stm32l4x5_usart_rx(uint8_t c) "USART: got character 0x%x from backend" +stm32l4x5_usart_tx(uint8_t c) "USART: character 0x%x sent to backend" +stm32l4x5_usart_tx_pending(void) "USART: character send to backend pending" +stm32l4x5_usart_irq_raised(uint32_t reg) "USART: IRQ raised: 0x%08"PRIx32 +stm32l4x5_usart_irq_lowered(void) "USART: IRQ lowered" +stm32l4x5_usart_overrun_detected(uint8_t current, uint8_t received) "USART= : Overrun detected, RDR=3D'0x%x', received 0x%x" +stm32l4x5_usart_receiver_not_enabled(uint8_t ue_bit, uint8_t re_bit) "USAR= T: Receiver not enabled, UE=3D0x%x, RE=3D0x%x" =20 # xen_console.c xen_console_connect(unsigned int idx, unsigned int ring_ref, unsigned int = port, unsigned int limit) "idx %u ring_ref %u port %u limit %u" --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041618; x=1714646418; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4/OyvTVKZYtoEIJ/h2hDyr2SLAKjdy8KBH3pJgY2yh4=; b=q2hlwIajxDgiFrKKgq/LW0RuqVmvuL3Pz/e7zKJYBNYAjm+TT4gK+WkJQr/j4pKrdk LKHSdCvS2KckNqSUKrlmcfNSCLrZ+G25hAofwZh36K3TF0iorSBG2z5yRF6X11H2nhYE cgtgjs63BKLsZnGfDJVeZY3iii5+dvLuTdeuLjgSDdIIT7SPcae5EdYj8DI/YSkSGfVo 4KZx7qKegtZsJiXH7Bre6XHq/jiZ9ZHk34Dqb88o3tJkQlcdn+N0gAUoSLRCZysyB37M oaMpJLpIrWxXBGaKGGCawv7up/szujZr5zectGXPgAVBzCKzLm3pQYFgIE+dMb4Udau3 STcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041618; x=1714646418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4/OyvTVKZYtoEIJ/h2hDyr2SLAKjdy8KBH3pJgY2yh4=; b=kcCGIDfgGAQ4qJkfm49A5/e45mW5y0M+xeMfcEXS3HwIcPq7dGjYgToPnXkaZBgj0E w+XGIfzQLNZe2nqQxXXA04lyj27hc9ZzzZPie9m7/LiY3MbijAxeCfcXt4ETfY94P3mt BgtxKGxPTFIZjQhmVHhdFefBt1oF6lqPj6y/DMU9KBnAtciD7IAQ1iqQ2we9HpOEjEy1 P67/f9zCdOSN78SXsJSRFYYMOCfbhIFg3k1EwELo32XqG88MSe4QmnZwHb/xQZ7YhUkp BDuVcwcCtpPATFuo9iXqrhQsmHXOjs/rLbhmvFYtY89DYbBwwIwGIAmuusZnJUcwSPO5 S7sQ== X-Gm-Message-State: AOJu0YycgeOSMNQ06fclixcmpjX6Ne/uhOmak7ZOJ1h+Ux56tam+gB2N NlT612XLabACE9f2OQQ/F+5AeqjUkQN+iq0ybMPcykE+lfYf8p4a0nXZWydr/GX3W4ZuXBB3OEv u X-Google-Smtp-Source: AGHT+IFMgdibrCQP29pxwWw8qZX2PRWQLg531DZbH2GFnbFqzcNVHvr8ZWUe2ilxyg+3EnNSP4BGIg== X-Received: by 2002:a05:6000:912:b0:348:b435:273b with SMTP id cw18-20020a056000091200b00348b435273bmr4149126wrb.54.1714041618680; Thu, 25 Apr 2024 03:40:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/37] hw/char/stm32l4x5_usart: Add options for serial parameters setting Date: Thu, 25 Apr 2024 11:39:56 +0100 Message-Id: <20240425103958.3237225-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041998048100029 From: Arnaud Minier Add a function to change the settings of the serial connection. Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell Message-id: 20240329174402.60382-4-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell --- hw/char/stm32l4x5_usart.c | 98 +++++++++++++++++++++++++++++++++++++++ hw/char/trace-events | 1 + 2 files changed, 99 insertions(+) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index 755fc0bb5a3..2627aab8324 100644 --- a/hw/char/stm32l4x5_usart.c +++ b/hw/char/stm32l4x5_usart.c @@ -271,6 +271,92 @@ static void usart_cancel_transmit(Stm32l4x5UsartBaseSt= ate *s) } } =20 +static void stm32l4x5_update_params(Stm32l4x5UsartBaseState *s) +{ + int speed, parity, data_bits, stop_bits; + uint32_t value, usart_div; + QEMUSerialSetParams ssp; + + /* Select the parity type */ + if (s->cr1 & R_CR1_PCE_MASK) { + if (s->cr1 & R_CR1_PS_MASK) { + parity =3D 'O'; + } else { + parity =3D 'E'; + } + } else { + parity =3D 'N'; + } + + /* Select the number of stop bits */ + switch (FIELD_EX32(s->cr2, CR2, STOP)) { + case 0: + stop_bits =3D 1; + break; + case 2: + stop_bits =3D 2; + break; + default: + qemu_log_mask(LOG_UNIMP, + "UNIMPLEMENTED: fractionnal stop bits; CR2[13:12] =3D %u", + FIELD_EX32(s->cr2, CR2, STOP)); + return; + } + + /* Select the length of the word */ + switch ((FIELD_EX32(s->cr1, CR1, M1) << 1) | FIELD_EX32(s->cr1, CR1, M= 0)) { + case 0: + data_bits =3D 8; + break; + case 1: + data_bits =3D 9; + break; + case 2: + data_bits =3D 7; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "UNDEFINED: invalid word length, CR1.M =3D 0b11"); + return; + } + + /* Select the baud rate */ + value =3D FIELD_EX32(s->brr, BRR, BRR); + if (value < 16) { + qemu_log_mask(LOG_GUEST_ERROR, + "UNDEFINED: BRR less than 16: %u", value); + return; + } + + if (FIELD_EX32(s->cr1, CR1, OVER8) =3D=3D 0) { + /* + * Oversampling by 16 + * BRR =3D USARTDIV + */ + usart_div =3D value; + } else { + /* + * Oversampling by 8 + * - BRR[2:0] =3D USARTDIV[3:0] shifted 1 bit to the right. + * - BRR[3] must be kept cleared. + * - BRR[15:4] =3D USARTDIV[15:4] + * - The frequency is multiplied by 2 + */ + usart_div =3D ((value & 0xFFF0) | ((value & 0x0007) << 1)) / 2; + } + + speed =3D clock_get_hz(s->clk) / usart_div; + + ssp.speed =3D speed; + ssp.parity =3D parity; + ssp.data_bits =3D data_bits; + ssp.stop_bits =3D stop_bits; + + qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); + + trace_stm32l4x5_usart_update_params(speed, parity, data_bits, stop_bit= s); +} + static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) { Stm32l4x5UsartBaseState *s =3D STM32L4X5_USART_BASE(obj); @@ -369,16 +455,19 @@ static void stm32l4x5_usart_base_write(void *opaque, = hwaddr addr, switch (addr) { case A_CR1: s->cr1 =3D value; + stm32l4x5_update_params(s); stm32l4x5_update_irq(s); return; case A_CR2: s->cr2 =3D value; + stm32l4x5_update_params(s); return; case A_CR3: s->cr3 =3D value; return; case A_BRR: s->brr =3D value; + stm32l4x5_update_params(s); return; case A_GTPR: s->gtpr =3D value; @@ -447,10 +536,19 @@ static void stm32l4x5_usart_base_init(Object *obj) s->clk =3D qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); } =20 +static int stm32l4x5_usart_base_post_load(void *opaque, int version_id) +{ + Stm32l4x5UsartBaseState *s =3D (Stm32l4x5UsartBaseState *)opaque; + + stm32l4x5_update_params(s); + return 0; +} + static const VMStateDescription vmstate_stm32l4x5_usart_base =3D { .name =3D TYPE_STM32L4X5_USART_BASE, .version_id =3D 1, .minimum_version_id =3D 1, + .post_load =3D stm32l4x5_usart_base_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState), VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState), diff --git a/hw/char/trace-events b/hw/char/trace-events index f22f0ee2bc5..8875758076c 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -116,6 +116,7 @@ stm32l4x5_usart_irq_raised(uint32_t reg) "USART: IRQ ra= ised: 0x%08"PRIx32 stm32l4x5_usart_irq_lowered(void) "USART: IRQ lowered" stm32l4x5_usart_overrun_detected(uint8_t current, uint8_t received) "USART= : Overrun detected, RDR=3D'0x%x', received 0x%x" stm32l4x5_usart_receiver_not_enabled(uint8_t ue_bit, uint8_t re_bit) "USAR= T: Receiver not enabled, UE=3D0x%x, RE=3D0x%x" +stm32l4x5_usart_update_params(int speed, uint8_t parity, int data, int sto= p) "USART: speed: %d, parity: %c, data bits: %d, stop bits: %d" =20 # xen_console.c xen_console_connect(unsigned int idx, unsigned int ring_ref, unsigned int = port, unsigned int limit) "idx %u ring_ref %u port %u limit %u" --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h15-20020a056000000f00b003434c764f01sm19485768wrx.107.2024.04.25.03.40.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 03:40:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714041619; x=1714646419; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2nRYCIjCuWG0oRIavpGdg9fYE7VNVQ46mPL/bZDIFQQ=; b=d2V7NAsXi87tUaRQiWmoLkr0YQPFWhfLXZJhHsREwnJCHfwehDTT4acbLSyfpz4yPz rlIjoaTVcPdLkOi9uy9eh0srJqDxWczKlmOY9ijAx7O+jBjjIfzMl0fgrGj+FqsWvmXF deykGltdu7THDZfZYsw1gcK6IVXyYKUozaTkmXq6bNeSHD5AXh4JUiT8erkWbC492KpO ELbNuT/64xXXjss0qAAVv9p9zDgNPEz4UcJP/J8YfAWP2cvtDNLcRiLL60m9hrED3FMy h/Alx+eb5k7Yq8OrSD9MUg5eleUh3dHIKRcfjfk+vBn75Lj30aGQz+PAI7a/06a+6+CM GxeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714041619; x=1714646419; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2nRYCIjCuWG0oRIavpGdg9fYE7VNVQ46mPL/bZDIFQQ=; b=dCac7gggQBw/8fyUfUE9st0rL1c3CrYQgjsSUIcG/mMBffYXkxOwsdI472SZYxO9Kl rA6Hw+J2cp9glrZTEJ8FktxR03fMeOJryqcbSLPVtcHo1P77qiab41A10RALTRk2moGH 5BZQBzAFTVN2TXUlxWeX4G/m1OlJvr99y+C2lXzM+w95q+cCVIZ/A4TVFgDdYN7r+YcK 7Yl5v3PHpWLe18DrzSTOatW37iMnOMoSjohBBAUr+V4VBj6yvk/gJ39+DzkSJDp/nuhv C/fI+cVbThitfxc77jeYxIebXkXBPeZb9M+yiv9BEzf3OpnINebZbHVhJdRUycLp9JD8 y5gg== X-Gm-Message-State: AOJu0Ywj7zKNNcmSYrhVHh9M54vR523J53qcOHb8S+b2s7BtTfrO9Q5d afA2Zg3IkA187x2JIgizooDzVj7SaBBY7oytnMNOkvpKZ6X0sIXpGqfcoqW2n3xUGOminXeh4jZ c X-Google-Smtp-Source: AGHT+IE+SwhApnyakaA2eazsLxxYWqK2bNgxAnKwuAK/hQ9k4GjcnsHhvquobdFOLNpMOuYli3z3Cw== X-Received: by 2002:a5d:6e5d:0:b0:34b:1f34:9c06 with SMTP id j29-20020a5d6e5d000000b0034b1f349c06mr3670361wrz.24.1714041619112; Thu, 25 Apr 2024 03:40:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/37] hw/arm: Add the USART to the stm32l4x5 SoC Date: Thu, 25 Apr 2024 11:39:57 +0100 Message-Id: <20240425103958.3237225-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425103958.3237225-1-peter.maydell@linaro.org> References: <20240425103958.3237225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041675120100004 From: Arnaud Minier Add the USART to the SoC and connect it to the other implemented devices. Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell Message-id: 20240329174402.60382-5-arnaud.minier@telecom-paris.fr [PMM: fixed a few checkpatch nits] Signed-off-by: Peter Maydell --- docs/system/arm/b-l475e-iot01a.rst | 2 +- include/hw/arm/stm32l4x5_soc.h | 7 +++ hw/arm/stm32l4x5_soc.c | 83 +++++++++++++++++++++++++++--- hw/arm/Kconfig | 1 + 4 files changed, 86 insertions(+), 7 deletions(-) diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-i= ot01a.rst index 0afef8e4f45..a76c9976c50 100644 --- a/docs/system/arm/b-l475e-iot01a.rst +++ b/docs/system/arm/b-l475e-iot01a.rst @@ -19,13 +19,13 @@ Currently B-L475E-IOT01A machine's only supports the fo= llowing devices: - STM32L4x5 SYSCFG (System configuration controller) - STM32L4x5 RCC (Reset and clock control) - STM32L4x5 GPIOs (General-purpose I/Os) +- STM32L4x5 USARTs, UARTs and LPUART (Serial ports) =20 Missing devices """"""""""""""" =20 The B-L475E-IOT01A does *not* support the following devices: =20 -- Serial ports (UART) - Analog to Digital Converter (ADC) - SPI controller - Timer controller (TIMER) diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h index ee5f3624055..c243fb0e7f9 100644 --- a/include/hw/arm/stm32l4x5_soc.h +++ b/include/hw/arm/stm32l4x5_soc.h @@ -31,6 +31,7 @@ #include "hw/misc/stm32l4x5_exti.h" #include "hw/misc/stm32l4x5_rcc.h" #include "hw/gpio/stm32l4x5_gpio.h" +#include "hw/char/stm32l4x5_usart.h" #include "qom/object.h" =20 #define TYPE_STM32L4X5_SOC "stm32l4x5-soc" @@ -41,6 +42,9 @@ OBJECT_DECLARE_TYPE(Stm32l4x5SocState, Stm32l4x5SocClass,= STM32L4X5_SOC) =20 #define NUM_EXTI_OR_GATES 4 =20 +#define STM_NUM_USARTS 3 +#define STM_NUM_UARTS 2 + struct Stm32l4x5SocState { SysBusDevice parent_obj; =20 @@ -51,6 +55,9 @@ struct Stm32l4x5SocState { Stm32l4x5SyscfgState syscfg; Stm32l4x5RccState rcc; Stm32l4x5GpioState gpio[NUM_GPIOS]; + Stm32l4x5UsartBaseState usart[STM_NUM_USARTS]; + Stm32l4x5UsartBaseState uart[STM_NUM_UARTS]; + Stm32l4x5UsartBaseState lpuart; =20 MemoryRegion sram1; MemoryRegion sram2; diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 40e294f838f..39924822f3d 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -28,6 +28,7 @@ #include "sysemu/sysemu.h" #include "hw/or-irq.h" #include "hw/arm/stm32l4x5_soc.h" +#include "hw/char/stm32l4x5_usart.h" #include "hw/gpio/stm32l4x5_gpio.h" #include "hw/qdev-clock.h" #include "hw/misc/unimp.h" @@ -116,6 +117,22 @@ static const struct { { 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 }, }; =20 +static const hwaddr usart_addr[] =3D { + 0x40013800, /* "USART1", 0x400 */ + 0x40004400, /* "USART2", 0x400 */ + 0x40004800, /* "USART3", 0x400 */ +}; +static const hwaddr uart_addr[] =3D { + 0x40004C00, /* "UART4" , 0x400 */ + 0x40005000 /* "UART5" , 0x400 */ +}; + +#define LPUART_BASE_ADDRESS 0x40008000 + +static const int usart_irq[] =3D { 37, 38, 39 }; +static const int uart_irq[] =3D { 52, 53 }; +#define LPUART_IRQ 70 + static void stm32l4x5_soc_initfn(Object *obj) { Stm32l4x5SocState *s =3D STM32L4X5_SOC(obj); @@ -132,6 +149,18 @@ static void stm32l4x5_soc_initfn(Object *obj) g_autofree char *name =3D g_strdup_printf("gpio%c", 'a' + i); object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPI= O); } + + for (int i =3D 0; i < STM_NUM_USARTS; i++) { + object_initialize_child(obj, "usart[*]", &s->usart[i], + TYPE_STM32L4X5_USART); + } + + for (int i =3D 0; i < STM_NUM_UARTS; i++) { + object_initialize_child(obj, "uart[*]", &s->uart[i], + TYPE_STM32L4X5_UART); + } + object_initialize_child(obj, "lpuart1", &s->lpuart, + TYPE_STM32L4X5_LPUART); } =20 static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) @@ -279,6 +308,54 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc= , Error **errp) sysbus_mmio_map(busdev, 0, RCC_BASE_ADDRESS); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, RCC_IRQ)); =20 + /* USART devices */ + for (int i =3D 0; i < STM_NUM_USARTS; i++) { + g_autofree char *name =3D g_strdup_printf("usart%d-out", i + 1); + dev =3D DEVICE(&(s->usart[i])); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + qdev_connect_clock_in(dev, "clk", + qdev_get_clock_out(DEVICE(&(s->rcc)), name)); + busdev =3D SYS_BUS_DEVICE(dev); + if (!sysbus_realize(busdev, errp)) { + return; + } + sysbus_mmio_map(busdev, 0, usart_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i= ])); + } + + /* + * TODO: Connect the USARTs, UARTs and LPUART to the EXTI once the EXTI + * can handle other gpio-in than the gpios. (e.g. Direct Lines for the + * usarts) + */ + + /* UART devices */ + for (int i =3D 0; i < STM_NUM_UARTS; i++) { + g_autofree char *name =3D g_strdup_printf("uart%d-out", STM_NUM_US= ARTS + i + 1); + dev =3D DEVICE(&(s->uart[i])); + qdev_prop_set_chr(dev, "chardev", serial_hd(STM_NUM_USARTS + i)); + qdev_connect_clock_in(dev, "clk", + qdev_get_clock_out(DEVICE(&(s->rcc)), name)); + busdev =3D SYS_BUS_DEVICE(dev); + if (!sysbus_realize(busdev, errp)) { + return; + } + sysbus_mmio_map(busdev, 0, uart_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, uart_irq[i]= )); + } + + /* LPUART device*/ + dev =3D DEVICE(&(s->lpuart)); + qdev_prop_set_chr(dev, "chardev", serial_hd(STM_NUM_USARTS + STM_NUM_U= ARTS)); + qdev_connect_clock_in(dev, "clk", + qdev_get_clock_out(DEVICE(&(s->rcc)), "lpuart1-out")); + busdev =3D SYS_BUS_DEVICE(dev); + if (!sysbus_realize(busdev, errp)) { + return; + } + sysbus_mmio_map(busdev, 0, LPUART_BASE_ADDRESS); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, LPUART_IRQ)); + /* APB1 BUS */ create_unimplemented_device("TIM2", 0x40000000, 0x400); create_unimplemented_device("TIM3", 0x40000400, 0x400); @@ -294,10 +371,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc= , Error **errp) create_unimplemented_device("SPI2", 0x40003800, 0x400); create_unimplemented_device("SPI3", 0x40003C00, 0x400); /* RESERVED: 0x40004000, 0x400 */ - create_unimplemented_device("USART2", 0x40004400, 0x400); - create_unimplemented_device("USART3", 0x40004800, 0x400); - create_unimplemented_device("UART4", 0x40004C00, 0x400); - create_unimplemented_device("UART5", 0x40005000, 0x400); create_unimplemented_device("I2C1", 0x40005400, 0x400); create_unimplemented_device("I2C2", 0x40005800, 0x400); create_unimplemented_device("I2C3", 0x40005C00, 0x400); @@ -308,7 +381,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) create_unimplemented_device("DAC1", 0x40007400, 0x400); create_unimplemented_device("OPAMP", 0x40007800, 0x400); create_unimplemented_device("LPTIM1", 0x40007C00, 0x400); - create_unimplemented_device("LPUART1", 0x40008000, 0x400); /* RESERVED: 0x40008400, 0x400 */ create_unimplemented_device("SWPMI1", 0x40008800, 0x400); /* RESERVED: 0x40008C00, 0x800 */ @@ -325,7 +397,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) create_unimplemented_device("TIM1", 0x40012C00, 0x400); create_unimplemented_device("SPI1", 0x40013000, 0x400); create_unimplemented_device("TIM8", 0x40013400, 0x400); - create_unimplemented_device("USART1", 0x40013800, 0x400); /* RESERVED: 0x40013C00, 0x400 */ create_unimplemented_device("TIM15", 0x40014000, 0x400); create_unimplemented_device("TIM16", 0x40014400, 0x400); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 893a7bff66b..098d0433753 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -477,6 +477,7 @@ config STM32L4X5_SOC select STM32L4X5_SYSCFG select STM32L4X5_RCC select STM32L4X5_GPIO + select STM32L4X5_USART =20 config XLNX_ZYNQMP_ARM bool --=20 2.34.1 From nobody Sat May 18 18:27:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714041731304100001 From: Arnaud Minier Test: - read/write from/to the usart registers - send/receive a character/string over the serial port Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell Message-id: 20240329174402.60382-6-arnaud.minier@telecom-paris.fr [PMM: fix checkpatch nits, remove commented out code] Signed-off-by: Peter Maydell --- tests/qtest/stm32l4x5_usart-test.c | 315 +++++++++++++++++++++++++++++ tests/qtest/meson.build | 4 +- 2 files changed, 318 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/stm32l4x5_usart-test.c diff --git a/tests/qtest/stm32l4x5_usart-test.c b/tests/qtest/stm32l4x5_usa= rt-test.c new file mode 100644 index 00000000000..89025182331 --- /dev/null +++ b/tests/qtest/stm32l4x5_usart-test.c @@ -0,0 +1,315 @@ +/* + * QTest testcase for STML4X5_USART + * + * Copyright (c) 2023 Arnaud Minier + * Copyright (c) 2023 In=C3=A8s Varhol + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "hw/misc/stm32l4x5_rcc_internals.h" +#include "hw/registerfields.h" + +#define RCC_BASE_ADDR 0x40021000 +/* Use USART 1 ADDR, assume the others work the same */ +#define USART1_BASE_ADDR 0x40013800 + +/* See stm32l4x5_usart for definitions */ +REG32(CR1, 0x00) + FIELD(CR1, M1, 28, 1) + FIELD(CR1, OVER8, 15, 1) + FIELD(CR1, M0, 12, 1) + FIELD(CR1, PCE, 10, 1) + FIELD(CR1, TXEIE, 7, 1) + FIELD(CR1, RXNEIE, 5, 1) + FIELD(CR1, TE, 3, 1) + FIELD(CR1, RE, 2, 1) + FIELD(CR1, UE, 0, 1) +REG32(CR2, 0x04) +REG32(CR3, 0x08) + FIELD(CR3, OVRDIS, 12, 1) +REG32(BRR, 0x0C) +REG32(GTPR, 0x10) +REG32(RTOR, 0x14) +REG32(RQR, 0x18) +REG32(ISR, 0x1C) + FIELD(ISR, TXE, 7, 1) + FIELD(ISR, RXNE, 5, 1) + FIELD(ISR, ORE, 3, 1) +REG32(ICR, 0x20) +REG32(RDR, 0x24) +REG32(TDR, 0x28) + +#define NVIC_ISPR1 0XE000E204 +#define NVIC_ICPR1 0xE000E284 +#define USART1_IRQ 37 + +static bool check_nvic_pending(QTestState *qts, unsigned int n) +{ + /* No USART interrupts are less than 32 */ + assert(n > 32); + n -=3D 32; + return qtest_readl(qts, NVIC_ISPR1) & (1 << n); +} + +static bool clear_nvic_pending(QTestState *qts, unsigned int n) +{ + /* No USART interrupts are less than 32 */ + assert(n > 32); + n -=3D 32; + qtest_writel(qts, NVIC_ICPR1, (1 << n)); + return true; +} + +/* + * Wait indefinitely for the flag to be updated. + * If this is run on a slow CI runner, + * the meson harness will timeout after 10 minutes for us. + */ +static bool usart_wait_for_flag(QTestState *qts, uint32_t event_addr, + uint32_t flag) +{ + while (true) { + if ((qtest_readl(qts, event_addr) & flag)) { + return true; + } + g_usleep(1000); + } + + return false; +} + +static void usart_receive_string(QTestState *qts, int sock_fd, const char = *in, + char *out) +{ + int i, in_len =3D strlen(in); + + g_assert_true(send(sock_fd, in, in_len, 0) =3D=3D in_len); + for (i =3D 0; i < in_len; i++) { + g_assert_true(usart_wait_for_flag(qts, + USART1_BASE_ADDR + A_ISR, R_ISR_RXNE_MASK)); + out[i] =3D qtest_readl(qts, USART1_BASE_ADDR + A_RDR); + } + out[i] =3D '\0'; +} + +static void usart_send_string(QTestState *qts, const char *in) +{ + int i, in_len =3D strlen(in); + + for (i =3D 0; i < in_len; i++) { + qtest_writel(qts, USART1_BASE_ADDR + A_TDR, in[i]); + g_assert_true(usart_wait_for_flag(qts, + USART1_BASE_ADDR + A_ISR, R_ISR_TXE_MASK)); + } +} + +/* Init the RCC clocks to run at 80 MHz */ +static void init_clocks(QTestState *qts) +{ + uint32_t value; + + /* MSIRANGE can be set only when MSI is OFF or READY */ + qtest_writel(qts, (RCC_BASE_ADDR + A_CR), R_CR_MSION_MASK); + + /* Clocking from MSI, in case MSI was not the default source */ + qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), 0); + + /* + * Update PLL and set MSI as the source clock. + * PLLM =3D 1 --> 000 + * PLLN =3D 40 --> 40 + * PPLLR =3D 2 --> 00 + * PLLDIV =3D unused, PLLP =3D unused (SAI3), PLLQ =3D unused (48M1) + * SRC =3D MSI --> 01 + */ + qtest_writel(qts, (RCC_BASE_ADDR + A_PLLCFGR), R_PLLCFGR_PLLREN_MASK | + (40 << R_PLLCFGR_PLLN_SHIFT) | + (0b01 << R_PLLCFGR_PLLSRC_SHIFT)); + + /* PLL activation */ + + value =3D qtest_readl(qts, (RCC_BASE_ADDR + A_CR)); + qtest_writel(qts, (RCC_BASE_ADDR + A_CR), value | R_CR_PLLON_MASK); + + /* RCC_CFGR is OK by defaut */ + qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), 0); + + /* CCIPR : no periph clock by default */ + qtest_writel(qts, (RCC_BASE_ADDR + A_CCIPR), 0); + + /* Switches on the PLL clock source */ + value =3D qtest_readl(qts, (RCC_BASE_ADDR + A_CFGR)); + qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), (value & ~R_CFGR_SW_MASK) | + (0b11 << R_CFGR_SW_SHIFT)); + + /* Enable SYSCFG clock enabled */ + qtest_writel(qts, (RCC_BASE_ADDR + A_APB2ENR), R_APB2ENR_SYSCFGEN_MASK= ); + + /* Enable the IO port B clock (See p.252) */ + qtest_writel(qts, (RCC_BASE_ADDR + A_AHB2ENR), R_AHB2ENR_GPIOBEN_MASK); + + /* Enable the clock for USART1 (cf p.259) */ + /* We rewrite SYSCFGEN to not disable it */ + qtest_writel(qts, (RCC_BASE_ADDR + A_APB2ENR), + R_APB2ENR_SYSCFGEN_MASK | R_APB2ENR_USART1EN_MASK); + + /* TODO: Enable usart via gpio */ + + /* Set PCLK as the clock for USART1(cf p.272) i.e. reset both bits */ + qtest_writel(qts, (RCC_BASE_ADDR + A_CCIPR), 0); + + /* Reset USART1 (see p.249) */ + qtest_writel(qts, (RCC_BASE_ADDR + A_APB2RSTR), 1 << 14); + qtest_writel(qts, (RCC_BASE_ADDR + A_APB2RSTR), 0); +} + +static void init_uart(QTestState *qts) +{ + uint32_t cr1; + + init_clocks(qts); + + /* + * For 115200 bauds, see p.1349. + * The clock has a frequency of 80Mhz, + * for 115200, we have to put a divider of 695 =3D 0x2B7. + */ + qtest_writel(qts, (USART1_BASE_ADDR + A_BRR), 0x2B7); + + /* + * Set the oversampling by 16, + * disable the parity control and + * set the word length to 8. (cf p.1377) + */ + cr1 =3D qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); + cr1 &=3D ~(R_CR1_M1_MASK | R_CR1_M0_MASK | R_CR1_OVER8_MASK | R_CR1_PC= E_MASK); + qtest_writel(qts, (USART1_BASE_ADDR + A_CR1), cr1); + + /* Enable the transmitter, the receiver and the USART. */ + qtest_writel(qts, (USART1_BASE_ADDR + A_CR1), + R_CR1_UE_MASK | R_CR1_RE_MASK | R_CR1_TE_MASK); +} + +static void test_write_read(void) +{ + QTestState *qts =3D qtest_init("-M b-l475e-iot01a"); + + /* Test that we can write and retrieve a value from the device */ + qtest_writel(qts, USART1_BASE_ADDR + A_TDR, 0xFFFFFFFF); + const uint32_t tdr =3D qtest_readl(qts, USART1_BASE_ADDR + A_TDR); + g_assert_cmpuint(tdr, =3D=3D, 0x000001FF); +} + +static void test_receive_char(void) +{ + int sock_fd; + uint32_t cr1; + QTestState *qts =3D qtest_init_with_serial("-M b-l475e-iot01a", &sock_= fd); + + init_uart(qts); + + /* Try without initializing IRQ */ + g_assert_true(send(sock_fd, "a", 1, 0) =3D=3D 1); + usart_wait_for_flag(qts, USART1_BASE_ADDR + A_ISR, R_ISR_RXNE_MASK); + g_assert_cmphex(qtest_readl(qts, USART1_BASE_ADDR + A_RDR), =3D=3D, 'a= '); + g_assert_false(check_nvic_pending(qts, USART1_IRQ)); + + /* Now with the IRQ */ + cr1 =3D qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); + cr1 |=3D R_CR1_RXNEIE_MASK; + qtest_writel(qts, USART1_BASE_ADDR + A_CR1, cr1); + g_assert_true(send(sock_fd, "b", 1, 0) =3D=3D 1); + usart_wait_for_flag(qts, USART1_BASE_ADDR + A_ISR, R_ISR_RXNE_MASK); + g_assert_cmphex(qtest_readl(qts, USART1_BASE_ADDR + A_RDR), =3D=3D, 'b= '); + g_assert_true(check_nvic_pending(qts, USART1_IRQ)); + clear_nvic_pending(qts, USART1_IRQ); + + close(sock_fd); + + qtest_quit(qts); +} + +static void test_send_char(void) +{ + int sock_fd; + char s[1]; + uint32_t cr1; + QTestState *qts =3D qtest_init_with_serial("-M b-l475e-iot01a", &sock_= fd); + + init_uart(qts); + + /* Try without initializing IRQ */ + qtest_writel(qts, USART1_BASE_ADDR + A_TDR, 'c'); + g_assert_true(recv(sock_fd, s, 1, 0) =3D=3D 1); + g_assert_cmphex(s[0], =3D=3D, 'c'); + g_assert_false(check_nvic_pending(qts, USART1_IRQ)); + + /* Now with the IRQ */ + cr1 =3D qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); + cr1 |=3D R_CR1_TXEIE_MASK; + qtest_writel(qts, USART1_BASE_ADDR + A_CR1, cr1); + qtest_writel(qts, USART1_BASE_ADDR + A_TDR, 'd'); + g_assert_true(recv(sock_fd, s, 1, 0) =3D=3D 1); + g_assert_cmphex(s[0], =3D=3D, 'd'); + g_assert_true(check_nvic_pending(qts, USART1_IRQ)); + clear_nvic_pending(qts, USART1_IRQ); + + close(sock_fd); + + qtest_quit(qts); +} + +static void test_receive_str(void) +{ + int sock_fd; + char s[10]; + QTestState *qts =3D qtest_init_with_serial("-M b-l475e-iot01a", &sock_= fd); + + init_uart(qts); + + usart_receive_string(qts, sock_fd, "hello", s); + g_assert_true(memcmp(s, "hello", 5) =3D=3D 0); + + close(sock_fd); + + qtest_quit(qts); +} + +static void test_send_str(void) +{ + int sock_fd; + char s[10]; + QTestState *qts =3D qtest_init_with_serial("-M b-l475e-iot01a", &sock_= fd); + + init_uart(qts); + + usart_send_string(qts, "world"); + g_assert_true(recv(sock_fd, s, 10, 0) =3D=3D 5); + g_assert_true(memcmp(s, "world", 5) =3D=3D 0); + + close(sock_fd); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + g_test_set_nonfatal_assertions(); + + qtest_add_func("stm32l4x5/usart/write_read", test_write_read); + qtest_add_func("stm32l4x5/usart/receive_char", test_receive_char); + qtest_add_func("stm32l4x5/usart/send_char", test_send_char); + qtest_add_func("stm32l4x5/usart/receive_str", test_receive_str); + qtest_add_func("stm32l4x5/usart/send_str", test_send_str); + ret =3D g_test_run(); + + return ret; +} + diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 36c5c13a7bb..b128fa5a4bd 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -7,6 +7,7 @@ slow_qtests =3D { 'npcm7xx_pwm-test': 300, 'npcm7xx_watchdog_timer-test': 120, 'qom-test' : 900, + 'stm32l4x5_usart-test' : 600, 'test-hmp' : 240, 'pxe-test': 610, 'prom-env-test': 360, @@ -205,7 +206,8 @@ qtests_stm32l4x5 =3D \ ['stm32l4x5_exti-test', 'stm32l4x5_syscfg-test', 'stm32l4x5_rcc-test', - 'stm32l4x5_gpio-test'] + 'stm32l4x5_gpio-test', + 'stm32l4x5_usart-test'] =20 qtests_arm =3D \ (config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \ --=20 2.34.1