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([156.19.246.23]) by smtp.gmail.com with ESMTPSA id t6-20020a170902e84600b001e604438791sm12465715plg.156.2024.04.24.17.00.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Apr 2024 17:00:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714003242; x=1714608042; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4yo5eUFmz1IcDDJEMMrGiy92xmplC4MQffE0DBG1K4o=; b=wQLeLrsenr6BIj3C/63pL/9gZuP4vo0Iq56CnqAFuxUE8g3Yrrbty/p18zpPTtdBd5 N+4MKIA8AOGuLg4IUEz5XQRBNvl/wUvHGJ8wo4rAEzFgVJPOj+J5zjz564ujVVwjnVYh gLG52ytMaHyhJfchqJYoaqBjeGNHhykowY1LS96OUQ7+3xq/numwnXt+fGKtb2NhjYp7 6qFNVocoem13DtsjvLDcVlbLCJ88dNlYDuQkkR1W36jwpGw8EegnwE5v9pJihIdfFa6V T4mO1IUfuAS6hAIIkVe6k402izL6VmpgqqagzZMdyEaETBmIdCrthHd5iArXWCnN9CTI +0EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714003242; x=1714608042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4yo5eUFmz1IcDDJEMMrGiy92xmplC4MQffE0DBG1K4o=; b=rviQHSkFlnDC5t5MNK77d0Ipo03+5Kt9uXSYlzNAbhFDO9+xyJH5oA0QTmmfrfI7xM TawVAuZDlxPEULcnrg17hZbxmIJph6SYU7sF8vq6Q1109ngPqq+D8fq58Z7fmuuhmWeS 9A+KJhEVPo992bBMMCW/JveQgZqnVECOtjPYTPIOYxy6Cvmaivz/nDJuC+fiDNmlUa5F yXwSQ1WGUrZNedv+52Bo7s3j29AXqw6D+spHR0uO7Pbh79GHFF0BxfzSqhWu7Vb6BcAc zU15qB71+U67UcxmzuCtWU0gCikA8A0KZ2wzm+PbPVeq8mJWsIHJi7HlBqtj5K/R8CZS ijaQ== X-Gm-Message-State: AOJu0YzuXYviGir7ffxVn3880jX3Gm9Iz4q6a2POG8UmoEf903qE8auA B6pzFpprAPqnxnjXkJF11Ta+vdbBz9i92zm0bk8eIkg7EnlYyDyXyNJTTqzDojIYzGJVXenL5hj 7 X-Google-Smtp-Source: AGHT+IFbxHiGfi+/wlfCBNYPgAd1nGV7UiSElWsXJzzb+7rDgNKOTgZyTgVh7EzWWP27Nv8nK01Yaw== X-Received: by 2002:a17:902:6b44:b0:1e8:b669:e65c with SMTP id g4-20020a1709026b4400b001e8b669e65cmr3907404plt.32.1714003241926; Wed, 24 Apr 2024 17:00:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 17/45] target/hppa: Introduce and use DisasIAQE for branch management Date: Wed, 24 Apr 2024 16:59:55 -0700 Message-Id: <20240425000023.1002026-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240425000023.1002026-1-richard.henderson@linaro.org> References: <20240425000023.1002026-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714003325511100001 Content-Type: text/plain; charset="utf-8" Wrap offset and space together in one structure, ensuring that they're copied together as required. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 378 +++++++++++++++++++++------------------- 1 file changed, 198 insertions(+), 180 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index dd5193cb6a..9d3bffb688 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -41,21 +41,23 @@ typedef struct DisasCond { TCGv_i64 a0, a1; } DisasCond; =20 +typedef struct DisasIAQE { + /* IASQ; may be null for no change from TB. */ + TCGv_i64 space; + /* IAOQ base; may be null for immediate absolute address. */ + TCGv_i64 base; + /* IAOQ addend; absolute immedate address if base is null. */ + int64_t disp; +} DisasIAQE; + typedef struct DisasContext { DisasContextBase base; CPUState *cs; =20 - uint64_t iaoq_f; - uint64_t iaoq_b; - uint64_t iaoq_n; - TCGv_i64 iaoq_n_var; - /* - * Null when IASQ_Back unchanged from IASQ_Front, - * or cpu_iasq_b, when IASQ_Back has been changed. - */ - TCGv_i64 iasq_b; - /* Null when IASQ_Next unchanged from IASQ_Back, or set by branch. */ - TCGv_i64 iasq_n; + /* IAQ_Front, IAQ_Back. */ + DisasIAQE iaq_f, iaq_b; + /* IAQ_Next, for jumps, otherwise null for simple advance. */ + DisasIAQE iaq_j, *iaq_n; =20 DisasCond null_cond; TCGLabel *null_lab; @@ -601,49 +603,67 @@ static bool nullify_end(DisasContext *ctx) return true; } =20 +static bool iaqe_variable(const DisasIAQE *e) +{ + return e->base || e->space; +} + +static DisasIAQE iaqe_incr(const DisasIAQE *e, int64_t disp) +{ + return (DisasIAQE){ + .space =3D e->space, + .base =3D e->base, + .disp =3D e->disp + disp, + }; +} + +static DisasIAQE iaqe_branchi(DisasContext *ctx, int64_t disp) +{ + return (DisasIAQE){ + .space =3D ctx->iaq_b.space, + .disp =3D ctx->iaq_f.disp + 8 + disp, + }; +} + +static DisasIAQE iaqe_next_absv(DisasContext *ctx, TCGv_i64 var) +{ + return (DisasIAQE){ + .space =3D ctx->iaq_b.space, + .base =3D var, + }; +} + static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, - uint64_t ival, TCGv_i64 vval) + const DisasIAQE *src) { uint64_t mask =3D gva_offset_mask(ctx->tb_flags); =20 - if (ival !=3D -1) { - tcg_gen_movi_i64(dest, ival & mask); - return; - } - tcg_debug_assert(vval !=3D NULL); - - /* - * We know that the IAOQ is already properly masked. - * This optimization is primarily for "iaoq_f =3D iaoq_b". - */ - if (vval =3D=3D cpu_iaoq_f || vval =3D=3D cpu_iaoq_b) { - tcg_gen_mov_i64(dest, vval); + if (src->base =3D=3D NULL) { + tcg_gen_movi_i64(dest, src->disp & mask); + } else if (src->disp =3D=3D 0) { + tcg_gen_andi_i64(dest, src->base, mask); } else { - tcg_gen_andi_i64(dest, vval, mask); + tcg_gen_addi_i64(dest, src->base, src->disp); + tcg_gen_andi_i64(dest, dest, mask); } } =20 -static void install_iaq_entries(DisasContext *ctx, - uint64_t bi, TCGv_i64 bv, TCGv_i64 bs, - uint64_t ni, TCGv_i64 nv, TCGv_i64 ns) +static void install_iaq_entries(DisasContext *ctx, const DisasIAQE *f, + const DisasIAQE *b) { - copy_iaoq_entry(ctx, cpu_iaoq_f, bi, bv); + DisasIAQE b_next; =20 - /* Allow ni variable, with nv null, to indicate a trivial advance. */ - if (ni !=3D -1 || nv) { - copy_iaoq_entry(ctx, cpu_iaoq_b, ni, nv); - } else if (bi !=3D -1) { - copy_iaoq_entry(ctx, cpu_iaoq_b, bi + 4, NULL); - } else { - tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4); - tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, - gva_offset_mask(ctx->tb_flags)); + if (b =3D=3D NULL) { + b_next =3D iaqe_incr(f, 4); + b =3D &b_next; } - if (bs) { - tcg_gen_mov_i64(cpu_iasq_f, bs); + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + copy_iaoq_entry(ctx, cpu_iaoq_b, b); + if (f->space) { + tcg_gen_mov_i64(cpu_iasq_f, f->space); } - if (ns || bs) { - tcg_gen_mov_i64(cpu_iasq_b, ns ? ns : bs); + if (b->space || f->space) { + tcg_gen_mov_i64(cpu_iasq_b, b->space ? : f->space); } } =20 @@ -651,10 +671,11 @@ static void install_link(DisasContext *ctx, unsigned = link, bool with_sr0) { tcg_debug_assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); if (link) { - if (ctx->iaoq_b =3D=3D -1) { - tcg_gen_addi_i64(cpu_gr[link], cpu_iaoq_b, 4); + if (ctx->iaq_b.base) { + tcg_gen_addi_i64(cpu_gr[link], ctx->iaq_b.base, + ctx->iaq_b.disp + 4); } else { - tcg_gen_movi_i64(cpu_gr[link], ctx->iaoq_b + 4); + tcg_gen_movi_i64(cpu_gr[link], ctx->iaq_b.disp + 4); } #ifndef CONFIG_USER_ONLY if (with_sr0) { @@ -664,11 +685,6 @@ static void install_link(DisasContext *ctx, unsigned l= ink, bool with_sr0) } } =20 -static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp) -{ - return ctx->iaoq_f + disp + 8; -} - static void gen_excp_1(int exception) { gen_helper_excp(tcg_env, tcg_constant_i32(exception)); @@ -676,8 +692,7 @@ static void gen_excp_1(int exception) =20 static void gen_excp(DisasContext *ctx, int exception) { - install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, NULL, - ctx->iaoq_b, cpu_iaoq_b, NULL); + install_iaq_entries(ctx, &ctx->iaq_f, &ctx->iaq_b); nullify_save(ctx); gen_excp_1(exception); ctx->base.is_jmp =3D DISAS_NORETURN; @@ -709,10 +724,12 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif =20 -static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) +static bool use_goto_tb(DisasContext *ctx, const DisasIAQE *f, + const DisasIAQE *b) { - return (bofs !=3D -1 && nofs !=3D -1 && - translator_use_goto_tb(&ctx->base, bofs)); + return (!iaqe_variable(f) && + (b =3D=3D NULL || !iaqe_variable(b)) && + translator_use_goto_tb(&ctx->base, f->disp)); } =20 /* If the next insn is to be nullified, and it's on the same page, @@ -722,20 +739,19 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t b= ofs, uint64_t nofs) static bool use_nullify_skip(DisasContext *ctx) { return (!(tb_cflags(ctx->base.tb) & CF_BP_PAGE) - && ctx->iaoq_b !=3D -1 - && is_same_page(&ctx->base, ctx->iaoq_b)); + && !iaqe_variable(&ctx->iaq_b) + && is_same_page(&ctx->base, ctx->iaq_b.disp)); } =20 static void gen_goto_tb(DisasContext *ctx, int which, - uint64_t b, uint64_t n) + const DisasIAQE *f, const DisasIAQE *b) { - if (use_goto_tb(ctx, b, n)) { + if (use_goto_tb(ctx, f, b)) { tcg_gen_goto_tb(which); - install_iaq_entries(ctx, b, NULL, NULL, n, NULL, NULL); + install_iaq_entries(ctx, f, b); tcg_gen_exit_tb(ctx->base.tb, which); } else { - install_iaq_entries(ctx, b, cpu_iaoq_b, ctx->iasq_b, - n, ctx->iaoq_n_var, ctx->iasq_n); + install_iaq_entries(ctx, f, b); tcg_gen_lookup_and_goto_ptr(); } } @@ -1816,37 +1832,35 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned= rt, static bool do_dbranch(DisasContext *ctx, int64_t disp, unsigned link, bool is_n) { - uint64_t dest =3D iaoq_dest(ctx, disp); + ctx->iaq_j =3D iaqe_branchi(ctx, disp); =20 if (ctx->null_cond.c =3D=3D TCG_COND_NEVER && ctx->null_lab =3D=3D NUL= L) { install_link(ctx, link, false); if (is_n) { if (use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 0, dest, dest + 4); + gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); ctx->base.is_jmp =3D DISAS_NORETURN; return true; } ctx->null_cond.c =3D TCG_COND_ALWAYS; } - ctx->iaoq_n =3D dest; - ctx->iaoq_n_var =3D NULL; + ctx->iaq_n =3D &ctx->iaq_j; } else { nullify_over(ctx); =20 install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 0, dest, dest + 4); + gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); } else { nullify_set(ctx, is_n); - gen_goto_tb(ctx, 0, ctx->iaoq_b, dest); + gen_goto_tb(ctx, 0, &ctx->iaq_b, &ctx->iaq_j); } - nullify_end(ctx); =20 nullify_set(ctx, 0); - gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n); + gen_goto_tb(ctx, 1, &ctx->iaq_b, NULL); ctx->base.is_jmp =3D DISAS_NORETURN; } return true; @@ -1857,7 +1871,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t dis= p, static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, DisasCond *cond) { - uint64_t dest =3D iaoq_dest(ctx, disp); + DisasIAQE next; TCGLabel *taken =3D NULL; TCGCond c =3D cond->c; bool n; @@ -1877,26 +1891,29 @@ static bool do_cbranch(DisasContext *ctx, int64_t d= isp, bool is_n, n =3D is_n && disp < 0; if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 0, ctx->iaoq_n, ctx->iaoq_n + 4); + next =3D iaqe_incr(&ctx->iaq_b, 4); + gen_goto_tb(ctx, 0, &next, NULL); } else { if (!n && ctx->null_lab) { gen_set_label(ctx->null_lab); ctx->null_lab =3D NULL; } nullify_set(ctx, n); - gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); + gen_goto_tb(ctx, 0, &ctx->iaq_b, NULL); } =20 gen_set_label(taken); =20 /* Taken: Condition satisfied; nullify on forward branches. */ n =3D is_n && disp >=3D 0; + + next =3D iaqe_branchi(ctx, disp); if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 1, dest, dest + 4); + gen_goto_tb(ctx, 1, &next, NULL); } else { nullify_set(ctx, n); - gen_goto_tb(ctx, 1, ctx->iaoq_b, dest); + gen_goto_tb(ctx, 1, &ctx->iaq_b, &next); } =20 /* Not taken: the branch itself was nullified. */ @@ -1910,45 +1927,36 @@ static bool do_cbranch(DisasContext *ctx, int64_t d= isp, bool is_n, return true; } =20 -/* Emit an unconditional branch to an indirect target. This handles - nullification of the branch itself. */ -static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 dspc, - unsigned link, bool with_sr0, bool is_n) +/* + * Emit an unconditional branch to an indirect target, in ctx->iaq_j. + * This handles nullification of the branch itself. + */ +static bool do_ibranch(DisasContext *ctx, unsigned link, + bool with_sr0, bool is_n) { - TCGv_i64 next; - if (ctx->null_cond.c =3D=3D TCG_COND_NEVER && ctx->null_lab =3D=3D NUL= L) { - next =3D tcg_temp_new_i64(); - tcg_gen_mov_i64(next, dest); - install_link(ctx, link, with_sr0); if (is_n) { if (use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); + install_iaq_entries(ctx, &ctx->iaq_j, NULL); nullify_set(ctx, 0); ctx->base.is_jmp =3D DISAS_IAQ_N_UPDATED; return true; } ctx->null_cond.c =3D TCG_COND_ALWAYS; } - ctx->iaoq_n =3D -1; - ctx->iaoq_n_var =3D next; - ctx->iasq_n =3D dspc; + ctx->iaq_n =3D &ctx->iaq_j; return true; } =20 nullify_over(ctx); =20 - next =3D tcg_temp_new_i64(); - tcg_gen_mov_i64(next, dest); - install_link(ctx, link, with_sr0); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); + install_iaq_entries(ctx, &ctx->iaq_j, NULL); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, next, dspc); + install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); nullify_set(ctx, is_n); } =20 @@ -1995,8 +2003,6 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TC= Gv_i64 offset) aforementioned BE. */ static void do_page_zero(DisasContext *ctx) { - TCGv_i64 tmp; - /* If by some means we get here with PSW[N]=3D1, that implies that the B,GATE instruction would be skipped, and we'd fault on the next insn within the privileged page. */ @@ -2016,11 +2022,11 @@ static void do_page_zero(DisasContext *ctx) non-sequential instruction execution. Normally the PSW[B] bit detects this by disallowing the B,GATE instruction to execute under such conditions. */ - if (ctx->iaoq_b !=3D ctx->iaoq_f + 4) { + if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp !=3D ctx->iaq_f.disp= + 4) { goto do_sigill; } =20 - switch (ctx->iaoq_f & -4) { + switch (ctx->iaq_f.disp & -4) { case 0x00: /* Null pointer call */ gen_excp_1(EXCP_IMP); ctx->base.is_jmp =3D DISAS_NORETURN; @@ -2032,11 +2038,15 @@ static void do_page_zero(DisasContext *ctx) break; =20 case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])= ); - tmp =3D tcg_temp_new_i64(); - tcg_gen_ori_i64(tmp, cpu_gr[31], 3); - install_iaq_entries(ctx, -1, tmp, NULL, -1, NULL, NULL); - ctx->base.is_jmp =3D DISAS_IAQ_N_UPDATED; + { + DisasIAQE next =3D { .base =3D tcg_temp_new_i64() }; + + tcg_gen_st_i64(cpu_gr[26], tcg_env, + offsetof(CPUHPPAState, cr[27])); + tcg_gen_ori_i64(next.base, cpu_gr[31], 3); + install_iaq_entries(ctx, &next, NULL); + ctx->base.is_jmp =3D DISAS_IAQ_N_UPDATED; + } break; =20 case 0x100: /* SYSCALL */ @@ -2075,11 +2085,12 @@ static bool trans_sync(DisasContext *ctx, arg_sync = *a) =20 static bool trans_mfia(DisasContext *ctx, arg_mfia *a) { - unsigned rt =3D a->t; - TCGv_i64 tmp =3D dest_gpr(ctx, rt); - tcg_gen_movi_i64(tmp, ctx->iaoq_f & ~3ULL); - save_gpr(ctx, rt, tmp); + TCGv_i64 dest =3D dest_gpr(ctx, a->t); =20 + copy_iaoq_entry(ctx, dest, &ctx->iaq_f); + tcg_gen_andi_i64(dest, dest, -4); + + save_gpr(ctx, a->t, dest); cond_free(&ctx->null_cond); return true; } @@ -2779,8 +2790,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d = *a) nullify_over(ctx); =20 /* Advance the instruction queue. */ - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - ctx->iaoq_n, ctx->iaoq_n_var, ctx->iasq_n); + install_iaq_entries(ctx, &ctx->iaq_b, NULL); nullify_set(ctx, 0); =20 /* Tell the qemu main loop to halt until this cpu has work. */ @@ -3914,18 +3924,18 @@ static bool trans_depi_sar(DisasContext *ctx, arg_d= epi_sar *a) =20 static bool trans_be(DisasContext *ctx, arg_be *a) { - TCGv_i64 dest =3D tcg_temp_new_i64(); - TCGv_i64 space =3D NULL; - - tcg_gen_addi_i64(dest, load_gpr(ctx, a->b), a->disp); - dest =3D do_ibranch_priv(ctx, dest); - #ifndef CONFIG_USER_ONLY - space =3D tcg_temp_new_i64(); - load_spr(ctx, space, a->sp); + ctx->iaq_j.space =3D tcg_temp_new_i64(); + load_spr(ctx, ctx->iaq_j.space, a->sp); #endif =20 - return do_ibranch(ctx, dest, space, a->l, true, a->n); + ctx->iaq_j.base =3D tcg_temp_new_i64(); + ctx->iaq_j.disp =3D 0; + + tcg_gen_addi_i64(ctx->iaq_j.base, load_gpr(ctx, a->b), a->disp); + ctx->iaq_j.base =3D do_ibranch_priv(ctx, ctx->iaq_j.base); + + return do_ibranch(ctx, a->l, true, a->n); } =20 static bool trans_bl(DisasContext *ctx, arg_bl *a) @@ -3935,7 +3945,7 @@ static bool trans_bl(DisasContext *ctx, arg_bl *a) =20 static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) { - uint64_t dest =3D iaoq_dest(ctx, a->disp); + int64_t disp =3D a->disp; =20 nullify_over(ctx); =20 @@ -3950,7 +3960,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gat= e *a) * b evil * in which instructions at evil would run with increased privs. */ - if (ctx->iaoq_b =3D=3D -1 || ctx->iaoq_b !=3D ctx->iaoq_f + 4) { + if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp !=3D ctx->iaq_f.disp= + 4) { return gen_illegal(ctx); } =20 @@ -3968,10 +3978,11 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_g= ate *a) } /* No change for non-gateway pages or for priv decrease. */ if (type >=3D 4 && type - 4 < ctx->privilege) { - dest =3D deposit64(dest, 0, 2, type - 4); + disp -=3D ctx->privilege; + disp +=3D type - 4; } } else { - dest &=3D -4; /* priv =3D 0 */ + disp -=3D ctx->privilege; /* priv =3D 0 */ } #endif =20 @@ -3984,17 +3995,23 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_g= ate *a) save_gpr(ctx, a->l, tmp); } =20 - return do_dbranch(ctx, dest - iaoq_dest(ctx, 0), 0, a->n); + return do_dbranch(ctx, disp, 0, a->n); } =20 static bool trans_blr(DisasContext *ctx, arg_blr *a) { if (a->x) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); - tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3); - tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8); + DisasIAQE next =3D iaqe_incr(&ctx->iaq_f, 8); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + /* The computation here never changes privilege level. */ - return do_ibranch(ctx, tmp, NULL, a->l, false, a->n); + copy_iaoq_entry(ctx, t0, &next); + tcg_gen_shli_i64(t1, load_gpr(ctx, a->x), 3); + tcg_gen_add_i64(t0, t0, t1); + + ctx->iaq_j =3D iaqe_next_absv(ctx, t0); + return do_ibranch(ctx, a->l, false, a->n); } else { /* BLR R0,RX is a good way to load PC+8 into RX. */ return do_dbranch(ctx, 0, a->l, a->n); @@ -4013,20 +4030,22 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); } dest =3D do_ibranch_priv(ctx, dest); - return do_ibranch(ctx, dest, NULL, 0, false, a->n); + ctx->iaq_j =3D iaqe_next_absv(ctx, dest); + + return do_ibranch(ctx, 0, false, a->n); } =20 static bool trans_bve(DisasContext *ctx, arg_bve *a) { TCGv_i64 b =3D load_gpr(ctx, a->b); - TCGv_i64 dest =3D do_ibranch_priv(ctx, b); - TCGv_i64 space =3D NULL; =20 #ifndef CONFIG_USER_ONLY - space =3D space_select(ctx, 0, b); + ctx->iaq_j.space =3D space_select(ctx, 0, b); #endif + ctx->iaq_j.base =3D do_ibranch_priv(ctx, b); + ctx->iaq_j.disp =3D 0; =20 - return do_ibranch(ctx, dest, space, a->l, false, a->n); + return do_ibranch(ctx, a->l, false, a->n); } =20 static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a) @@ -4598,9 +4617,8 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) #ifdef CONFIG_USER_ONLY ctx->privilege =3D MMU_IDX_TO_PRIV(MMU_USER_IDX); ctx->mmu_idx =3D MMU_USER_IDX; - ctx->iaoq_f =3D ctx->base.pc_first | ctx->privilege; - ctx->iaoq_b =3D ctx->base.tb->cs_base | ctx->privilege; - ctx->iasq_b =3D NULL; + ctx->iaq_f.disp =3D ctx->base.pc_first | ctx->privilege; + ctx->iaq_b.disp =3D ctx->base.tb->cs_base | ctx->privilege; ctx->unalign =3D (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIG= N); #else ctx->privilege =3D (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; @@ -4613,9 +4631,13 @@ static void hppa_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) uint64_t iasq_f =3D cs_base & ~0xffffffffull; int32_t diff =3D cs_base; =20 - ctx->iaoq_f =3D (ctx->base.pc_first & ~iasq_f) + ctx->privilege; - ctx->iaoq_b =3D (diff ? ctx->iaoq_f + diff : -1); - ctx->iasq_b =3D (diff ? NULL : cpu_iasq_b); + ctx->iaq_f.disp =3D (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + if (diff) { + ctx->iaq_b.disp =3D ctx->iaq_f.disp + diff; + } else { + ctx->iaq_b.base =3D cpu_iaoq_b; + ctx->iaq_b.space =3D cpu_iasq_b; + } #endif =20 ctx->zero =3D tcg_constant_i64(0); @@ -4643,7 +4665,10 @@ static void hppa_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b, 0); + tcg_debug_assert(!iaqe_variable(&ctx->iaq_f)); + tcg_gen_insn_start(ctx->iaq_f.disp, + iaqe_variable(&ctx->iaq_b) ? -1 : ctx->iaq_b.disp, + 0); ctx->insn_start_updated =3D false; } =20 @@ -4666,11 +4691,12 @@ static void hppa_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cs) the page permissions for execute. */ uint32_t insn =3D translator_ldl(env, &ctx->base, ctx->base.pc_nex= t); =20 - /* Set up the IA queue for the next insn. - This will be overwritten by a branch. */ - ctx->iasq_n =3D NULL; - ctx->iaoq_n_var =3D NULL; - ctx->iaoq_n =3D ctx->iaoq_b =3D=3D -1 ? -1 : ctx->iaoq_b + 4; + /* + * Set up the IA queue for the next insn. + * This will be overwritten by a branch. + */ + ctx->iaq_n =3D NULL; + memset(&ctx->iaq_j, 0, sizeof(ctx->iaq_j)); =20 if (unlikely(ctx->null_cond.c =3D=3D TCG_COND_ALWAYS)) { ctx->null_cond.c =3D TCG_COND_NEVER; @@ -4691,7 +4717,8 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) return; } /* Note this also detects a priority change. */ - if (ctx->iaoq_b !=3D ctx->iaoq_f + 4 || ctx->iasq_b) { + if (iaqe_variable(&ctx->iaq_b) + || ctx->iaq_b.disp !=3D ctx->iaq_f.disp + 4) { ctx->base.is_jmp =3D DISAS_IAQ_N_STALE; return; } @@ -4700,20 +4727,25 @@ static void hppa_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cs) * Advance the insn queue. * The only exit now is DISAS_TOO_MANY from the translator loop. */ - ctx->iaoq_f =3D ctx->iaoq_b; - ctx->iaoq_b =3D ctx->iaoq_n; - if (ctx->iaoq_b =3D=3D -1) { - if (ctx->iaoq_n_var) { - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); - } else { - tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); - tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, - gva_offset_mask(ctx->tb_flags)); - } + ctx->iaq_f.disp =3D ctx->iaq_b.disp; + if (!ctx->iaq_n) { + ctx->iaq_b.disp +=3D 4; + return; } - if (ctx->iasq_n) { - tcg_gen_mov_i64(cpu_iasq_b, ctx->iasq_n); - ctx->iasq_b =3D cpu_iasq_b; + /* + * If IAQ_Next is variable in any way, we need to copy into the + * IAQ_Back globals, in case the next insn raises an exception. + */ + if (ctx->iaq_n->base) { + copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaq_n); + ctx->iaq_b.base =3D cpu_iaoq_b; + ctx->iaq_b.disp =3D 0; + } else { + ctx->iaq_b.disp =3D ctx->iaq_n->disp; + } + if (ctx->iaq_n->space) { + tcg_gen_mov_i64(cpu_iasq_b, ctx->iaq_n->space); + ctx->iaq_b.space =3D cpu_iasq_b; } } =20 @@ -4721,43 +4753,29 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbas= e, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); DisasJumpType is_jmp =3D ctx->base.is_jmp; - uint64_t fi, bi; - TCGv_i64 fv, bv; - TCGv_i64 fs, bs; - /* Assume the insn queue has not been advanced. */ - fi =3D ctx->iaoq_b; - fv =3D cpu_iaoq_b; - fs =3D ctx->iasq_b; - bi =3D ctx->iaoq_n; - bv =3D ctx->iaoq_n_var; - bs =3D ctx->iasq_n; + DisasIAQE *f =3D &ctx->iaq_b; + DisasIAQE *b =3D ctx->iaq_n; =20 switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: /* The insn queue has not been advanced. */ - bi =3D fi; - bv =3D fv; - bs =3D fs; - fi =3D ctx->iaoq_f; - fv =3D NULL; - fs =3D NULL; + f =3D &ctx->iaq_f; + b =3D &ctx->iaq_b; /* FALLTHRU */ case DISAS_IAQ_N_STALE: - if (fs =3D=3D NULL - && bs =3D=3D NULL - && use_goto_tb(ctx, fi, bi) + if (use_goto_tb(ctx, f, b) && (ctx->null_cond.c =3D=3D TCG_COND_NEVER || ctx->null_cond.c =3D=3D TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c =3D=3D TCG_COND_ALWAYS); - gen_goto_tb(ctx, 0, fi, bi); + gen_goto_tb(ctx, 0, f, b); break; } /* FALLTHRU */ case DISAS_IAQ_N_STALE_EXIT: - install_iaq_entries(ctx, fi, fv, fs, bi, bv, bs); + install_iaq_entries(ctx, f, b); nullify_save(ctx); if (is_jmp =3D=3D DISAS_IAQ_N_STALE_EXIT) { tcg_gen_exit_tb(NULL, 0); @@ -4813,6 +4831,6 @@ static const TranslatorOps hppa_tr_ops =3D { void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_in= sns, vaddr pc, void *host_pc) { - DisasContext ctx; + DisasContext ctx =3D { }; translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.bas= e); } --=20 2.34.1