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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id l1-20020a170902f68100b001e3e244e5c0sm8694439plg.78.2024.04.15.21.06.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Apr 2024 21:06:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1713240377; x=1713845177; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SGHcSo147SgN6rnFLSb3VGek6gUZYoiow/EIARfgQaI=; b=qnvBKeqvUCwKHGbcCgTHflcOR52tZpqyQ3ziHizT+ldJO9Z2Xe72jluHKDGdjStJPX 2lVqogXRpVUiU3Nrl3iVM5AmaS/P7Dl4VKd0GwFBG0xqsDO3Nc/NHy4YPn6GZmYYtPUv ZgUQ8ofPQfp9mFnSzz5huoXWdWzSJUaMVdy5KcKu0PCdpUYDvsL/GggYmkWrQJt9K11y 6Fw7QXaiqWidt6V+HJkx4bg0+rYFk6dm7/rPGNSCwmTJLwH4g1ucFOPezP6NCemyLx19 VtVBQ7iI4TiXU84Z7ng4QblT42b44e0wwkI9DTbjKhuyDbGoa2GFxPhwLyzSWI9+JtY9 v4DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713240377; x=1713845177; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SGHcSo147SgN6rnFLSb3VGek6gUZYoiow/EIARfgQaI=; b=cx9bqepdFcVCV54jYIZnzyIUloNCnf5hbGxXt7F6/AwbxwZKvkwzVUyAfQ/x15usfV tGzFkd0MIYHGmIcuZEFD7JK10a/87HP0INZ7Gziz1dXrG23onB1VxaZWVTlgorx/cJ/W bGyzDBsGJhFfkvexaUmM9P9tWPMY3Kro/g4v8ZOasAinSU1tHefauI5ebThTgLpxQEIi 6d5JEMyHTRZDgaQylw9XDViwqgXEy1i7F8bSoZRuC67CAIjhzEBT5GCnQbU7XK8tp8iW Gcv8WBgNsWXViUzvMSwOzWRbFx0NbI3F/U1sm3XI1BoAN50CRWk04j/XREIwQzVXSwxH V78A== X-Gm-Message-State: AOJu0YzYPeMDB1MdfmF6tAM1g0qbLgsdDBZF8fRY6cp1ZkZU6+t+EyEq cDqJnsGHHP7IxIlBfMqVDwYi0MgDj0I4dsewgpJSUPg/ICYPDRhVPeSw62PpzWjEk9xqzaDNM36 n X-Google-Smtp-Source: AGHT+IFHSl4pIJ3RQk0j5ij5rqS3i2lJqANY3IMNaWQosD3WTiI19+ZfVg5NraQMgWrTXuEhdSsacQ== X-Received: by 2002:a17:903:41c7:b0:1e3:ce12:ef77 with SMTP id u7-20020a17090341c700b001e3ce12ef77mr1256616ple.11.1713240377293; Mon, 15 Apr 2024 21:06:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org Subject: [PATCH 7/7] target/i386: Implement TCGCPUOps for plugin register reads Date: Mon, 15 Apr 2024 21:06:09 -0700 Message-Id: <20240416040609.1313605-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240416040609.1313605-1-richard.henderson@linaro.org> References: <20240416040609.1313605-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1713240434742100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/i386/tcg/tcg-cpu.c | 72 ++++++++++++++++++++++++++++++--------- 1 file changed, 56 insertions(+), 16 deletions(-) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index cca19cd40e..2370053df2 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -22,9 +22,11 @@ #include "helper-tcg.h" #include "qemu/accel.h" #include "hw/core/accel-cpu.h" - +#include "gdbstub/helpers.h" +#include "gdb-internal.h" #include "tcg-cpu.h" =20 + /* Frob eflags into and out of the CPU temporary format. */ =20 static void x86_cpu_exec_enter(CPUState *cs) @@ -61,38 +63,74 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, } } =20 -static void x86_restore_state_to_opc(CPUState *cs, - const TranslationBlock *tb, - const uint64_t *data) +static uint64_t eip_from_unwind(CPUX86State *env, const TranslationBlock *= tb, + uint64_t data0) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - int cc_op =3D data[1]; uint64_t new_pc; =20 if (tb_cflags(tb) & CF_PCREL) { /* - * data[0] in PC-relative TBs is also a linear address, i.e. an ad= dress with - * the CS base added, because it is not guaranteed that EIP bits 1= 2 and higher - * stay the same across the translation block. Add the CS base ba= ck before - * replacing the low bits, and subtract it below just like for !CF= _PCREL. + * data[0] in PC-relative TBs is also a linear address, + * i.e. an address with the CS base added, because it is + * not guaranteed that EIP bits 12 and higher stay the + * same across the translation block. Add the CS base + * back before replacing the low bits, and subtract it + * below just like for !CF_PCREL. */ uint64_t pc =3D env->eip + tb->cs_base; - new_pc =3D (pc & TARGET_PAGE_MASK) | data[0]; + new_pc =3D (pc & TARGET_PAGE_MASK) | data0; } else { - new_pc =3D data[0]; + new_pc =3D data0; } if (tb->flags & HF_CS64_MASK) { - env->eip =3D new_pc; - } else { - env->eip =3D (uint32_t)(new_pc - tb->cs_base); + return new_pc; } + return (uint32_t)(new_pc - tb->cs_base); +} =20 +static void x86_restore_state_to_opc(CPUState *cs, + const TranslationBlock *tb, + const uint64_t *data) +{ + CPUX86State *env =3D cpu_env(cs); + CCOp cc_op; + + env->eip =3D eip_from_unwind(env, tb, data[0]); + + cc_op =3D data[1]; if (cc_op !=3D CC_OP_DYNAMIC) { env->cc_op =3D cc_op; } } =20 +static bool x86_plugin_need_unwind_for_reg(CPUState *cs, int reg) +{ + return reg =3D=3D IDX_IP_REG || reg =3D=3D IDX_FLAGS_REG; +} + +static int x86_plugin_unwind_read_reg(CPUState *cs, GByteArray *buf, int r= eg, + const TranslationBlock *tb, + const uint64_t *data) +{ + CPUX86State *env =3D cpu_env(cs); + CCOp cc_op; + + switch (reg) { + case IDX_IP_REG: + return gdb_get_regl(buf, eip_from_unwind(env, tb, data[0])); + + case IDX_FLAGS_REG: + cc_op =3D data[1]; + if (cc_op =3D=3D CC_OP_DYNAMIC) { + cc_op =3D env->cc_op; + } + return gdb_get_reg32(buf, cpu_compute_eflags_ccop(env, cc_op)); + + default: + g_assert_not_reached(); + } +} + #ifndef CONFIG_USER_ONLY static bool x86_debug_check_breakpoint(CPUState *cs) { @@ -110,6 +148,8 @@ static const TCGCPUOps x86_tcg_ops =3D { .initialize =3D tcg_x86_init, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .restore_state_to_opc =3D x86_restore_state_to_opc, + .plugin_need_unwind_for_reg =3D x86_plugin_need_unwind_for_reg, + .plugin_unwind_read_reg =3D x86_plugin_unwind_read_reg, .cpu_exec_enter =3D x86_cpu_exec_enter, .cpu_exec_exit =3D x86_cpu_exec_exit, #ifdef CONFIG_USER_ONLY --=20 2.34.1