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Tue, 09 Apr 2024 06:38:30 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Chuhong Yuan , Jason Wang , Alexander Bulekov , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-9.1 v2 05/11] hw/net/lan9118: Add definitions for FIFO allocated sizes Date: Tue, 9 Apr 2024 15:37:54 +0200 Message-ID: <20240409133801.23503-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240409133801.23503-1-philmd@linaro.org> References: <20240409133801.23503-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1712669995808100001 Add definitions for the TX_FIF_SZ=3D5 case, per TABLE 5-3 "VALID TX/RX FIFO ALLOCATIONS". Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/lan9118.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index a6a869de32..00409927fe 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -158,6 +158,17 @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while= (0) */ #define MIL_TXFIFO_SIZE 2048 =20 +/* + * TX and RX FIFO space is configurable through the TX FIFO Size (TX_FIF_S= Z) + * field in the hardware configuration (CSR HW_CFG) register. These are the + * default configuration settings for TX_FIF_SZ =3D 5 + * (see TABLE 5-3: VALID TX/RX FIFO ALLOCATIONS). + */ +#define TX_DATA_FIFO_BYTES 4608 /* 1152 words */ +#define TX_STATUS_FIFO_BYTES 512 /* 128 words */ +#define RX_DATA_FIFO_BYTES 10560 /* 2640 words */ +#define RX_STATUS_FIFO_BYTES 704 /* 176 words */ + enum tx_state { TX_IDLE, TX_B, --=20 2.41.0