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[98.147.7.212]) by smtp.gmail.com with ESMTPSA id z26-20020aa785da000000b006e64ddfa71asm7654894pfn.170.2024.04.08.22.03.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Apr 2024 22:03:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712638996; x=1713243796; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Lp1ipweNADN/6K9dE0kz0Ja73YaJ/vSstA3RIvGr8kM=; b=bGVWqD60NjJM/0SL2FCs5WeHp9OQhyuHbwyG+WkNwqlu/g3ydJBOx/IMFMgY7vcRYk NNWmyWTqxm7Bp/C4CQmZ5rkhICt+5ukRoH4vNCcjGK69PbjL5sHhU9swEPyQNvhLnZOE xMruL8Xy84zWJxEqsdpP/4CqsnbpiFm+PVLtXxc4qISXvXOXAsdXT2MaF3YXw5+uobuq PxarYji448fn3sMbHKDGzVEjepVD1lGfZKSDEaIR8U/qTII1L7NLyTmOK/uOBS1NZtCB k6vvBx+TqJBBBxgq8yaubnfk+xp9Naet/aCI9dXsd0eyVeDbWVLRynKVNO4q1ROm9pfu 3etg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712638996; x=1713243796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lp1ipweNADN/6K9dE0kz0Ja73YaJ/vSstA3RIvGr8kM=; b=Y+gLNH1FY64rNZ1VWVj0mtEYwAJIIgRNLPzmtlkEP9V8pfZogZKve+TIHyJOv91tOJ QdXPVMTgsE80jd6gUsTS6yelFkA11/J8aDQBgpkBOGqwSZ8iIZLzxamuWDXWO93nz57k z91JT5rtUGFgAekQlFpJDduV0odnnnYn4xRKfwzswG6aaWMj9KtO4kOMNNUpH9h7+5CJ cvgwx/L/flg2CBBHAoZdVqHhm7G2Vv/PZDHWbbW6dShS+ZRnek+1TdkEPux40ITBQLC8 bpKU/EkSp5tGHLtKN0kJ28sZ97kpHe8UTDZ6cRrk25dmWzW6niHVIE5Z1V6g26RDoBUD 8QAA== X-Gm-Message-State: AOJu0YwDUTFbLO93OSmNjqxg74foIauetUmkJ6+2stfglX21jCpjxybW atTXQnyXVtK/xYixiUUOLXl0heXE3Cs3hzs6OfA/pKaarH9VkP5H8fPSBXhbnKs664MKJgh7Cci e X-Google-Smtp-Source: AGHT+IE1EjXWqERMqHuixMbS+d0ZzVL/NyFNelP5PQYT7yl4XEAk59u+sW8kp2QE9vL20D8VVvYcLw== X-Received: by 2002:a05:6870:15c4:b0:22a:107c:4dd6 with SMTP id k4-20020a05687015c400b0022a107c4dd6mr11849811oad.40.1712638996599; Mon, 08 Apr 2024 22:03:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 09/28] tagret/i386: Convert do_fxsave, do_fxrstor to X86Access Date: Mon, 8 Apr 2024 19:02:43 -1000 Message-Id: <20240409050302.1523277-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240409050302.1523277-1-richard.henderson@linaro.org> References: <20240409050302.1523277-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1712639047180100011 Content-Type: text/plain; charset="utf-8" Move the alignment fault from do_* to helper_*, as it need not apply to usage from within user-only signal handling. Signed-off-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 84 ++++++++++++++++++++---------------- 1 file changed, 48 insertions(+), 36 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 59f73ad075..23e22e4521 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -2618,8 +2618,25 @@ static void do_xsave_pkru(CPUX86State *env, target_u= long ptr, uintptr_t ra) cpu_stq_data_ra(env, ptr, env->pkru, ra); } =20 -static void do_fxsave(CPUX86State *env, target_ulong ptr, uintptr_t ra) +static void do_fxsave(X86Access *ac, target_ulong ptr) { + CPUX86State *env =3D ac->env; + + do_xsave_fpu(ac, ptr); + if (env->cr[4] & CR4_OSFXSR_MASK) { + do_xsave_mxcsr(ac, ptr); + /* Fast FXSAVE leaves out the XMM registers */ + if (!(env->efer & MSR_EFER_FFXSR) + || (env->hflags & HF_CPL_MASK) + || !(env->hflags & HF_LMA_MASK)) { + do_xsave_sse(ac, ptr); + } + } +} + +void helper_fxsave(CPUX86State *env, target_ulong ptr) +{ + uintptr_t ra =3D GETPC(); X86Access ac; =20 /* The operand must be 16 byte aligned */ @@ -2629,22 +2646,7 @@ static void do_fxsave(CPUX86State *env, target_ulong= ptr, uintptr_t ra) =20 access_prepare(&ac, env, ptr, sizeof(X86LegacyXSaveArea), MMU_DATA_STORE, ra); - do_xsave_fpu(&ac, ptr); - - if (env->cr[4] & CR4_OSFXSR_MASK) { - do_xsave_mxcsr(&ac, ptr); - /* Fast FXSAVE leaves out the XMM registers */ - if (!(env->efer & MSR_EFER_FFXSR) - || (env->hflags & HF_CPL_MASK) - || !(env->hflags & HF_LMA_MASK)) { - do_xsave_sse(&ac, ptr); - } - } -} - -void helper_fxsave(CPUX86State *env, target_ulong ptr) -{ - do_fxsave(env, ptr, GETPC()); + do_fxsave(&ac, ptr); } =20 static uint64_t get_xinuse(CPUX86State *env) @@ -2849,8 +2851,25 @@ static void do_xrstor_pkru(CPUX86State *env, target_= ulong ptr, uintptr_t ra) env->pkru =3D cpu_ldq_data_ra(env, ptr, ra); } =20 -static void do_fxrstor(CPUX86State *env, target_ulong ptr, uintptr_t ra) +static void do_fxrstor(X86Access *ac, target_ulong ptr) { + CPUX86State *env =3D ac->env; + + do_xrstor_fpu(ac, ptr); + if (env->cr[4] & CR4_OSFXSR_MASK) { + do_xrstor_mxcsr(ac, ptr); + /* Fast FXRSTOR leaves out the XMM registers */ + if (!(env->efer & MSR_EFER_FFXSR) + || (env->hflags & HF_CPL_MASK) + || !(env->hflags & HF_LMA_MASK)) { + do_xrstor_sse(ac, ptr); + } + } +} + +void helper_fxrstor(CPUX86State *env, target_ulong ptr) +{ + uintptr_t ra =3D GETPC(); X86Access ac; =20 /* The operand must be 16 byte aligned */ @@ -2860,22 +2879,7 @@ static void do_fxrstor(CPUX86State *env, target_ulon= g ptr, uintptr_t ra) =20 access_prepare(&ac, env, ptr, sizeof(X86LegacyXSaveArea), MMU_DATA_LOAD, ra); - do_xrstor_fpu(&ac, ptr); - - if (env->cr[4] & CR4_OSFXSR_MASK) { - do_xrstor_mxcsr(&ac, ptr); - /* Fast FXRSTOR leaves out the XMM registers */ - if (!(env->efer & MSR_EFER_FFXSR) - || (env->hflags & HF_CPL_MASK) - || !(env->hflags & HF_LMA_MASK)) { - do_xrstor_sse(&ac, ptr); - } - } -} - -void helper_fxrstor(CPUX86State *env, target_ulong ptr) -{ - do_fxrstor(env, ptr, GETPC()); + do_fxrstor(&ac, ptr); } =20 static void do_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm, u= intptr_t ra) @@ -3007,12 +3011,20 @@ void cpu_x86_frstor(CPUX86State *env, target_ulong = ptr, int data32) =20 void cpu_x86_fxsave(CPUX86State *env, target_ulong ptr) { - do_fxsave(env, ptr, 0); + X86Access ac; + + access_prepare(&ac, env, ptr, sizeof(X86LegacyXSaveArea), + MMU_DATA_STORE, 0); + do_fxsave(&ac, ptr); } =20 void cpu_x86_fxrstor(CPUX86State *env, target_ulong ptr) { - do_fxrstor(env, ptr, 0); + X86Access ac; + + access_prepare(&ac, env, ptr, sizeof(X86LegacyXSaveArea), + MMU_DATA_LOAD, 0); + do_fxrstor(&ac, ptr); } =20 void cpu_x86_xsave(CPUX86State *env, target_ulong ptr) --=20 2.34.1