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Mon, 08 Apr 2024 07:09:12 -0700 (PDT) Date: Mon, 8 Apr 2024 14:08:10 +0000 In-Reply-To: <20240408140818.3799590-1-smostafa@google.com> Mime-Version: 1.0 References: <20240408140818.3799590-1-smostafa@google.com> X-Mailer: git-send-email 2.44.0.478.gd926399ef9-goog Message-ID: <20240408140818.3799590-6-smostafa@google.com> Subject: [RFC PATCH v2 05/13] hw/arm/smmu-common: Support nested translation From: Mostafa Saleh To: qemu-arm@nongnu.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, alex.bennee@linaro.org, maz@kernel.org, nicolinc@nvidia.com, julien@xen.org, richard.henderson@linaro.org, marcin.juszkiewicz@linaro.org, Mostafa Saleh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1149; envelope-from=3iPoTZggKCgUxrtxyfkflttlqj.htrvjrz-ij0jqstslsz.twl@flex--smostafa.bounces.google.com; helo=mail-yw1-x1149.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1712585436427100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When nested translation is requested, do the following: - Translate stage-1 IPA using stage-2 to a physical address. - Translate stage-1 PTW walks using stage-2. - Combine both to create a single TLB entry, for that we choose the smallest entry to cache, which means that if the smallest entry comes from stage-2, and stage-2 use different granule, TLB lookup for stage-1 (in nested config) will always miss. Lookup logic is modified for nesting to lookup using stage-2 granule if stage-1 granule missed and they are different. Also, add more visibility in trace points, to make it easier to debug. Signed-off-by: Mostafa Saleh --- hw/arm/smmu-common.c | 153 ++++++++++++++++++++++++++++------- hw/arm/trace-events | 6 +- include/hw/arm/smmu-common.h | 3 +- 3 files changed, 131 insertions(+), 31 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 771b9c79a3..2cf27b490b 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -66,8 +66,10 @@ SMMUIOTLBKey smmu_get_iotlb_key(int asid, int vmid, uint= 64_t iova, return key; } =20 -SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, - SMMUTransTableInfo *tt, hwaddr iova) +static SMMUTLBEntry *smmu_iotlb_lookup_all_levels(SMMUState *bs, + SMMUTransCfg *cfg, + SMMUTransTableInfo *tt, + hwaddr iova) { uint8_t tg =3D (tt->granule_sz - 10) / 2; uint8_t inputsize =3D 64 - tt->tsz; @@ -88,10 +90,29 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTran= sCfg *cfg, } level++; } + return entry; +} + +SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, + SMMUTransTableInfo *tt, hwaddr iova) +{ + SMMUTLBEntry *entry =3D NULL; + + entry =3D smmu_iotlb_lookup_all_levels(bs, cfg, tt, iova); + /* + * For nested translation also use the s2 granule, as the TLB will ins= ert + * the smallest of both, so the entry can be cached with the s2 granul= e. + */ + if (!entry && (cfg->stage =3D=3D SMMU_NESTED) && + (cfg->s2cfg.granule_sz !=3D tt->granule_sz)) { + tt->granule_sz =3D cfg->s2cfg.granule_sz; + entry =3D smmu_iotlb_lookup_all_levels(bs, cfg, tt, iova); + } =20 if (entry) { cfg->iotlb_hits++; trace_smmu_iotlb_lookup_hit(cfg->asid, cfg->s2cfg.vmid, iova, + entry->entry.addr_mask, cfg->iotlb_hits, cfg->iotlb_misses, 100 * cfg->iotlb_hits / (cfg->iotlb_hits + cfg->iotlb_misses)); @@ -117,7 +138,7 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg= , SMMUTLBEntry *new) *key =3D smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, new->entry.iov= a, tg, new->level); trace_smmu_iotlb_insert(cfg->asid, cfg->s2cfg.vmid, new->entry.iova, - tg, new->level); + tg, new->level, new->entry.translated_addr); g_hash_table_insert(bs->iotlb, key, new); } =20 @@ -286,6 +307,27 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_a= ddr_t iova) return NULL; } =20 +/* Return the correct table address based on configuration. */ +static inline int translate_table_s1(dma_addr_t *table_addr, SMMUTransCfg = *cfg, + SMMUPTWEventInfo *info, SMMUState *bs) +{ + dma_addr_t addr =3D *table_addr; + SMMUTLBEntry *cached_entry; + + if (cfg->stage !=3D SMMU_NESTED) { + return 0; + } + + CALL_FUNC_CFG_S2(cfg, cached_entry, smmu_translate, + bs, cfg, addr, IOMMU_RO, info); + + if (cached_entry) { + *table_addr =3D CACHED_ENTRY_TO_ADDR(cached_entry, addr); + return 0; + } + return -EINVAL; +} + /** * smmu_ptw_64_s1 - VMSAv8-64 Walk of the page tables for a given IOVA * @cfg: translation config @@ -301,7 +343,8 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) */ static int smmu_ptw_64_s1(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, - SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info, + SMMUState *bs) { dma_addr_t baseaddr, indexmask; SMMUStage stage =3D cfg->stage; @@ -349,6 +392,10 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg, goto error; } baseaddr =3D get_table_pte_address(pte, granule_sz); + /* In case of failure, retain stage-2 fault. */ + if (translate_table_s1(&baseaddr, cfg, info, bs)) { + goto error_no_stage; + } level++; continue; } else if (is_page_pte(pte, level)) { @@ -384,7 +431,7 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg, tlbe->entry.translated_addr =3D gpa; tlbe->entry.iova =3D iova & ~mask; tlbe->entry.addr_mask =3D mask; - tlbe->entry.perm =3D PTE_AP_TO_PERM(ap); + tlbe->parent_perm =3D tlbe->entry.perm =3D PTE_AP_TO_PERM(ap); tlbe->level =3D level; tlbe->granule =3D granule_sz; return 0; @@ -393,6 +440,7 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg, =20 error: info->stage =3D SMMU_STAGE_1; +error_no_stage: tlbe->entry.perm =3D IOMMU_NONE; return -EINVAL; } @@ -505,7 +553,7 @@ static int smmu_ptw_64_s2(SMMUTransCfg *cfg, tlbe->entry.translated_addr =3D gpa; tlbe->entry.iova =3D ipa & ~mask; tlbe->entry.addr_mask =3D mask; - tlbe->entry.perm =3D s2ap; + tlbe->parent_perm =3D tlbe->entry.perm =3D s2ap; tlbe->level =3D level; tlbe->granule =3D granule_sz; return 0; @@ -518,6 +566,28 @@ error: return -EINVAL; } =20 +/* Combine 2 TLB enteries and return in tlbe. */ +static void combine_tlb(SMMUTLBEntry *tlbe, SMMUTLBEntry *tlbe_s2, + dma_addr_t iova, SMMUTransCfg *cfg) +{ + if (cfg->stage =3D=3D SMMU_NESTED) { + tlbe->entry.addr_mask =3D MIN(tlbe->entry.addr_mask, + tlbe_s2->entry.addr_mask); + tlbe->entry.translated_addr =3D CACHED_ENTRY_TO_ADDR(tlbe_s2, + tlbe->entry.translated_addr); + + tlbe->granule =3D MIN(tlbe->granule, tlbe_s2->granule); + tlbe->level =3D MAX(tlbe->level, tlbe_s2->level); + tlbe->entry.iova =3D iova & ~tlbe->entry.addr_mask; + /* parent_perm has s2 perm while perm has s1 perm. */ + tlbe->parent_perm =3D tlbe_s2->entry.perm; + return; + } + + /* That was not nested, use the s2. */ + memcpy(tlbe, tlbe_s2, sizeof(*tlbe)); +} + /** * smmu_ptw - Walk the page tables for an IOVA, according to @cfg * @@ -530,28 +600,59 @@ error: * return 0 on success */ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, - SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info, SMMUState *bs) { - if (cfg->stage =3D=3D SMMU_STAGE_1) { - return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info); - } else if (cfg->stage =3D=3D SMMU_STAGE_2) { - /* - * If bypassing stage 1(or unimplemented), the input address is pa= ssed - * directly to stage 2 as IPA. If the input address of a transacti= on - * exceeds the size of the IAS, a stage 1 Address Size fault occur= s. - * For AA64, IAS =3D OAS according to (IHI 0070.E.a) "3.4 Address = sizes" - */ - if (iova >=3D (1ULL << cfg->oas)) { - info->type =3D SMMU_PTW_ERR_ADDR_SIZE; - info->stage =3D SMMU_STAGE_1; - tlbe->entry.perm =3D IOMMU_NONE; - return -EINVAL; + int ret =3D 0; + SMMUTLBEntry tlbe_s2; + dma_addr_t ipa =3D iova; + + if (cfg->stage & SMMU_STAGE_1) { + ret =3D smmu_ptw_64_s1(cfg, iova, perm, tlbe, info, bs); + if (ret) { + return ret; } + /* This is the IPA for next stage.*/ + ipa =3D CACHED_ENTRY_TO_ADDR(tlbe, iova); + } =20 - return smmu_ptw_64_s2(cfg, iova, perm, tlbe, info); + /* + * The address output from the translation causes a stage 1 Address Si= ze + * fault if it exceeds the range of the effective IPA size for the giv= en CD. + * If bypassing stage 1(or unimplemented), the input address is passed + * directly to stage 2 as IPA. If the input address of a transaction + * exceeds the size of the IAS, a stage 1 Address Size fault occurs. + * For AA64, IAS =3D OAS according to (IHI 0070.E.a) "3.4 Address size= s" + */ + if (ipa >=3D (1ULL << cfg->oas)) { + info->type =3D SMMU_PTW_ERR_ADDR_SIZE; + info->stage =3D SMMU_STAGE_1; + tlbe->entry.perm =3D IOMMU_NONE; + return -EINVAL; } =20 - g_assert_not_reached(); + if (cfg->stage & SMMU_STAGE_2) { + ret =3D smmu_ptw_64_s2(cfg, ipa, perm, &tlbe_s2, info); + if (ret) { + return ret; + } + combine_tlb(tlbe, &tlbe_s2, iova, cfg); + } + + return ret; +} + +static int validate_tlb_entry(SMMUTLBEntry *cached_entry, IOMMUAccessFlags= flag, + SMMUPTWEventInfo *info) +{ + if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & + cached_entry->parent_perm & IOMMU_WO)) { + info->type =3D SMMU_PTW_ERR_PERMISSION; + info->stage =3D !(cached_entry->entry.perm & IOMMU_WO) ? + SMMU_STAGE_1 : + SMMU_STAGE_2; + return -EINVAL; + } + return 0; } =20 SMMUTLBEntry *smmu_translate(SMMUState *bs, SMMUTransCfg *cfg, dma_addr_t = addr, @@ -595,16 +696,14 @@ SMMUTLBEntry *smmu_translate(SMMUState *bs, SMMUTrans= Cfg *cfg, dma_addr_t addr, =20 cached_entry =3D smmu_iotlb_lookup(bs, cfg, &tt_combined, aligned_addr= ); if (cached_entry) { - if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { - info->type =3D SMMU_PTW_ERR_PERMISSION; - info->stage =3D cfg->stage; + if (validate_tlb_entry(cached_entry, flag, info)) { return NULL; } return cached_entry; } =20 cached_entry =3D g_new0(SMMUTLBEntry, 1); - status =3D smmu_ptw(cfg, aligned_addr, flag, cached_entry, info); + status =3D smmu_ptw(cfg, aligned_addr, flag, cached_entry, info, bs); if (status) { g_free(cached_entry); return NULL; diff --git a/hw/arm/trace-events b/hw/arm/trace-events index cc12924a84..5f23f0b963 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -15,9 +15,9 @@ smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid= =3D%d" smmu_iotlb_inv_vmid(uint16_t vmid) "IOTLB invalidate vmid=3D%d" smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid= =3D%d addr=3D0x%"PRIx64 smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" -smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_= t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=3D%d vmid=3D%d addr= =3D0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%d" -smmu_iotlb_lookup_miss(uint16_t asid, uint16_t vmid, uint64_t addr, uint32= _t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=3D%d vmid=3D%d ad= dr=3D0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%d" -smmu_iotlb_insert(uint16_t asid, uint16_t vmid, uint64_t addr, uint8_t tg,= uint8_t level) "IOTLB ++ asid=3D%d vmid=3D%d addr=3D0x%"PRIx64" tg=3D%d le= vel=3D%d" +smmu_iotlb_lookup_hit(int asid, uint16_t vmid, uint64_t addr, uint64_t mas= k, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=3D%d vmid= =3D%d addr=3D0x%"PRIx64" mask=3D0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%= d" +smmu_iotlb_lookup_miss(int asid, uint16_t vmid, uint64_t addr, uint32_t hi= t, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=3D%d vmid=3D%d addr=3D= 0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%d" +smmu_iotlb_insert(int asid, uint16_t vmid, uint64_t addr, uint8_t tg, uint= 8_t level, uint64_t translate_addr) "IOTLB ++ asid=3D%d vmid=3D%d addr=3D0x= %"PRIx64" tg=3D%d level=3D%d translate_addr=3D0x%"PRIx64 =20 # smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "= addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 2772175115..03ff0f02ba 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -91,6 +91,7 @@ typedef struct SMMUTLBEntry { IOMMUTLBEntry entry; uint8_t level; uint8_t granule; + IOMMUAccessFlags parent_perm; } SMMUTLBEntry; =20 /* Stage-2 configuration. */ @@ -198,7 +199,7 @@ static inline uint16_t smmu_get_sid(SMMUDevice *sdev) * pair, according to @cfg translation config */ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, - SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info, SMMUState *bs); =20 =20 /* --=20 2.44.0.478.gd926399ef9-goog