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Mon, 08 Apr 2024 07:09:02 -0700 (PDT) Date: Mon, 8 Apr 2024 14:08:06 +0000 In-Reply-To: <20240408140818.3799590-1-smostafa@google.com> Mime-Version: 1.0 References: <20240408140818.3799590-1-smostafa@google.com> X-Mailer: git-send-email 2.44.0.478.gd926399ef9-goog Message-ID: <20240408140818.3799590-2-smostafa@google.com> Subject: [RFC PATCH v2 01/13] hw/arm/smmu: Use enum for SMMU stage From: Mostafa Saleh To: qemu-arm@nongnu.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, alex.bennee@linaro.org, maz@kernel.org, nicolinc@nvidia.com, julien@xen.org, richard.henderson@linaro.org, marcin.juszkiewicz@linaro.org, Mostafa Saleh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::114a; envelope-from=3fvoTZggKCvktnptubgbhpphmf.dpnrfnv-efwfmopohov.psh@flex--smostafa.bounces.google.com; helo=mail-yw1-x114a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1712585438437100006 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, translation stage is represented as an int, where 1 is stage-1 a= nd 2 is stage-2, when nested is added, 3 would be confusing to represent nesti= ng, so we use an enum instead. While keeping the same values, this is useful for: - Doing tricks with bit masks, where BIT(0) is stage-1 and BIT(1) is stage-2 and both is nested. - Tracing, as stage is printed as int. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger --- hw/arm/smmu-common.c | 14 +++++++------- hw/arm/smmuv3.c | 15 ++++++++------- include/hw/arm/smmu-common.h | 11 +++++++++-- 3 files changed, 24 insertions(+), 16 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 4caedb4998..3a7c350aca 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -304,7 +304,7 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg, SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { dma_addr_t baseaddr, indexmask; - int stage =3D cfg->stage; + SMMUStage stage =3D cfg->stage; SMMUTransTableInfo *tt =3D select_tt(cfg, iova); uint8_t level, granule_sz, inputsize, stride; =20 @@ -392,7 +392,7 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg, info->type =3D SMMU_PTW_ERR_TRANSLATION; =20 error: - info->stage =3D 1; + info->stage =3D SMMU_STAGE_1; tlbe->entry.perm =3D IOMMU_NONE; return -EINVAL; } @@ -415,7 +415,7 @@ static int smmu_ptw_64_s2(SMMUTransCfg *cfg, dma_addr_t ipa, IOMMUAccessFlags perm, SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { - const int stage =3D 2; + const SMMUStage stage =3D SMMU_STAGE_2; int granule_sz =3D cfg->s2cfg.granule_sz; /* ARM DDI0487I.a: Table D8-7. */ int inputsize =3D 64 - cfg->s2cfg.tsz; @@ -513,7 +513,7 @@ static int smmu_ptw_64_s2(SMMUTransCfg *cfg, info->type =3D SMMU_PTW_ERR_TRANSLATION; =20 error: - info->stage =3D 2; + info->stage =3D SMMU_STAGE_2; tlbe->entry.perm =3D IOMMU_NONE; return -EINVAL; } @@ -532,9 +532,9 @@ error: int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { - if (cfg->stage =3D=3D 1) { + if (cfg->stage =3D=3D SMMU_STAGE_1) { return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info); - } else if (cfg->stage =3D=3D 2) { + } else if (cfg->stage =3D=3D SMMU_STAGE_2) { /* * If bypassing stage 1(or unimplemented), the input address is pa= ssed * directly to stage 2 as IPA. If the input address of a transacti= on @@ -543,7 +543,7 @@ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUA= ccessFlags perm, */ if (iova >=3D (1ULL << cfg->oas)) { info->type =3D SMMU_PTW_ERR_ADDR_SIZE; - info->stage =3D 1; + info->stage =3D SMMU_STAGE_1; tlbe->entry.perm =3D IOMMU_NONE; return -EINVAL; } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 9eb56a70f3..50e5a72d54 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -34,7 +34,8 @@ #include "smmuv3-internal.h" #include "smmu-internal.h" =20 -#define PTW_RECORD_FAULT(cfg) (((cfg)->stage =3D=3D 1) ? (cfg)->record_f= aults : \ +#define PTW_RECORD_FAULT(cfg) (((cfg)->stage =3D=3D SMMU_STAGE_1) ? \ + (cfg)->record_faults : \ (cfg)->s2cfg.record_faults) =20 /** @@ -402,7 +403,7 @@ static bool s2_pgtable_config_valid(uint8_t sl0, uint8_= t t0sz, uint8_t gran) =20 static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste) { - cfg->stage =3D 2; + cfg->stage =3D SMMU_STAGE_2; =20 if (STE_S2AA64(ste) =3D=3D 0x0) { qemu_log_mask(LOG_UNIMP, @@ -678,7 +679,7 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEve= ntInfo *event) =20 /* we support only those at the moment */ cfg->aa64 =3D true; - cfg->stage =3D 1; + cfg->stage =3D SMMU_STAGE_1; =20 cfg->oas =3D oas2bits(CD_IPS(cd)); cfg->oas =3D MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas); @@ -762,7 +763,7 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, = SMMUTransCfg *cfg, return ret; } =20 - if (cfg->aborted || cfg->bypassed || (cfg->stage =3D=3D 2)) { + if (cfg->aborted || cfg->bypassed || (cfg->stage =3D=3D SMMU_STAGE_2))= { return 0; } =20 @@ -882,7 +883,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, goto epilogue; } =20 - if (cfg->stage =3D=3D 1) { + if (cfg->stage =3D=3D SMMU_STAGE_1) { /* Select stage1 translation table. */ tt =3D select_tt(cfg, addr); if (!tt) { @@ -919,7 +920,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, * nesting is not supported. So it is sufficient to check the * translation stage to know the TLB stage for now. */ - event.u.f_walk_eabt.s2 =3D (cfg->stage =3D=3D 2); + event.u.f_walk_eabt.s2 =3D (cfg->stage =3D=3D SMMU_STAGE_2); if (PTW_RECORD_FAULT(cfg)) { event.type =3D SMMU_EVT_F_PERMISSION; event.u.f_permission.addr =3D addr; @@ -935,7 +936,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, =20 if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { /* All faults from PTW has S2 field. */ - event.u.f_walk_eabt.s2 =3D (ptw_info.stage =3D=3D 2); + event.u.f_walk_eabt.s2 =3D (ptw_info.stage =3D=3D SMMU_STAGE_2); g_free(cached_entry); switch (ptw_info.type) { case SMMU_PTW_ERR_WALK_EABT: diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 5ec2e6c1a4..b3c881f0ee 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -49,8 +49,15 @@ typedef enum { SMMU_PTW_ERR_PERMISSION, /* Permission fault */ } SMMUPTWEventType; =20 +/* SMMU Stage */ +typedef enum { + SMMU_STAGE_1 =3D 1, + SMMU_STAGE_2, + SMMU_NESTED, +} SMMUStage; + typedef struct SMMUPTWEventInfo { - int stage; + SMMUStage stage; SMMUPTWEventType type; dma_addr_t addr; /* fetched address that induced an abort, if any */ } SMMUPTWEventInfo; @@ -88,7 +95,7 @@ typedef struct SMMUS2Cfg { */ typedef struct SMMUTransCfg { /* Shared fields between stage-1 and stage-2. */ - int stage; /* translation stage */ + SMMUStage stage; /* translation stage */ bool disabled; /* smmu is disabled */ bool bypassed; /* translation is bypassed */ bool aborted; /* translation is aborted */ --=20 2.44.0.478.gd926399ef9-goog