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Mon, 08 Apr 2024 04:46:26 -0400 Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2024 01:46:21 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.124]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2024 01:46:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712565984; x=1744101984; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B7nXRh7ZojaXtdhNyRfMhv/+nlUrwKMI6CTd3vTaKw0=; b=YWb7ANvXvqymp8/4lDO7onYW+uCjFs0veURBjU7kIB8sI038RxcRXTVp G+lBJQ5HfN2GAT/ELdJOtLXQAoDWJH+DAXBAKnGZJ6KsWBXERVHbILTeo fJgBR7Oqlhou/+R8UWsNpBhNl51rf2N58F2Iru6pMz4mjws5NdVXi1Rwd 9gQy1DTsXO0vFb7QIzLgxQeT297rnbv519RJqo1YUprLHmMUEx1IoCGEO mhA4TZMSx2DTWKusoVaJH6Cx2Mzkq6nABxy8jl5qFkPDojsZmqbg7VGWz vEKEhPjZJYX1pcRVjAAt8To+lHgCnlVlfJgmoQC3ojNJ05auzBcy4ieqn Q==; X-CSE-ConnectionGUID: 00PzoLMrSdeUkShyqwjYmQ== X-CSE-MsgGUID: CHrQeTi9TImYc7gi6AdxLg== X-IronPort-AV: E=McAfee;i="6600,9927,11037"; a="19269429" X-IronPort-AV: E=Sophos;i="6.07,186,1708416000"; d="scan'208";a="19269429" X-CSE-ConnectionGUID: IZEFe70/QNapo2muGtHk4A== X-CSE-MsgGUID: B0pyljUtRXG8NHLWOhcjRw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,186,1708416000"; d="scan'208";a="42985871" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, peterx@redhat.com, jasowang@redhat.com, mst@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v2 1/5] intel_iommu: Extract out vtd_cap_init() to initialize cap/ecap Date: Mon, 8 Apr 2024 16:44:00 +0800 Message-Id: <20240408084404.1111628-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240408084404.1111628-1-zhenzhong.duan@intel.com> References: <20240408084404.1111628-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.12; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.355, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1712566013055100001 Content-Type: text/plain; charset="utf-8" Extract cap/ecap initialization in vtd_cap_init() to make code cleaner. No functional change intended. Reviewed-by: Eric Auger Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 93 ++++++++++++++++++++++++------------------- 1 file changed, 51 insertions(+), 42 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index cc8e59674e..519063c8f8 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3934,30 +3934,10 @@ static void vtd_iommu_replay(IOMMUMemoryRegion *iom= mu_mr, IOMMUNotifier *n) return; } =20 -/* Do the initialization. It will also be called when reset, so pay - * attention when adding new initialization stuff. - */ -static void vtd_init(IntelIOMMUState *s) +static void vtd_cap_init(IntelIOMMUState *s) { X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); =20 - memset(s->csr, 0, DMAR_REG_SIZE); - memset(s->wmask, 0, DMAR_REG_SIZE); - memset(s->w1cmask, 0, DMAR_REG_SIZE); - memset(s->womask, 0, DMAR_REG_SIZE); - - s->root =3D 0; - s->root_scalable =3D false; - s->dmar_enabled =3D false; - s->intr_enabled =3D false; - s->iq_head =3D 0; - s->iq_tail =3D 0; - s->iq =3D 0; - s->iq_size =3D 0; - s->qi_enabled =3D false; - s->iq_last_desc_type =3D VTD_INV_DESC_NONE; - s->iq_dw =3D false; - s->next_frcd_reg =3D 0; s->cap =3D VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS | VTD_CAP_MGAW(s->aw_bits); @@ -3974,27 +3954,6 @@ static void vtd_init(IntelIOMMUState *s) } s->ecap =3D VTD_ECAP_QI | VTD_ECAP_IRO; =20 - /* - * Rsvd field masks for spte - */ - vtd_spte_rsvd[0] =3D ~0ULL; - vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, - x86_iommu->dt_supported); - vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); - vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); - vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); - - vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, - x86_iommu->dt_sup= ported); - vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, - x86_iommu->dt_sup= ported); - - if (s->scalable_mode || s->snoop_control) { - vtd_spte_rsvd[1] &=3D ~VTD_SPTE_SNP; - vtd_spte_rsvd_large[2] &=3D ~VTD_SPTE_SNP; - vtd_spte_rsvd_large[3] &=3D ~VTD_SPTE_SNP; - } - if (x86_iommu_ir_supported(x86_iommu)) { s->ecap |=3D VTD_ECAP_IR | VTD_ECAP_MHMV; if (s->intr_eim =3D=3D ON_OFF_AUTO_ON) { @@ -4027,6 +3986,56 @@ static void vtd_init(IntelIOMMUState *s) if (s->pasid) { s->ecap |=3D VTD_ECAP_PASID; } +} + +/* + * Do the initialization. It will also be called when reset, so pay + * attention when adding new initialization stuff. + */ +static void vtd_init(IntelIOMMUState *s) +{ + X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); + + memset(s->csr, 0, DMAR_REG_SIZE); + memset(s->wmask, 0, DMAR_REG_SIZE); + memset(s->w1cmask, 0, DMAR_REG_SIZE); + memset(s->womask, 0, DMAR_REG_SIZE); + + s->root =3D 0; + s->root_scalable =3D false; + s->dmar_enabled =3D false; + s->intr_enabled =3D false; + s->iq_head =3D 0; + s->iq_tail =3D 0; + s->iq =3D 0; + s->iq_size =3D 0; + s->qi_enabled =3D false; + s->iq_last_desc_type =3D VTD_INV_DESC_NONE; + s->iq_dw =3D false; + s->next_frcd_reg =3D 0; + + vtd_cap_init(s); + + /* + * Rsvd field masks for spte + */ + vtd_spte_rsvd[0] =3D ~0ULL; + vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, + x86_iommu->dt_supported); + vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); + + vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, + x86_iommu->dt_supporte= d); + vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, + x86_iommu->dt_supporte= d); + + if (s->scalable_mode || s->snoop_control) { + vtd_spte_rsvd[1] &=3D ~VTD_SPTE_SNP; + vtd_spte_rsvd_large[2] &=3D ~VTD_SPTE_SNP; + vtd_spte_rsvd_large[3] &=3D ~VTD_SPTE_SNP; + } =20 vtd_reset_caches(s); =20 --=20 2.34.1 From nobody Fri May 17 07:56:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1712566029; cv=none; d=zohomail.com; s=zohoarc; b=a7bGrQjD8AXmdoke6OdNgOA0SnBsdIiLFO7pH0RFOnqGYZfdMCrDl9wn23/i1ukywiS8vfcvUQ4EdlE5LgOvrg8C8IcO9OpRcofyCEwzNdriGDcbwDCLHvXEkh9IyIr8VfUQe4QT3PczRX7SwpCn0CPqj5LP6mJqkkdNdZ4uZq0= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.12; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.355, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1712566031193100003 Content-Type: text/plain; charset="utf-8" From: Yi Liu Implement set/unset_iommu_device() callback in Intel vIOMMU. In set call, a new structure VTDHostIOMMUDevice which holds a reference to HostIOMMUDevice is stored in hash table indexed by PCI BDF. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 8 ++++ include/hw/i386/intel_iommu.h | 2 + hw/i386/intel_iommu.c | 76 ++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index f8cf99bddf..becafd03c1 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -537,4 +537,12 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SL_IGN_COM 0xbff0000000000000ULL #define VTD_SL_TM (1ULL << 62) =20 + +typedef struct VTDHostIOMMUDevice { + IntelIOMMUState *iommu_state; + PCIBus *bus; + uint8_t devfn; + HostIOMMUDevice *dev; + QLIST_ENTRY(VTDHostIOMMUDevice) next; +} VTDHostIOMMUDevice; #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 7fa0a695c8..bbc7b96add 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -292,6 +292,8 @@ struct IntelIOMMUState { /* list of registered notifiers */ QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; =20 + GHashTable *vtd_host_iommu_dev; /* VTDHostIOMMUDevice */ + /* interrupt remapping */ bool intr_enabled; /* Whether guest enabled IR */ dma_addr_t intr_root; /* Interrupt remapping table pointer */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 519063c8f8..4f84e2e801 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -237,6 +237,13 @@ static gboolean vtd_as_equal(gconstpointer v1, gconstp= ointer v2) (key1->pasid =3D=3D key2->pasid); } =20 +static gboolean vtd_as_idev_equal(gconstpointer v1, gconstpointer v2) +{ + const struct vtd_as_key *key1 =3D v1; + const struct vtd_as_key *key2 =3D v2; + + return (key1->bus =3D=3D key2->bus) && (key1->devfn =3D=3D key2->devfn= ); +} /* * Note that we use pointer to PCIBus as the key, so hashing/shifting * based on the pointer value is intended. Note that we deal with @@ -3812,6 +3819,70 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,= PCIBus *bus, return vtd_dev_as; } =20 +static int vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, + HostIOMMUDevice *hiod, Error **errp) +{ + IntelIOMMUState *s =3D opaque; + VTDHostIOMMUDevice *vtd_hdev; + struct vtd_as_key key =3D { + .bus =3D bus, + .devfn =3D devfn, + }; + struct vtd_as_key *new_key; + + assert(hiod); + + vtd_iommu_lock(s); + + vtd_hdev =3D g_hash_table_lookup(s->vtd_host_iommu_dev, &key); + + if (vtd_hdev) { + error_setg(errp, "IOMMUFD device already exist"); + vtd_iommu_unlock(s); + return -EEXIST; + } + + vtd_hdev =3D g_malloc0(sizeof(VTDHostIOMMUDevice)); + vtd_hdev->bus =3D bus; + vtd_hdev->devfn =3D (uint8_t)devfn; + vtd_hdev->iommu_state =3D s; + vtd_hdev->dev =3D hiod; + + new_key =3D g_malloc(sizeof(*new_key)); + new_key->bus =3D bus; + new_key->devfn =3D devfn; + + object_ref(hiod); + g_hash_table_insert(s->vtd_host_iommu_dev, new_key, vtd_hdev); + + vtd_iommu_unlock(s); + + return 0; +} + +static void vtd_dev_unset_iommu_device(PCIBus *bus, void *opaque, int devf= n) +{ + IntelIOMMUState *s =3D opaque; + VTDHostIOMMUDevice *vtd_hdev; + struct vtd_as_key key =3D { + .bus =3D bus, + .devfn =3D devfn, + }; + + vtd_iommu_lock(s); + + vtd_hdev =3D g_hash_table_lookup(s->vtd_host_iommu_dev, &key); + if (!vtd_hdev) { + vtd_iommu_unlock(s); + return; + } + + g_hash_table_remove(s->vtd_host_iommu_dev, &key); + object_unref(vtd_hdev->dev); + + vtd_iommu_unlock(s); +} + /* Unmap the whole range in the notifier's scope. */ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n) { @@ -4116,6 +4187,8 @@ static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, = void *opaque, int devfn) =20 static PCIIOMMUOps vtd_iommu_ops =3D { .get_address_space =3D vtd_host_dma_iommu, + .set_iommu_device =3D vtd_dev_set_iommu_device, + .unset_iommu_device =3D vtd_dev_unset_iommu_device, }; =20 static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) @@ -4235,6 +4308,9 @@ static void vtd_realize(DeviceState *dev, Error **err= p) g_free, g_free); s->vtd_address_spaces =3D g_hash_table_new_full(vtd_as_hash, vtd_as_eq= ual, g_free, g_free); + s->vtd_host_iommu_dev =3D g_hash_table_new_full(vtd_as_hash, + vtd_as_idev_equal, + g_free, g_free); vtd_init(s); pci_setup_iommu(bus, &vtd_iommu_ops, dev); /* Pseudo address space under root PCI bus. */ --=20 2.34.1 From nobody Fri May 17 07:56:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1712566021; cv=none; d=zohomail.com; s=zohoarc; b=gBuMwlcSfhwlwygPcCwmjWBCUBtW9hm24fOJ9B+jKGtxDsQtN6XdQkrVcYZmx+vP+mNJAKejMrFkwIUv0qz59KQjYHlKx5fzL1kBh8QfXkkHC5Vxy87RNr8yXLmIi1KZS9cAkN5KcMvZxew2CJ4BI0QY2kT6N5Gr21ZhjVDiQMw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.12; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.355, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1712566023104100001 Content-Type: text/plain; charset="utf-8" From: Yi Liu If check fails, the host side device(either vfio or vdpa device) should not be passed to guest. Implementation details for different backends will be in following patches. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 4f84e2e801..a49b587c73 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -35,6 +35,7 @@ #include "sysemu/kvm.h" #include "sysemu/dma.h" #include "sysemu/sysemu.h" +#include "sysemu/iommufd.h" #include "hw/i386/apic_internal.h" #include "kvm/kvm_i386.h" #include "migration/vmstate.h" @@ -3819,6 +3820,32 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,= PCIBus *bus, return vtd_dev_as; } =20 +static int vtd_check_legacy_hdev(IntelIOMMUState *s, + HostIOMMUDevice *hiod, + Error **errp) +{ + return 0; +} + +static int vtd_check_iommufd_hdev(IntelIOMMUState *s, + HostIOMMUDevice *hiod, + Error **errp) +{ + return 0; +} + +static int vtd_check_hdev(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hdev, + Error **errp) +{ + HostIOMMUDevice *hiod =3D vtd_hdev->dev; + + if (object_dynamic_cast(OBJECT(hiod), TYPE_HIOD_IOMMUFD)) { + return vtd_check_iommufd_hdev(s, hiod, errp); + } + + return vtd_check_legacy_hdev(s, hiod, errp); +} + static int vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, HostIOMMUDevice *hiod, Error **errp) { @@ -3829,6 +3856,7 @@ static int vtd_dev_set_iommu_device(PCIBus *bus, void= *opaque, int devfn, .devfn =3D devfn, }; struct vtd_as_key *new_key; + int ret; =20 assert(hiod); =20 @@ -3848,6 +3876,13 @@ static int vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, vtd_hdev->iommu_state =3D s; vtd_hdev->dev =3D hiod; =20 + ret =3D vtd_check_hdev(s, vtd_hdev, errp); + if (ret) { + g_free(vtd_hdev); + vtd_iommu_unlock(s); + return ret; + } + new_key =3D g_malloc(sizeof(*new_key)); new_key->bus =3D bus; new_key->devfn =3D devfn; --=20 2.34.1 From nobody Fri May 17 07:56:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="42985899" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, peterx@redhat.com, jasowang@redhat.com, mst@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v2 4/5] intel_iommu: Check for compatibility with legacy device Date: Mon, 8 Apr 2024 16:44:03 +0800 Message-Id: <20240408084404.1111628-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240408084404.1111628-1-zhenzhong.duan@intel.com> References: <20240408084404.1111628-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.12; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.355, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1712566087568100001 Content-Type: text/plain; charset="utf-8" Currently only stage-2 translation is supported which is backed by shadow page table on host side. So we don't need exact matching of each bit of cap/ecap between vIOMMU and host. However, we can still ensure compatibility of host and vIOMMU's address width at least, i.e., vIOMMU's aw-bits <=3D host IOMMU aw-bits, which is missed before. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a49b587c73..d2cd186df0 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3824,6 +3824,21 @@ static int vtd_check_legacy_hdev(IntelIOMMUState *s, HostIOMMUDevice *hiod, Error **errp) { + HostIOMMUDeviceClass *hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); + HIOD_LEGACY_INFO info; + int ret; + + ret =3D hiodc->get_host_iommu_info(hiod, &info, sizeof(info), errp); + if (ret) { + return ret; + } + + if (s->aw_bits > info.aw_bits) { + error_setg(errp, "aw-bits %d > host aw-bits %d", + s->aw_bits, info.aw_bits); + return -EINVAL; + } + return 0; } =20 --=20 2.34.1 From nobody Fri May 17 07:56:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="42985904" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, peterx@redhat.com, jasowang@redhat.com, mst@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v2 5/5] intel_iommu: Check for compatibility with iommufd backed device Date: Mon, 8 Apr 2024 16:44:04 +0800 Message-Id: <20240408084404.1111628-6-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240408084404.1111628-1-zhenzhong.duan@intel.com> References: <20240408084404.1111628-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.12; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.355, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1712566041219100003 Content-Type: text/plain; charset="utf-8" Currently only stage-2 translation is supported which is backed by shadow page table on host side. So we don't need exact matching of each bit of cap/ecap between vIOMMU and host. However, we can still ensure compatibility of host and vIOMMU's address width at least, i.e., vIOMMU's aw-bits <=3D host IOMMU aw-bits, which is missed before. When stage-1 translation is supported in future, a.k.a. scalable modern mode, this mechanism will be further extended to check more bits. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index bbc7b96add..2bbde41e45 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -47,6 +47,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_D= EVICE) #define VTD_HOST_AW_48BIT 48 #define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1) +#define VTD_MGAW_FROM_CAP(cap) ((cap >> 16) & 0x3fULL) =20 #define DMAR_REPORT_F_INTR (1) =20 diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index d2cd186df0..d8fac9ef9f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3846,6 +3846,29 @@ static int vtd_check_iommufd_hdev(IntelIOMMUState *s, HostIOMMUDevice *hiod, Error **errp) { + HostIOMMUDeviceClass *hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); + struct iommu_hw_info_vtd *vtd; + HIOD_IOMMUFD_INFO info; + int host_aw_bits, ret; + + ret =3D hiodc->get_host_iommu_info(hiod, &info, sizeof(info), errp); + if (ret) { + return ret; + } + + if (info.type !=3D IOMMU_HW_INFO_TYPE_INTEL_VTD) { + error_setg(errp, "IOMMU hardware is not compatible"); + return -EINVAL; + } + + vtd =3D &info.data.vtd; + host_aw_bits =3D VTD_MGAW_FROM_CAP(vtd->cap_reg) + 1; + if (s->aw_bits > host_aw_bits) { + error_setg(errp, "aw-bits %d > host aw-bits %d", + s->aw_bits, host_aw_bits); + return -EINVAL; + } + return 0; } =20 --=20 2.34.1