From nobody Thu Nov 14 17:50:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1712478072; cv=none; d=zohomail.com; s=zohoarc; b=fSThqEZgUt8Fu5stL3QbXmt0nRiJVxegaxzl8g++fIl0WTqG8v46PO9o7voXnERzDnE/8S52ZiRUwPBMB28a82HxO95z+KmfNSUMGHjx5GDpwb2nvKrGUkiB108b1e3Rjxf0ZXCwJles4wr5lldcCtqWEMI1+6kzdjNgRLKXl0g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1712478072; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=dX5iwsrpR8mW09UzXkfQ77cS4j8jWsZBF9AY6ZX9Yho=; b=YcmZpF/r4c+BrZLSILQp8pIjmA0JQjVdY5gqwbOOoC3hTZKmTB0vHUNDux/iZyzO7GePVYLQydDnRxlXSUEoyJU0RwPWV7R/O9h8yiUUwjzfU3pGQ7X2XwzuVZNFSlgwoMvHapBe3F/JcbPJ1/2Ic4qT+V1AVPpS/KONhX9aBKM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1712478072603591.2094556755724; Sun, 7 Apr 2024 01:21:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rtNkx-0004GD-8t; Sun, 07 Apr 2024 04:20:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rtNkq-0004Bb-TX; Sun, 07 Apr 2024 04:19:56 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rtNkl-0001zZ-4d; Sun, 07 Apr 2024 04:19:55 -0400 Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4VC4nt3hFWztRtY; Sun, 7 Apr 2024 16:17:06 +0800 (CST) Received: from kwepemi500008.china.huawei.com (unknown [7.221.188.139]) by mail.maildlp.com (Postfix) with ESMTPS id E388114010C; Sun, 7 Apr 2024 16:19:45 +0800 (CST) Received: from huawei.com (10.67.174.55) by kwepemi500008.china.huawei.com (7.221.188.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Sun, 7 Apr 2024 16:19:45 +0800 To: , , , , , , , CC: Subject: [PATCH v13 01/24] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI Date: Sun, 7 Apr 2024 08:17:10 +0000 Message-ID: <20240407081733.3231820-2-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240407081733.3231820-1-ruanjinjie@huawei.com> References: <20240407081733.3231820-1-ruanjinjie@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.174.55] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemi500008.china.huawei.com (7.221.188.139) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.187; envelope-from=ruanjinjie@huawei.com; helo=szxga01-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jinjie Ruan From: Jinjie Ruan via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1712478073914100001 Content-Type: text/plain; charset="utf-8" FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and HCRX_VFNMI. When the feature is enabled, allow these bits to be written in HCRX_EL2. Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell --- v13: - Add Reviewed-by. v12: - Remove the redundant blank line. v9: - Declare cpu variable to reuse latter. v4: - Update the comment for FEAT_NMI in hcrx_write(). - Update the commit message, s/thress/three/g. v3: - Add Reviewed-by. - Add HCRX_VINMI and HCRX_VFNMI support in HCRX_EL2. - Upate the commit messsage. --- target/arm/cpu-features.h | 5 +++++ target/arm/helper.c | 8 +++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e5758d9fbc..b300d0446d 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -681,6 +681,11 @@ static inline bool isar_feature_aa64_sme(const ARMISAR= egisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) !=3D 0; } =20 +static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, NMI) !=3D 0; +} + static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f3a5b55d4..408922c94d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6183,13 +6183,19 @@ bool el_is_in_host(CPUARMState *env, int el) static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu =3D env_archcpu(env); uint64_t valid_mask =3D 0; =20 /* FEAT_MOPS adds MSCEn and MCE2 */ - if (cpu_isar_feature(aa64_mops, env_archcpu(env))) { + if (cpu_isar_feature(aa64_mops, cpu)) { valid_mask |=3D HCRX_MSCEN | HCRX_MCE2; } =20 + /* FEAT_NMI adds TALLINT, VINMI and VFNMI */ + if (cpu_isar_feature(aa64_nmi, cpu)) { + valid_mask |=3D HCRX_TALLINT | HCRX_VINMI | HCRX_VFNMI; + } + /* Clear RES0 bits. */ env->cp15.hcrx_el2 =3D value & valid_mask; } --=20 2.34.1