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Tue, 02 Apr 2024 06:16:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGv9rfS994LOeFSg9rWMBVOh/d4CewI5kVkEQRRqiaNbuyjgTWsRss50ukeMi/VFu+3mLoecw== X-Received: by 2002:a5d:6c63:0:b0:343:3e5b:e8af with SMTP id r3-20020a5d6c63000000b003433e5be8afmr8299679wrz.52.1712063814639; Tue, 02 Apr 2024 06:16:54 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 1/7] vga: merge conditionals on shift control register Date: Tue, 2 Apr 2024 15:16:43 +0200 Message-ID: <20240402131649.23225-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240402131649.23225-1-pbonzini@redhat.com> References: <20240402131649.23225-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1712063870704100003 There are two sets of conditionals using the shift control bits: one to verify the palette and adjust disp_width, one to compute the "v" and "bits" variables. Merge them into one, with the extra benefit that we now have the "bits" value available early and can use it to compute region_end. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Paolo Bonzini --- hw/display/vga.c | 89 +++++++++++++++++++++++------------------------- 1 file changed, 42 insertions(+), 47 deletions(-) diff --git a/hw/display/vga.c b/hw/display/vga.c index bc5b83421bf..4795a0012e2 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -1546,12 +1546,54 @@ static void vga_draw_graphic(VGACommonState *s, int= full_update) } =20 if (shift_control =3D=3D 0) { + full_update |=3D update_palette16(s); if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) { disp_width <<=3D 1; + v =3D VGA_DRAW_LINE4D2; + } else { + v =3D VGA_DRAW_LINE4; } + bits =3D 4; + } else if (shift_control =3D=3D 1) { + full_update |=3D update_palette16(s); if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) { disp_width <<=3D 1; + v =3D VGA_DRAW_LINE2D2; + } else { + v =3D VGA_DRAW_LINE2; + } + bits =3D 4; + + } else { + switch (depth) { + default: + case 0: + full_update |=3D update_palette256(s); + v =3D VGA_DRAW_LINE8D2; + bits =3D 4; + break; + case 8: + full_update |=3D update_palette256(s); + v =3D VGA_DRAW_LINE8; + bits =3D 8; + break; + case 15: + v =3D s->big_endian_fb ? VGA_DRAW_LINE15_BE : VGA_DRAW_LINE15_= LE; + bits =3D 16; + break; + case 16: + v =3D s->big_endian_fb ? VGA_DRAW_LINE16_BE : VGA_DRAW_LINE16_= LE; + bits =3D 16; + break; + case 24: + v =3D s->big_endian_fb ? VGA_DRAW_LINE24_BE : VGA_DRAW_LINE24_= LE; + bits =3D 24; + break; + case 32: + v =3D s->big_endian_fb ? VGA_DRAW_LINE32_BE : VGA_DRAW_LINE32_= LE; + bits =3D 32; + break; } } =20 @@ -1607,53 +1649,6 @@ static void vga_draw_graphic(VGACommonState *s, int = full_update) } } =20 - if (shift_control =3D=3D 0) { - full_update |=3D update_palette16(s); - if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) { - v =3D VGA_DRAW_LINE4D2; - } else { - v =3D VGA_DRAW_LINE4; - } - bits =3D 4; - } else if (shift_control =3D=3D 1) { - full_update |=3D update_palette16(s); - if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) { - v =3D VGA_DRAW_LINE2D2; - } else { - v =3D VGA_DRAW_LINE2; - } - bits =3D 4; - } else { - switch(s->get_bpp(s)) { - default: - case 0: - full_update |=3D update_palette256(s); - v =3D VGA_DRAW_LINE8D2; - bits =3D 4; - break; - case 8: - full_update |=3D update_palette256(s); - v =3D VGA_DRAW_LINE8; - bits =3D 8; - break; - case 15: - v =3D s->big_endian_fb ? VGA_DRAW_LINE15_BE : VGA_DRAW_LINE15_= LE; - bits =3D 16; - break; - case 16: - v =3D s->big_endian_fb ? VGA_DRAW_LINE16_BE : VGA_DRAW_LINE16_= LE; - bits =3D 16; - break; - case 24: - v =3D s->big_endian_fb ? VGA_DRAW_LINE24_BE : VGA_DRAW_LINE24_= LE; - bits =3D 24; - break; - case 32: - v =3D s->big_endian_fb ? VGA_DRAW_LINE32_BE : VGA_DRAW_LINE32_= LE; - bits =3D 32; - break; - } - } vga_draw_line =3D vga_draw_line_table[v]; =20 if (!is_buffer_shared(surface) && s->cursor_invalidate) { --=20 2.44.0