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Tsirkin" , Paolo Bonzini , Igor Mammedov , Anthony Perard , Ani Sinha , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH-for-9.1 17/29] hw/i386/pc: Inline gigabyte_align() Date: Thu, 28 Mar 2024 16:54:25 +0100 Message-ID: <20240328155439.58719-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240328155439.58719-1-philmd@linaro.org> References: <20240328155439.58719-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1711641454507100010 All PCI-based machines have the gigabyte_align field set to %true. Simplify by using an inlined helper checking whether the machine is PCI-based or not. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/i386/pc.h | 9 --------- hw/i386/pc.c | 1 - hw/i386/pc_piix.c | 16 +++++++++++++--- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 2db2aa03d3..758dd5f29b 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -76,14 +76,6 @@ typedef struct PcPciMachineState { =20 /** * PCMachineClass: - * - * Compat fields: - * - * @gigabyte_align: Make sure that guest addresses aligned at - * 1Gbyte boundaries get mapped to host - * addresses aligned at 1Gbyte boundaries. This - * way we can use 1GByte pages in the host. - * */ typedef struct PCMachineClass { X86MachineClass parent_class; @@ -99,7 +91,6 @@ typedef struct PCMachineClass { SmbiosEntryPointType default_smbios_ep_type; =20 /* RAM / address space compat: */ - bool gigabyte_align; bool has_reserved_memory; bool broken_reserved_end; bool enforce_amd_1tb_hole; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index dd44df0470..093a7c35f7 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1752,7 +1752,6 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(oc); =20 pcmc->smbios_defaults =3D true; - pcmc->gigabyte_align =3D true; pcmc->has_reserved_memory =3D true; pcmc->enforce_amd_1tb_hole =3D true; pcmc->pvh_enabled =3D true; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 2043a7022a..0bc14da768 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -99,6 +99,17 @@ static void piix_intx_routing_notifier_xen(PCIDevice *de= v) } } =20 +/* + * gigabyte_align: Make sure that guest addresses aligned at + * 1Gbyte boundaries get mapped to host + * addresses aligned at 1Gbyte boundaries. + * This way we can use 1GByte pages in the host. + */ +static bool gigabyte_align(PCMachineState *pcms) +{ + return pc_machine_is_pci_enabled(pcms); +} + /* PC hardware initialisation */ static void pc_init1(MachineState *machine, const char *pci_type) { @@ -130,7 +141,7 @@ static void pc_init1(MachineState *machine, const char = *pci_type) * - Then, to gigabyte align the memory, we move the split to 3G * (lowmem =3D 0xc0000000). But only in case we have to split in * the first place, i.e. ram_size is larger than (traditional) - * lowmem. And for new machine types (gigabyte_align =3D true) + * lowmem. And for new machine types (gigabyte_align() =3D true) * only, for live migration compatibility reasons. * * - Next the max-ram-below-4g option was added, which allowed to @@ -160,7 +171,7 @@ static void pc_init1(MachineState *machine, const char = *pci_type) } lowmem =3D pcms->max_ram_below_4g; if (machine->ram_size >=3D pcms->max_ram_below_4g) { - if (pcmc->gigabyte_align) { + if (gigabyte_align(pcms)) { if (lowmem > 0xc0000000) { lowmem =3D 0xc0000000; } @@ -818,7 +829,6 @@ static void isapc_machine_options(MachineClass *m) m->option_rom_has_mr =3D true; m->rom_file_has_mr =3D false; pcmc->smbios_defaults =3D false; - pcmc->gigabyte_align =3D false; pcmc->smbios_legacy_mode =3D true; pcmc->has_reserved_memory =3D false; m->default_nic =3D "ne2k_isa"; --=20 2.41.0