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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id c3-20020a633503000000b005dc36761ad1sm6958819pga.33.2024.03.25.23.44.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Mar 2024 23:44:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711435450; x=1712040250; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qo1Cy+/ahqbmFMcF+S3a41PcnAQ9BeXKsl8/poFdtaM=; b=RNKGLGdlQEodIC32jpMJB288rvs9p0mLvHRyXI0KRkGXJh50KNyPcLsB+AAkF9JcGk kWOZgurvw2jO3+2FQHWQbFigWFeFc8zfYvZ+KVwrx416stnW3ArSz6bVPhZSqTkCqogK Pgy4bNIpRQvq6pSWl8adDPUcbQExXDLmb+5X672TQFyQefv5nkk/dpFVrzFosmuzMpuL I6afwyMmRFq79T/zMjUA45tx2EIM73PoGATJw3+4zZqy3M8MzTTk3XVwB5bTae99sN4K 2sK3njpanPs2svTqqoUOYgTXR7xR67ZDmD0QMjDsjGwJkFpGgrkVAoQ6eSvfBXHJ4aHY rdBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711435450; x=1712040250; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qo1Cy+/ahqbmFMcF+S3a41PcnAQ9BeXKsl8/poFdtaM=; b=j9NoE4m5uCvdTd2/zDGDj73LuJUqlXeEje6LZk02TNl32I4ObxtqXHXB6t2V7UROLW 1N9GRRF0dpfv+EpKtCJ8+WKRjSYxzKB7RqzUsK7KGyh7f+3yLRjiwrCqo65gKtZzoG7x G3wqXorsTQdbvSEgiugnEgXm0H1tYcKqo55wtxAx6U27zq+vtDq0c5U246BtxV8jWbg4 JXzcZ8smwC8XRbEc12GzyIKEOV0UCMD4XEse4iY0uTXTZAqOGCnIumW9Kp2Cl3i3zQOr c+KmXwrIGKBa5co/HKxVD4H2EdBraoFj3+2bkhBu4ffoeQfPP1aQ0nFpBeyLDtt+VtvJ z5SA== X-Gm-Message-State: AOJu0YxCpUco9oDNf8i2iYILT/9pmae+nPIuxuDx+LIKONwzEb1+oHDr p5SKTCuOFrLkjpeXUO0ixvJh733Olis87tAxGKQ+9AUj19fLb7gKzvOyXO+BXc2U9n4Q5r6Re7W V X-Google-Smtp-Source: AGHT+IGh0T2LtPGDepvq19nFEldPttRLRorimoHHluX1/4+azuz9IWw4r+aFvKYb8TXbVJT93TiGZw== X-Received: by 2002:a05:6870:7986:b0:220:65ba:ca3a with SMTP id he6-20020a056870798600b0022065baca3amr2449996oab.14.1711435449777; Mon, 25 Mar 2024 23:44:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 1/3] target/hppa: Squash d for pa1.x during decode Date: Mon, 25 Mar 2024 20:44:03 -1000 Message-Id: <20240326064405.320551-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326064405.320551-1-richard.henderson@linaro.org> References: <20240326064405.320551-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1711435496237100001 Content-Type: text/plain; charset="utf-8" The cond_need_ext predicate was created while we still had a 32-bit compilation mode. It now makes more sense to treat D as an absolute indicator of a 64-bit operation. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller Tested-by: Helge Deller --- target/hppa/insns.decode | 20 +++++++++++++------- target/hppa/translate.c | 38 ++++++++++++++++++++------------------ 2 files changed, 33 insertions(+), 25 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index f58455dfdb..6a74cf23cd 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -57,6 +57,9 @@ %neg_to_m 0:1 !function=3Dneg_to_m %a_to_m 2:1 !function=3Dneg_to_m %cmpbid_c 13:2 !function=3Dcmpbid_c +%d_5 5:1 !function=3Dpa20_d +%d_11 11:1 !function=3Dpa20_d +%d_13 13:1 !function=3Dpa20_d =20 #### # Argument set definitions @@ -84,15 +87,16 @@ # Format definitions #### =20 -@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d +@rr_cf_d ...... r:5 ..... cf:4 ...... . t:5 &rr_cf_d d=3D%d_5 @rrr ...... r2:5 r1:5 .... ....... t:5 &rrr @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf -@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d +@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d d=3D%d_5 @rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh -@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh -@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=3D0 +@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_d_sh d=3D%= d_5 +@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d_sh d=3D%= d_5 sh=3D0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=3D%lowsi= gn_11 -@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=3D%low= sign_11 +@rri_cf_d ...... r:5 t:5 cf:4 . ........... \ + &rri_cf_d d=3D%d_11 i=3D%lowsign_11 =20 @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ &rrb_c_f disp=3D%assemble_12 @@ -368,8 +372,10 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 .....= @mpyadd # Conditional Branches #### =20 -bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=3D%assem= ble_12 -bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=3D%assem= ble_12 +bb_sar 110000 00000 r:5 c:1 1 . ........... n:1 . \ + disp=3D%assemble_12 d=3D%d_13 +bb_imm 110001 p:5 r:5 c:1 1 . ........... n:1 . \ + disp=3D%assemble_12 d=3D%d_13 =20 movb 110010 ..... ..... ... ........... . . @rrb_cf f=3D0 movbi 110011 ..... ..... ... ........... . . @rib_cf f=3D0 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 99c5c4cbca..a70d644c0b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -200,6 +200,14 @@ static int cmpbid_c(DisasContext *ctx, int val) return val ? val : 4; /* 0 =3D=3D "*<<" */ } =20 +/* + * In many places pa1.x did not decode the bit that later became + * the pa2.0 D bit. Suppress D unless the cpu is pa2.0. + */ +static int pa20_d(DisasContext *ctx, int val) +{ + return ctx->is_pa20 & val; +} =20 /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" @@ -693,12 +701,6 @@ static bool cond_need_cb(int c) return c =3D=3D 4 || c =3D=3D 5; } =20 -/* Need extensions from TCGv_i32 to TCGv_i64. */ -static bool cond_need_ext(DisasContext *ctx, bool d) -{ - return !(ctx->is_pa20 && d); -} - /* * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of * the Parisc 1.1 Architecture Reference Manual for details. @@ -715,7 +717,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf= , bool d, cond =3D cond_make_f(); break; case 1: /* =3D / <> (Z / !Z) */ - if (cond_need_ext(ctx, d)) { + if (!d) { tmp =3D tcg_temp_new_i64(); tcg_gen_ext32u_i64(tmp, res); res =3D tmp; @@ -725,7 +727,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf= , bool d, case 2: /* < / >=3D (N ^ V / !(N ^ V) */ tmp =3D tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, res, sv); - if (cond_need_ext(ctx, d)) { + if (!d) { tcg_gen_ext32s_i64(tmp, tmp); } cond =3D cond_make_0_tmp(TCG_COND_LT, tmp); @@ -742,7 +744,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf= , bool d, */ tmp =3D tcg_temp_new_i64(); tcg_gen_eqv_i64(tmp, res, sv); - if (cond_need_ext(ctx, d)) { + if (!d) { tcg_gen_sextract_i64(tmp, tmp, 31, 1); tcg_gen_and_i64(tmp, tmp, res); tcg_gen_ext32u_i64(tmp, tmp); @@ -760,13 +762,13 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, tmp =3D tcg_temp_new_i64(); tcg_gen_neg_i64(tmp, cb_msb); tcg_gen_and_i64(tmp, tmp, res); - if (cond_need_ext(ctx, d)) { + if (!d) { tcg_gen_ext32u_i64(tmp, tmp); } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); break; case 6: /* SV / NSV (V / !V) */ - if (cond_need_ext(ctx, d)) { + if (!d) { tmp =3D tcg_temp_new_i64(); tcg_gen_ext32s_i64(tmp, sv); sv =3D tmp; @@ -827,7 +829,7 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigne= d cf, bool d, if (cf & 1) { tc =3D tcg_invert_cond(tc); } - if (cond_need_ext(ctx, d)) { + if (!d) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 @@ -904,7 +906,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigne= d cf, bool d, g_assert_not_reached(); } =20 - if (cond_need_ext(ctx, d)) { + if (!d) { TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 if (ext_uns) { @@ -979,7 +981,7 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d,= TCGv_i64 res) static TCGv_i64 get_carry(DisasContext *ctx, bool d, TCGv_i64 cb, TCGv_i64 cb_msb) { - if (cond_need_ext(ctx, d)) { + if (!d) { TCGv_i64 t =3D tcg_temp_new_i64(); tcg_gen_extract_i64(t, cb, 32, 1); return t; @@ -3448,12 +3450,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_= sar *a) =20 tmp =3D tcg_temp_new_i64(); tcg_r =3D load_gpr(ctx, a->r); - if (cond_need_ext(ctx, a->d)) { + if (a->d) { + tcg_gen_shl_i64(tmp, tcg_r, cpu_sar); + } else { /* Force shift into [32,63] */ tcg_gen_ori_i64(tmp, cpu_sar, 32); tcg_gen_shl_i64(tmp, tcg_r, tmp); - } else { - tcg_gen_shl_i64(tmp, tcg_r, cpu_sar); } =20 cond =3D cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); @@ -3470,7 +3472,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_im= m *a) =20 tmp =3D tcg_temp_new_i64(); tcg_r =3D load_gpr(ctx, a->r); - p =3D a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); + p =3D a->p | (a->d ? 0 : 32); tcg_gen_shli_i64(tmp, tcg_r, p); =20 cond =3D cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); --=20 2.34.1