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Mon, 25 Mar 2024 10:47:39 -0400 Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-297-U76x7RzGPXSkPRtX21nQRg-1; Mon, 25 Mar 2024 10:47:31 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C5ACD2800E84; Mon, 25 Mar 2024 14:47:30 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.158]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 672CA2166B31; Mon, 25 Mar 2024 14:47:30 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 653DA1801CDB; Mon, 25 Mar 2024 15:47:25 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1711378055; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VazSRcTbku3LywnN/7Q7TrP0Ppb/9wCf++7ePYqCWwE=; b=G6M8BWnJ5GxuEkvqw/Fn/cmlzqbPJ1nkN20X+4qM0UYhdULRd6REDU/7/BhYNzWIb0U8w0 e003P8QptZKZaL8Yeyzkmm4WPDeduFkkEMBI/RwkNfyLdulAx0pK5J3e2NMtKNGh9sivnA aHid+Y3sZd19A2gqdAeo9ammn4qgOzA= X-MC-Unique: U76x7RzGPXSkPRtX21nQRg-1 From: Gerd Hoffmann To: qemu-devel@nongnu.org Cc: Tom Lendacky , Marcelo Tosatti , kvm@vger.kernel.org, Paolo Bonzini , Gerd Hoffmann Subject: [PATCH v5 1/2] kvm: add support for guest physical bits Date: Mon, 25 Mar 2024 15:47:23 +0100 Message-ID: <20240325144725.1089192-2-kraxel@redhat.com> In-Reply-To: <20240325144725.1089192-1-kraxel@redhat.com> References: <20240325144725.1089192-1-kraxel@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.6 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=kraxel@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.065, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1711378100798100005 Content-Type: text/plain; charset="utf-8" Query kvm for supported guest physical address bits, in cpuid function 80000008, eax[23:16]. Usually this is identical to host physical address bits. With NPT or EPT being used this might be restricted to 48 (max 4-level paging address space size) even if the host cpu supports more physical address bits. When set pass this to the guest, using cpuid too. Guest firmware can use this to figure how big the usable guest physical address space is, so PCI bar mapping are actually reachable. Signed-off-by: Gerd Hoffmann --- target/i386/cpu.h | 1 + target/i386/cpu.c | 1 + target/i386/kvm/kvm-cpu.c | 31 ++++++++++++++++++++++++++++++- 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6b0573807918..83e473584517 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2026,6 +2026,7 @@ struct ArchCPU { =20 /* Number of physical address bits supported */ uint32_t phys_bits; + uint32_t guest_phys_bits; =20 /* in order to simplify APIC support, we leave this pointer to the user */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 33760a2ee163..3b7bd506baf1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6570,6 +6570,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { /* 64 bit processor */ *eax |=3D (cpu_x86_virtual_addr_width(env) << 8); + *eax |=3D (cpu->guest_phys_bits << 16); } *ebx =3D env->features[FEAT_8000_0008_EBX]; if (cs->nr_cores * cs->nr_threads > 1) { diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 9c791b7b0520..c5c24f6a8282 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -18,10 +18,33 @@ #include "kvm_i386.h" #include "hw/core/accel-cpu.h" =20 +static void kvm_set_guest_phys_bits(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + uint32_t eax, guest_phys_bits; + + eax =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0x80000008, 0, R_E= AX); + guest_phys_bits =3D (eax >> 16) & 0xff; + if (!guest_phys_bits) { + return; + } + + if (cpu->guest_phys_bits =3D=3D 0 || + cpu->guest_phys_bits > guest_phys_bits) { + cpu->guest_phys_bits =3D guest_phys_bits; + } + + if (cpu->host_phys_bits && cpu->host_phys_bits_limit && + cpu->guest_phys_bits > cpu->host_phys_bits_limit) { + cpu->guest_phys_bits =3D cpu->host_phys_bits_limit; + } +} + static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; + bool ret; =20 /* * The realize order is important, since x86_cpu_realize() checks if @@ -50,7 +73,13 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) MSR_IA32_UCODE_REV); } } - return host_cpu_realizefn(cs, errp); + ret =3D host_cpu_realizefn(cs, errp); + if (!ret) { + return ret; + } + + kvm_set_guest_phys_bits(cs); + return true; } =20 static bool lmce_supported(void) --=20 2.44.0 From nobody Sun May 12 15:13:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1711378083; cv=none; d=zohomail.com; s=zohoarc; b=ZEXQ5/MS5c47oRPBPMfd0ryOp8pSj2BmmD0KaBG0L8wesFA8y4tcZz6EYBf6bZC24h5j1IvAgbtP+7WlzCPBKQWpswaLGlwTaf+1Di4j9g7bbjrOYxh5UyAHD8valosZkw/Bzm1CzGtigixY3GVGQGloL3ReuTktNpYPCX+wXmA= ARC-Message-Signature: i=1; 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Mon, 25 Mar 2024 14:47:36 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.158]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 05EA51121306; Mon, 25 Mar 2024 14:47:36 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 9AB551801CDC; Mon, 25 Mar 2024 15:47:25 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1711378061; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DsJzNPnYlAzllKzELoC8ajG8VB6UCIrLwt5d6+Usjys=; b=aowVExhdDK+ZiC9f5DWsyGuy/gPNPdH2sc3bf2AIgo5/2uc8OV7FpkAU2P9aFEUhUAbSw7 Xfq6JTkM3AHZ/qK1ijQySJ0eLx+rFuQkMZhNi2u2m91jIzBYK8qA9Mks1TKROBR0BsacGd FbvgxwW2WHAsLZDpHyqHUhgN8CtZEuo= X-MC-Unique: XMZUEqHON_e8BDus4gvrKg-1 From: Gerd Hoffmann To: qemu-devel@nongnu.org Cc: Tom Lendacky , Marcelo Tosatti , kvm@vger.kernel.org, Paolo Bonzini , Gerd Hoffmann Subject: [PATCH v5 2/2] target/i386: add guest-phys-bits cpu property Date: Mon, 25 Mar 2024 15:47:24 +0100 Message-ID: <20240325144725.1089192-3-kraxel@redhat.com> In-Reply-To: <20240325144725.1089192-1-kraxel@redhat.com> References: <20240325144725.1089192-1-kraxel@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=kraxel@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.065, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1711378084771100005 Content-Type: text/plain; charset="utf-8" Allows to set guest-phys-bits (cpuid leaf 80000008, eax[23:16]) via -cpu $model,guest-phys-bits=3D$nr. Signed-off-by: Gerd Hoffmann --- target/i386/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3b7bd506baf1..79bea83b7b1c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7380,6 +7380,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) if (cpu->phys_bits =3D=3D 0) { cpu->phys_bits =3D TCG_PHYS_ADDR_BITS; } + if (cpu->guest_phys_bits && + (cpu->guest_phys_bits > cpu->phys_bits || + cpu->guest_phys_bits < 32)) { + error_setg(errp, "guest-phys-bits should be between 32 and %u " + " (but is %u)", + cpu->phys_bits, cpu->guest_phys_bits); + return; + } } else { /* For 32 bit systems don't use the user set value, but keep * phys_bits consistent with what we tell the guest. @@ -7388,6 +7396,10 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) error_setg(errp, "phys-bits is not user-configurable in 32 bit= "); return; } + if (cpu->guest_phys_bits !=3D 0) { + error_setg(errp, "guest-phys-bits is not user-configurable in = 32 bit"); + return; + } =20 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { cpu->phys_bits =3D 36; @@ -7888,6 +7900,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), + DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, 0), DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit= , 0), DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), --=20 2.44.0