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Mon, 25 Mar 2024 16:49:16 +0800 (CST) Received: from kwepemi500008.china.huawei.com (unknown [7.221.188.139]) by mail.maildlp.com (Postfix) with ESMTPS id BA9831A016F; Mon, 25 Mar 2024 16:51:53 +0800 (CST) Received: from huawei.com (10.67.174.55) by kwepemi500008.china.huawei.com (7.221.188.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Mon, 25 Mar 2024 16:51:53 +0800 To: , , , , , , , CC: Subject: [PATCH v10 05/23] target/arm: Support MSR access to ALLINT Date: Mon, 25 Mar 2024 08:48:36 +0000 Message-ID: <20240325084854.3010562-6-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240325084854.3010562-1-ruanjinjie@huawei.com> References: <20240325084854.3010562-1-ruanjinjie@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.174.55] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemi500008.china.huawei.com (7.221.188.139) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=ruanjinjie@huawei.com; helo=szxga04-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jinjie Ruan From: Jinjie Ruan via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1711356838472100001 Content-Type: text/plain; charset="utf-8" Support ALLINT msr access as follow: mrs , ALLINT // read allint msr ALLINT, // write allint with imm Signed-off-by: Jinjie Ruan Reviewed-by: Richard Henderson --- v9: - Move nmi_reginfo and related functions inside an existing ifdef TARGET_AARCH64 to solve the --target-list=3Daarch64-softmmu,arm-softmmu compilation problem. - Check 'isread' when writing to ALLINT. v5: - Add Reviewed-by. v4: - Remove arm_is_el2_enabled() check in allint_check(). - Change to env->pstate instead of env->allint. v3: - Remove EL0 check in aa64_allint_access() which alreay checks in .access PL1_RW. - Use arm_hcrx_el2_eff() in aa64_allint_access() instead of env->cp15.hcrx_= el2. - Make ALLINT msr access function controlled by aa64_nmi. --- target/arm/helper.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d6c6e9878..a65729af66 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7497,6 +7497,37 @@ static const ARMCPRegInfo rme_mte_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NOP }, }; + +static void aa64_allint_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_ALLINT) | (value & PSTATE_ALLIN= T); +} + +static uint64_t aa64_allint_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_ALLINT; +} + +static CPAccessResult aa64_allint_access(CPUARMState *env, + const ARMCPRegInfo *ri, bool isre= ad) +{ + if (!isread && arm_current_el(env) =3D=3D 1 && + (arm_hcrx_el2_eff(env) & HCRX_TALLINT)) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo nmi_reginfo[] =3D { + { .name =3D "ALLINT", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 0, .crn =3D 4, .crm =3D 3, + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, .accessfn =3D aa64_allint_access, + .fieldoffset =3D offsetof(CPUARMState, pstate), + .writefn =3D aa64_allint_write, .readfn =3D aa64_allint_read, + .resetfn =3D arm_cp_reset_ignore }, +}; #endif /* TARGET_AARCH64 */ =20 static void define_pmu_regs(ARMCPU *cpu) @@ -9891,6 +9922,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_nv2, cpu)) { define_arm_cp_regs(cpu, nv2_reginfo); } + + if (cpu_isar_feature(aa64_nmi, cpu)) { + define_arm_cp_regs(cpu, nmi_reginfo); + } #endif =20 if (cpu_isar_feature(any_predinv, cpu)) { --=20 2.34.1