From nobody Tue Feb 10 14:44:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1711356904; cv=none; d=zohomail.com; s=zohoarc; b=aQr9KrkIE0CbV8ok5RCHE1ddcN6ob60EnX87zmbgxnVsnhFk2HM7FRx3p0dvi5nL4przKiVyovjcLrq9SsJqWeK/xOBWE50Bny3lNf8GBIuWtKGYZehIXw/P46s9VrqjyQ2pYAbw81GIh/tHWDmunOndIx07ML/tCCg/hbtfnz8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711356904; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=URye7WXe5stYLBKMDeBSiUd34ShQseJwDglCJV6y23E=; b=aZ9qNOpLzkESRxGkYQ7WvLhh10Vav0ueVYhIac5lWZ7qBTavLaAllNPXEV8bB2k1xGTVxeGRDi1Xu75dGWA3kjXG6KvbC1xZn93WMdz5q4WL0BXzB4exwRmAJjakvt+mRibpF4Dj84KU+zlZTV5s97ih3TU4566PpfVlY+X4WmE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711356904578780.5240639198679; Mon, 25 Mar 2024 01:55:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rog4Z-0003SL-8i; Mon, 25 Mar 2024 04:52:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rog3x-00031M-4P; Mon, 25 Mar 2024 04:52:15 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rog3q-0007Q4-2m; Mon, 25 Mar 2024 04:52:11 -0400 Received: from mail.maildlp.com (unknown [172.19.88.194]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4V367R2PX4ztQgD; Mon, 25 Mar 2024 16:49:39 +0800 (CST) Received: from kwepemi500008.china.huawei.com (unknown [7.221.188.139]) by mail.maildlp.com (Postfix) with ESMTPS id DE01A1402C7; Mon, 25 Mar 2024 16:52:01 +0800 (CST) Received: from huawei.com (10.67.174.55) by kwepemi500008.china.huawei.com (7.221.188.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Mon, 25 Mar 2024 16:52:01 +0800 To: , , , , , , , CC: Subject: [PATCH v10 14/23] hw/intc/arm_gicv3: Add irq non-maskable property Date: Mon, 25 Mar 2024 08:48:45 +0000 Message-ID: <20240325084854.3010562-15-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240325084854.3010562-1-ruanjinjie@huawei.com> References: <20240325084854.3010562-1-ruanjinjie@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.174.55] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemi500008.china.huawei.com (7.221.188.139) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.187; envelope-from=ruanjinjie@huawei.com; helo=szxga01-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jinjie Ruan From: Jinjie Ruan via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1711356906556100003 Content-Type: text/plain; charset="utf-8" A SPI, PPI or SGI interrupt can have non-maskable property. So maintain non-maskable property in PendingIrq and GICR/GICD. Since add new device state, it also needs to be migrated, so also save NMI info in vmstate_gicv3_cpu and vmstate_gicv3. Signed-off-by: Jinjie Ruan Acked-by: Richard Henderson --- v10: - superprio -> nmi, gicr_isuperprio -> gicr_inmir0. - Save NMI state in vmstate_gicv3_cpu and vmstate_gicv3. - Update the commit message. v3: - Place this ahead of implement GICR_INMIR. - Add Acked-by. --- hw/intc/arm_gicv3_common.c | 44 ++++++++++++++++++++++++++++++ include/hw/intc/arm_gicv3_common.h | 4 +++ 2 files changed, 48 insertions(+) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 2d2cea6858..be76ae0be6 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -164,6 +164,24 @@ const VMStateDescription vmstate_gicv3_gicv4 =3D { } }; =20 +static bool nmi_needed(void *opaque) +{ + GICv3CPUState *cs =3D opaque; + + return cs->gic->nmi_support !=3D 0; +} + +static const VMStateDescription vmstate_gicv3_cpu_nmi =3D { + .name =3D "arm_gicv3_cpu/nmi", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D nmi_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(gicr_inmir0, GICv3CPUState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_gicv3_cpu =3D { .name =3D "arm_gicv3_cpu", .version_id =3D 1, @@ -197,6 +215,10 @@ static const VMStateDescription vmstate_gicv3_cpu =3D { &vmstate_gicv3_cpu_sre_el1, &vmstate_gicv3_gicv4, NULL + }, + .subsections =3D (const VMStateDescription * const []) { + &vmstate_gicv3_cpu_nmi, + NULL } }; =20 @@ -238,6 +260,24 @@ const VMStateDescription vmstate_gicv3_gicd_no_migrati= on_shift_bug =3D { } }; =20 +static bool needed_nmi(void *opaque) +{ + GICv3State *cs =3D opaque; + + return cs->nmi_support !=3D 0; +} + +const VMStateDescription vmstate_gicv3_gicd_nmi =3D { + .name =3D "arm_gicv3/gicd_nmi", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D needed_nmi, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(nmi, GICv3State, GICV3_BMP_SIZE), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_gicv3 =3D { .name =3D "arm_gicv3", .version_id =3D 1, @@ -267,6 +307,10 @@ static const VMStateDescription vmstate_gicv3 =3D { .subsections =3D (const VMStateDescription * const []) { &vmstate_gicv3_gicd_no_migration_shift_bug, NULL + }, + .subsections =3D (const VMStateDescription * const []) { + &vmstate_gicv3_gicd_nmi, + NULL } }; =20 diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 4358c5319c..88533749eb 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -146,6 +146,7 @@ typedef struct { int irq; uint8_t prio; int grp; + bool nmi; } PendingIrq; =20 struct GICv3CPUState { @@ -172,6 +173,7 @@ struct GICv3CPUState { uint32_t gicr_ienabler0; uint32_t gicr_ipendr0; uint32_t gicr_iactiver0; + uint32_t gicr_inmir0; uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */ uint32_t gicr_igrpmodr0; uint32_t gicr_nsacr; @@ -275,6 +277,7 @@ struct GICv3State { GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */ GIC_DECLARE_BITMAP(level); /* Current level */ GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */ + GIC_DECLARE_BITMAP(nmi); /* GICD_INMIR */ uint8_t gicd_ipriority[GICV3_MAXIRQ]; uint64_t gicd_irouter[GICV3_MAXIRQ]; /* Cached information: pointer to the cpu i/f for the CPUs specified @@ -314,6 +317,7 @@ GICV3_BITMAP_ACCESSORS(pending) GICV3_BITMAP_ACCESSORS(active) GICV3_BITMAP_ACCESSORS(level) GICV3_BITMAP_ACCESSORS(edge_trigger) +GICV3_BITMAP_ACCESSORS(nmi) =20 #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common" typedef struct ARMGICv3CommonClass ARMGICv3CommonClass; --=20 2.34.1