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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: "Michael S . Tsirkin" , CC: Huang Rui , Jiqian Chen Subject: [RFC QEMU PATCH v7 1/1] virtio-pci: implement No_Soft_Reset bit Date: Mon, 25 Mar 2024 15:07:24 +0800 Message-ID: <20240325070724.574508-2-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240325070724.574508-1-Jiqian.Chen@amd.com> References: <20240325070724.574508-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000C:EE_|IA1PR12MB8079:EE_ X-MS-Office365-Filtering-Correlation-Id: b8fbb072-c64a-46ab-434e-08dc4c9a4336 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PMwnoDhT1SOn3x+9wd1lnJZFJAvpfhYeq2QNs8EW9CUVkeusPnHTkGORnfrk1kiUMntuAUbPK5J6ZJ5Wi6EGu5KakbdgcILhyRX8GKy/Urx2d6Jtnu6/4blmg7G7pC6P+2qODx/c9yXfV2TzAvWgt3/Mruw8+hJfs9Ckp6GKFN4WAUOwKmPbtqUiVVeZ/W3/VvQaw9Ru4zlyTZrJ/HqeuaT8OhEuhI7i5HeSDxTgUmOgiz4WVpHtgm4Kdci0ZbHE/syBt47EbPjTblEnY398ot6TKKWApiFbTBgSHNOC4FldJ7ecumqngioRNLmADsXZEgBdZx8xunz4dORGPdzH7Zu3mTNs/Goy78h5To9sIYFbu1IaLrOM3e2KRpHBTdcG9OnlcFtoaNSEakC8zBj23++2TR5RylVShG98wdr0y2GCfApCr9j2fzCcdR4GQ49HuROXygMosBmuJRsF3dXK5rL/idRh3qZbBdL7clpwkALKQvL/6rRhH7ckTRo5vYsbCEPtQ4Egx6FCb4h5RJlOQccKRUjOHw3nnphjJBqg+m2zSMIjgS0LCDlTwg6N/G7TrkLqZl9Y4KiJZHtqvt6vg+chv1yIJ57ln2nM6pva4+A+0odgdA7TFe3Ikg7lJhAYNeEVv70K31lsca9ubVgnCgv/KMo0dlA5YYAsDTXW19RGUwCSmGdR2/PdRbIuAEEQkZfnixZyDQwKsgky1hhveGLvEA+k8dPNsNknBpmo/waL8P0nXVL8jywe1VEBwK+o X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(1800799015)(376005)(36860700004)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Mar 2024 07:07:41.5446 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8fbb072-c64a-46ab-434e-08dc4c9a4336 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8079 Received-SPF: permerror client-ip=40.107.243.50; envelope-from=Jiqian.Chen@amd.com; helo=NAM12-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.099, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1711350835661100001 Content-Type: text/plain; charset="utf-8" In current code, when guest does S3, virtio devices are reset due to the bit No_Soft_Reset is not set. After resetting, the display resources of virtio-gpu are destroyed, then the display can't come back and only show blank after resuming. Implement No_Soft_Reset bit of PCI_PM_CTRL register, then guest can check this bit, if this bit is set, the devices resetting will not be done, and then the display can work after resuming. Signed-off-by: Jiqian Chen --- hw/virtio/virtio-pci.c | 38 +++++++++++++++++++++++++++++++++- include/hw/virtio/virtio-pci.h | 5 +++++ 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 1a7039fb0c68..daafda315f8c 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2197,6 +2197,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, E= rror **errp) pcie_cap_lnkctl_init(pci_dev); } =20 + if (proxy->flags & VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET) { + pci_set_word(pci_dev->config + pos + PCI_PM_CTRL, + PCI_PM_CTRL_NO_SOFT_RESET); + } + if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) { /* Init Power Management Control Register */ pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL, @@ -2259,18 +2264,47 @@ static void virtio_pci_reset(DeviceState *qdev) } } =20 +static bool device_no_need_reset(PCIDevice *dev) +{ + if (pci_is_express(dev)) { + uint16_t pmcsr; + + pmcsr =3D pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL= ); + /* + * When No_Soft_Reset bit is set and the device + * is in D3hot state, don't reset device + */ + if ((pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) && + (pmcsr & PCI_PM_CTRL_STATE_MASK) =3D=3D 3) { + return true; + } + } + + return false; +} + static void virtio_pci_bus_reset_hold(Object *obj) { PCIDevice *dev =3D PCI_DEVICE(obj); DeviceState *qdev =3D DEVICE(obj); =20 + if (device_no_need_reset(dev)) { + return; + } + virtio_pci_reset(qdev); =20 if (pci_is_express(dev)) { + uint16_t val =3D 0; + VirtIOPCIProxy *proxy =3D VIRTIO_PCI(dev); + pcie_cap_deverr_reset(dev); pcie_cap_lnkctl_reset(dev); =20 - pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0); + if (proxy->flags & VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET) { + val |=3D PCI_PM_CTRL_NO_SOFT_RESET; + } + pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, val); } } =20 @@ -2297,6 +2331,8 @@ static Property virtio_pci_properties[] =3D { VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true), DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_INIT_PM_BIT, true), + DEFINE_PROP_BIT("x-pcie-pm-no-soft-reset", VirtIOPCIProxy, flags, + VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT, false), DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_INIT_FLR_BIT, true), DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags, diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h index 59d88018c16a..9e67ba38c748 100644 --- a/include/hw/virtio/virtio-pci.h +++ b/include/hw/virtio/virtio-pci.h @@ -43,6 +43,7 @@ enum { VIRTIO_PCI_FLAG_INIT_FLR_BIT, VIRTIO_PCI_FLAG_AER_BIT, VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT, + VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT, }; =20 /* Need to activate work-arounds for buggy guests at vmstate load. */ @@ -79,6 +80,10 @@ enum { /* Init Power Management */ #define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT) =20 +/* Init The No_Soft_Reset bit of Power Management */ +#define VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET \ + (1 << VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT) + /* Init Function Level Reset capability */ #define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT) =20 --=20 2.34.1