From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711098020; cv=none; d=zohomail.com; s=zohoarc; b=g1kvJsBK0S7k+9PFFEnV6wvJ5sxt+cYnWlSX4o5y3vb4pVYcGGZt5DPRkVpWKNC08tNwRKL683dJAje9lJcKKhgFewXKzE/Sg1n3XCbX7DnxELWUoxictGrA10igzqlTZ96nhUWoTJ2cqTLoOkd40f8LtrFiSKazhbU3eVL/nS0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711098020; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aZXIs8sadw+5YTvtfFcTNBIyJz0eNqaMZ6kYLK2RH70=; b=JW5uwR+C7dPi5XpExVUAA6bRwp9imeboMbRrJRhNWCUjJ0yiKUPUm7eoBpEMpnZNT/cw3n702AtcLYLWli/ovOZRn/7rJVLYiC/M0jhjRmlHJ+4H0+A4A9vYNcJvbQAc4YEFA6MqrjzmehqD8xCCis+5/N+LJqPkrDEwZDYo8lw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711098020833774.542855680564; Fri, 22 Mar 2024 02:00:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnakr-0001HR-Te; Fri, 22 Mar 2024 05:00:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnakr-0001GS-3N for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:00:01 -0400 Received: from mail-vk1-xa34.google.com ([2607:f8b0:4864:20::a34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnako-0001tc-75 for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:59:59 -0400 Received: by mail-vk1-xa34.google.com with SMTP id 71dfb90a1353d-4d43a1f0188so705148e0c.2 for ; Fri, 22 Mar 2024 01:59:57 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.53.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:53:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711097997; x=1711702797; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aZXIs8sadw+5YTvtfFcTNBIyJz0eNqaMZ6kYLK2RH70=; b=E2gKLBooRAk5cWdxHnls2nGCErhwTXqFHCR9+tAjEmcg7Ly3B4azA8dDTcmySaxB4n iEzTH5v8iQmFyFoEe0vMr57vt/oAe+eZuEfAJdRbLV7N0VqKGa6Y27byxhSbhmlA3OmR YsNz61o2D7F9TtjDoo3lwqeEF+mp3glX+rQcMXUqoEagN2ZJ+WaQcsfIK2PTKGrhlSNI LrVDN/fxNDGJ5GAP7/kWlBXiatRcN04MoAwgOFQ9MQlGQ/gfQHwKK+OdJw+/R8Ufh7gt DlYO2f3b0KMR9ni6OKdG3kVwDaGGupjzo/vmpaP/YdfkCt35iTEXSu7UiLYEYD/J8SRG 2cpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711097997; x=1711702797; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aZXIs8sadw+5YTvtfFcTNBIyJz0eNqaMZ6kYLK2RH70=; b=KJ5znfnDTl+TquI25FjIuruON+IlJQ02gUaglykIUNUwGTSv6lqCW9+9MSO1mVSS37 3qEyNkSbqm33+IqnjUXAn1zk0ASbPLacj5EaKbMhX4PBWfEsftAAoyAVUwncj500AnB/ 5uv9hR0zDoorS7MFroejvRYFsDtfP5BG2EKgNj7Q2CCcTiyF8MrqttT+leM4nJoM7+n3 /IR+iqtcJ5i3Aizwcf9UbxTLSp5/R5ANHlF9HoFjnuxobOi7Hk2cZ3kSmRGIgVIlcBhd aqX+Rl4M8TCHEVksh8Syy4BF5eX2AzBGu/ipIQ7upDSaVcOd/zARRCuA4lFI2Mvn/K5Y xK6A== X-Gm-Message-State: AOJu0YwjNjSDeSD+46R8sSDMEca8KcdYIubRA4gFsuBlBpTbEOJdiyQK 2DvexWZvg7FS8DyIJGNZjCxgb7/HKrnetzLbeCzR4R5vgsU3BzYKKJZwkzs5KrKE9g== X-Google-Smtp-Source: AGHT+IGeybim0zxVpQSNEizFFfzf6EcTTl27vkBc7WRGykSjsQKPQIrInvDujZe9EWekMCM9F4BrJA== X-Received: by 2002:a05:6a20:b92:b0:1a3:463e:af40 with SMTP id i18-20020a056a200b9200b001a3463eaf40mr1518020pzh.24.1711097611077; Fri, 22 Mar 2024 01:53:31 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , =?UTF-8?q?Cl=C3=A9ment=20Chigot?= , Andrew Jones , Alistair Francis Subject: [PULL 01/15] target/riscv: do not enable all named features by default Date: Fri, 22 Mar 2024 18:53:05 +1000 Message-ID: <20240322085319.1758843-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::a34; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711098021772100001 From: Daniel Henrique Barboza Commit 3b8022269c added the capability of named features/profile extensions to be added in riscv,isa. To do that we had to assign priv versions for each one of them in isa_edata_arr[]. But this resulted in a side-effect: vendor CPUs that aren't running priv_version_latest started to experience warnings for these profile extensions [1]: | $ qemu-system-riscv32 -M sifive_e | qemu-system-riscv32: warning: disabling zic64b extension for hart 0x00000000 because privilege spec version does not match | qemu-system-riscv32: warning: disabling ziccamoa extension for hart 0x00000000 because privilege spec version does not match This is benign as far as the CPU behavior is concerned since disabling both extensions is a no-op (aside from riscv,isa). But the warnings are unpleasant to deal with, especially because we're sending user warnings for extensions that users can't enable/disable. Instead of enabling all named features all the time, separate them by priv version. During finalize() time, after we decided which priv_version the CPU is running, enable/disable all the named extensions based on the priv spec chosen. This will be enough for a bug fix, but as a future work we should look into how we can name these extensions in a way that we don't need an explicit ext_name =3D> priv_ver as we're doing here. The named extensions being added in isa_edata_arr[] that will be enabled/disabled based solely on priv version can be removed from riscv_cpu_named_features[]. 'zic64b' is an extension that can be disabled based on block sizes so it'll retain its own flag and entry. [1] https://lists.gnu.org/archive/html/qemu-devel/2024-03/msg02592.html Reported-by: Cl=C3=A9ment Chigot Fixes: 3b8022269c ("target/riscv: add riscv,isa to named features") Suggested-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Tested-by: Cl=C3=A9ment Chigot Message-ID: <20240312203214.350980-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 8 +++++--- target/riscv/cpu.c | 40 +++++++++----------------------------- target/riscv/tcg/tcg-cpu.c | 14 ++++++++++--- 3 files changed, 25 insertions(+), 37 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2040b90da0..cb750154bd 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -130,10 +130,12 @@ struct RISCVCPUConfig { bool ext_zic64b; =20 /* - * Always 'true' boolean for named features - * TCG always implement/can't be disabled. + * Always 'true' booleans for named features + * TCG always implement/can't be user disabled, + * based on spec version. */ - bool ext_always_enabled; + bool has_priv_1_12; + bool has_priv_1_11; =20 /* Vendor-specific custom extensions */ bool ext_xtheadba; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c160b9216b..36e3e5fdaf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -102,10 +102,10 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom), ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz), - ISA_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, ext_always_enabled), - ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, ext_always_enabled), - ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, ext_always_enabled), - ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, ext_always_enabled), + ISA_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, has_priv_1_11), + ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, has_priv_1_11), + ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11), + ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr), @@ -114,7 +114,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm), ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), - ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, ext_always_enabled), + ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo), ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas), ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc), @@ -179,12 +179,12 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), - ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, ext_always_enabled), + ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), - ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, ext_always_enabl= ed), + ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), - ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, ext_always_enabled), - ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, ext_always_enabled), + ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), @@ -1575,11 +1575,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_= exts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -#define ALWAYS_ENABLED_FEATURE(_name) \ - {.name =3D _name, \ - .offset =3D CPU_CFG_OFFSET(ext_always_enabled), \ - .enabled =3D true} - /* * 'Named features' is the name we give to extensions that we * don't want to expose to users. They are either immutable @@ -1590,23 +1585,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_= exts[] =3D { const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D { MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), =20 - /* - * cache-related extensions that are always enabled - * in TCG since QEMU RISC-V does not have a cache - * model. - */ - ALWAYS_ENABLED_FEATURE("za64rs"), - ALWAYS_ENABLED_FEATURE("ziccif"), - ALWAYS_ENABLED_FEATURE("ziccrse"), - ALWAYS_ENABLED_FEATURE("ziccamoa"), - ALWAYS_ENABLED_FEATURE("zicclsm"), - ALWAYS_ENABLED_FEATURE("ssccptr"), - - /* Other named features that TCG always implements */ - ALWAYS_ENABLED_FEATURE("sstvecd"), - ALWAYS_ENABLED_FEATURE("sstvala"), - ALWAYS_ENABLED_FEATURE("sscounterenw"), - DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ab6db817db..63192ef54f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -315,9 +315,19 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCV= CPU *cpu) =20 static void riscv_cpu_update_named_features(RISCVCPU *cpu) { + if (cpu->env.priv_ver >=3D PRIV_VERSION_1_11_0) { + cpu->cfg.has_priv_1_11 =3D true; + } + + if (cpu->env.priv_ver >=3D PRIV_VERSION_1_12_0) { + cpu->cfg.has_priv_1_12 =3D true; + } + + /* zic64b is 1.12 or later */ cpu->cfg.ext_zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 && cpu->cfg.cbop_blocksize =3D=3D 64 && - cpu->cfg.cboz_blocksize =3D=3D 64; + cpu->cfg.cboz_blocksize =3D=3D 64 && + cpu->cfg.has_priv_1_12; } =20 static void riscv_cpu_validate_g(RISCVCPU *cpu) @@ -1316,8 +1326,6 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); Object *obj =3D OBJECT(cpu); =20 - cpu->cfg.ext_always_enabled =3D true; - misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); riscv_cpu_add_user_properties(obj); --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711097642; cv=none; d=zohomail.com; s=zohoarc; b=bN+5//vBSHBoffuBATgrrFoBjvFpldzLXuKSEG6vqUx1Z3Wf/1ddz8/Tup06bBJykrWksY29sT+11Epjx92scGfSxOqKatK+E0fC7LWRU6Crf9wf0/7u97s939y/TLzXBGR886YXwLv/OsU8irxZifol8Yk54W7neWC3mkTg6kg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711097642; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/T4QIc6EALM5qs4syXwYUJFKzH0rDTI4HgRx0f53UXA=; b=gpaZHS6VyoRjdNloePqBdPLTKbqH3Pi2ddVb7cQkBo8hX6riVOiAQwYRtax8MdvzMilNqVwrQnXMhQraC5a9F3Lp+tYRnNelUUeDxaMcF+pNopNGn2wp3x0BzrGOTf2IcB4xsgn8+iK7XBu4Jdh71jwTLWE/UWprVeO9ZcYx3Mc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711097642924610.0773916594835; Fri, 22 Mar 2024 01:54:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnael-0003mO-6E; Fri, 22 Mar 2024 04:53:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnaei-0003ls-Q8 for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:53:41 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnaef-0000yg-64 for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:53:39 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1e0511a4383so13397005ad.2 for ; Fri, 22 Mar 2024 01:53:36 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.53.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:53:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711097615; x=1711702415; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/T4QIc6EALM5qs4syXwYUJFKzH0rDTI4HgRx0f53UXA=; b=Ttw25UB6LocDVERVF0W/7xsCR49mbPvm7ObTFDp/3/fj3x5y3Fys5cmQisI9Vk18n8 zromp+g6VqFk657ilRvCo8/33QSKh3R8pCfy5r5KgXFmlLW3vpNVVCzvsMU5vFrgKkng pcyHf+0NekZRD2e+UsfrgR0A1G77pLkGemOZDqiFJnqxRDwfyZ0VR5kr0D0aJOKcWc6W g3iJniv86uYktBR4NyLpVpuHmPlTUa70bK8A2idf3TxnlCJ3QR4juobsi6+v3aXQEmFt 6rSuVsfZ8IkLiax/nDjVx1u/NhnDOqj7SRgDGZPeRN+HqKwjlAvpCXiw7Aq5jyxk80YS A1ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711097615; x=1711702415; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/T4QIc6EALM5qs4syXwYUJFKzH0rDTI4HgRx0f53UXA=; b=UW9QgtUC/3F0HhwLHydiX16wF4U6kDWLc7dc9Nv9a4kByleHQ7dBrbkztB1XJfchaG YQ6RWTa8ei9yVr6aJeUenrwxDTfdBlsLjxq84ZjdUPJl74fVI+OUnfnL+hcdDThnV5+c hJXhJkno89eE5z3h89a28EQoW/DqK+IdRUNsCH2NU+yw9ZC7wsxvhIXTuSYUdw7u06lT jMS1L1Fea01AyQuKPYTGz21qwS+zRCBp2mZPHhqGHKh/pndG1WB9u+EfBNmaG2pgDjhu MF0tSYOC6BFbco68rn9bJGPKxF0/qZjNvh4LIYoRrwNUhNevPvdL1X83oWOPbeaWOy29 X6vA== X-Gm-Message-State: AOJu0YxlOoWrb8WkEz6wN1A8nu4fmCo8cT9iKhzru4kvGQ8Dy2po/xhc rBi548vhNltwje8qc06ENN5WeEpoAokG6oLqjkyLhhSdCIO1h/+7RRNL01JggmIk/g== X-Google-Smtp-Source: AGHT+IHLCWLh6I39YY/Q1B2soBjT966aqKb4Y2te1hD/eP7q66uIu/uh9abVVq6QK22c5yFgTmKJmQ== X-Received: by 2002:a17:902:ef10:b0:1dd:135e:2604 with SMTP id d16-20020a170902ef1000b001dd135e2604mr2217417plx.40.1711097614834; Fri, 22 Mar 2024 01:53:34 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Richard Henderson , Alistair Francis , LIU Zhiwei Subject: [PULL 02/15] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() Date: Fri, 22 Mar 2024 18:53:06 +1000 Message-ID: <20240322085319.1758843-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=alistair23@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711097644642100007 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The helper isn't setting env->vstart =3D 0 after its execution, as it is expected from every vector instruction that completes successfully. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Message-ID: <20240314175704.478276-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index fe56c007d5..ca79571ae2 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4781,6 +4781,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ } \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - offset)); = \ } \ + env->vstart =3D 0; = \ /* set tail elements to 1s */ \ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711097642; cv=none; d=zohomail.com; s=zohoarc; b=NMyJMGjrM+kRpRJRaPvsqlJD+gg5AU0Y1o3510W8flXEllkkWGDUMaqZMbsT9T7Bao5UQOWTpmFBKBKd7D+Ctfb0GdvDiSDpRM3gcfFPeHsN6ZFu0fZ0T8j4MywWf7BPY3KTm8zLJL6z3xgSCJvBB5p49tCqPLGIteAiiwF6isQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711097642; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Vw0zayBEls3I265PM6dPGFHfEsT5GLnnXUtSra9I+Qc=; b=QNMxPWlUQyN5WTUEQBpIfh/4gs91NNMx755qA1djPirrWLSe09wWRbg7SbxLQVQInAzsQMDnt6qOz4HMHWfFUkaSCeTaWL5V8oBY8bN2Llohx8uSUDtHS6Pj+UwUOMV6hzTP3KNNGiu6bl3t3+aJsYmGXsKCJijdfVWH5/vspAg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17110976427431022.5794182096724; Fri, 22 Mar 2024 01:54:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnael-0003mR-Pe; Fri, 22 Mar 2024 04:53:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnaek-0003m2-8S for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:53:42 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnaei-0000yp-Jm for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:53:42 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1dddad37712so15709535ad.3 for ; Fri, 22 Mar 2024 01:53:39 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.53.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:53:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711097618; x=1711702418; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vw0zayBEls3I265PM6dPGFHfEsT5GLnnXUtSra9I+Qc=; b=Ax37E4+/X0RFfZCzTKYJU3K2ypK49qpAvFRcTyNJxrdu9YJYszKVXGCyf+V03LIRQ1 z5KNV8nrwEFh0WTBlM6B7q3H2j4eILlBgxARsD+E9t2lUmFOmOUDmfgzBrbDtSaEd8/r 7gH0+R4likyeRa1YN2Ik12ZnZhzy09VC7t440ziQ1zqQQyTpj6c4SWhelOrXaYemyOzl jb/M7aP7b6r/kvQhgCiyaecmY71elOCVInL+KfUcr7TZjhTsfyNoOHuZAgSepI4quaFP ZXuW/91k7WnM/tB/F/BPoZb9gin7B20v+95LzsHSCZ0nnLRKjAkj7a8DlzmkL1ulO7/B ImlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711097618; x=1711702418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vw0zayBEls3I265PM6dPGFHfEsT5GLnnXUtSra9I+Qc=; b=rIAOkyTsEHkGC8WjG1phWv+rZcAqt8GA0d2Yyv1Vj5zaj/vm8cKIDyp1mkgkS7QEdR y5JbEZ6WI64g4m80BLIqLtMfkjcak7zVElcDcaeAgX1cToJ9zq/cMpic9aI4pA+KNhca XLV2rIf9quIkcMrNEcSCshQ4XA6FcA9MbtiLqTB4RMNpIryu5ooefyP2FQED8IZvRDDm C5NPXL8gm8OZfWilvCtjTo9ghgs3VGMKX+0+12MqVw8pqBCuNgjVwV0AhsOYbQawaXQY XQfgdnbTxCRuudXx9oRI704d66elmFOJQHauVy9iEeoVy1KoDVozw7OHFYjzGpdytRJc 6ysg== X-Gm-Message-State: AOJu0YwVY4Z+Ld1Cf+9CAprwbovodYYksm8nKO9FUpKfSAobENE03CsF LJEltFFbbho/S84mCPm81rScRQJznDI9xErvf4KcnR7dbEVwEXUkhYTsemmzADmDzQ== X-Google-Smtp-Source: AGHT+IE84yWqkzNVwLZV55anXtRlr6g7Zr3Zj6HwS/qtozfPnztMlnkD4NPlqSud0hn40LveyKMSjg== X-Received: by 2002:a17:902:db04:b0:1dd:c7ee:2ca6 with SMTP id m4-20020a170902db0400b001ddc7ee2ca6mr2070954plx.50.1711097618285; Fri, 22 Mar 2024 01:53:38 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Richard Henderson , Alistair Francis Subject: [PULL 03/15] trans_rvv.c.inc: set vstart = 0 in int scalar move insns Date: Fri, 22 Mar 2024 18:53:07 +1000 Message-ID: <20240322085319.1758843-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711097644607100005 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza trans_vmv_x_s, trans_vmv_s_x, trans_vfmv_f_s and trans_vfmv_s_f aren't setting vstart =3D 0 after execution. This is usually done by a helper in vector_helper.c but these functions don't use helpers. We'll set vstart after any potential 'over' brconds, and that will also mandate a mark_vs_dirty() too. Fixes: dedc53cbc9 ("target/riscv: rvv-1.0: integer scalar move instructions= ") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20240314175704.478276-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index e42728990e..8c16a9f5b3 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3373,6 +3373,8 @@ static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_= s *a) vec_element_loadi(s, t1, a->rs2, 0, true); tcg_gen_trunc_i64_tl(dest, t1); gen_set_gpr(s, a->rd, dest); + tcg_gen_movi_tl(cpu_vstart, 0); + mark_vs_dirty(s); return true; } return false; @@ -3399,8 +3401,9 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) s1 =3D get_gpr(s, a->rs1, EXT_NONE); tcg_gen_ext_tl_i64(t1, s1); vec_element_storei(s, a->rd, 0, t1); - mark_vs_dirty(s); gen_set_label(over); + tcg_gen_movi_tl(cpu_vstart, 0); + mark_vs_dirty(s); return true; } return false; @@ -3427,6 +3430,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_= f_s *a) } =20 mark_fs_dirty(s); + tcg_gen_movi_tl(cpu_vstart, 0); + mark_vs_dirty(s); return true; } return false; @@ -3452,8 +3457,9 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_= s_f *a) do_nanbox(s, t1, cpu_fpr[a->rs1]); =20 vec_element_storei(s, a->rd, 0, t1); - mark_vs_dirty(s); gen_set_label(over); + tcg_gen_movi_tl(cpu_vstart, 0); + mark_vs_dirty(s); return true; } return false; --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711097702; cv=none; d=zohomail.com; s=zohoarc; b=hkBQ088YCDUEUidKpKWeh6xiwEqETTOEJal2VC2UhlOljK+GBhz/5+YpMUaYozge5iuMkZOYF666EmN3p+Wq485ys5QCjpS54/1tKcyvCfGbwF7brVZl7SFhY8pP9lwGq4WGmBPTydrwjlR48ZoIwoiMAsp0Vr7WFurjtdZsKwU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711097702; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nlXAD82ebz/CyDsPxrmXVSEpvs08EGAPAZEitMfGHS4=; b=l9N+sBtBs8HlPUH+d3xp9kuwVRJ0LgUqDgek1XaEwxqSeUgtEQAYrveDp39ZOvjo4sZx4uq+YtnkzkMzqV1lpNJiBcidTWxdy9wsBL5S0+OdxosIeqRDtzvgF3uBeJi9QkKM3q5ZvSlATLcp994Rd7zo6EvS01nESRXjKmu17c4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711097702170801.0213063618564; Fri, 22 Mar 2024 01:55:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnaeq-0003nM-9g; Fri, 22 Mar 2024 04:53:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnaen-0003mw-GE for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:53:45 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnaem-0000zB-3s for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:53:45 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1dff837d674so14950105ad.3 for ; Fri, 22 Mar 2024 01:53:43 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.53.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:53:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711097622; x=1711702422; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nlXAD82ebz/CyDsPxrmXVSEpvs08EGAPAZEitMfGHS4=; b=W8ya+HGp4bY/TuDybe3Qmfk5du/YmiS/SzKftj5oqkEeKynQeozjIbTdWoto3nb6vP bzYdaqP955/NLpb4pc6wL5L6uDg67V3cMcW3HxwilT9ey+No9cMdtMdnmP2coflfUkTu iCki6xBwyO072Sudq3d2hWcz5AnMZ5+RY8RtPoDpud81ZTb2bGUN6LFR82jFlJpihRIn Ame2gHzVTr5Puk9YFTJ1pCDpg6lJBu6jZZIPm7E2pq+wyYYfW2JQ0hdIqLXfsUdUpzAM 9xQloqkb0mnzVK9EO1wplUbUXBjmXJG/TGIyMHEy38VnOsmrprQlhGF8DH+5U67Zi5S7 0bcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711097622; x=1711702422; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nlXAD82ebz/CyDsPxrmXVSEpvs08EGAPAZEitMfGHS4=; b=FqsFuAKYEssELd+V865PKpz0nY1rVAOg4JeRQBFRQZV24lUGlzaasJZtGwEgkC+EFQ sWjbDgOPUO7x8RV7ZlhB/2VCqQLztXcNYt2cUrm9vkugzEmTs8CudU6RxjLZBTkOKhJ7 9oB93fZs+r8mE8OnqBM6POpg/wwcCUP+SPKAVnx5MaEnuFlRUQA5EI9tTgIKmgwDFvPO mve1+0/iui0PuskDH+HdpfSCIRp4Ci5vHQlrtGEvm6jV/LzmgS0jtVWNlM5Csv0v85W3 k5IcIY0BMBzY1R9mpSmI0B8A0fUKVCTzzwboFvuw26zxX/owdFiJET5LJ3SqhaAwlm2L BvLQ== X-Gm-Message-State: AOJu0Ywf1HHwrVBcjtPcuVwjLRBHliR++DmiIjW36NcL7e4CcS45SRKF tM7sHNL9ax5wWq9JBMuS4IBYxvguQ9ztj+PzHVv6UKBcDY5AYrTeoIcsCu/0ZwFXvg== X-Google-Smtp-Source: AGHT+IG2KUmHIsErl4CjZ2NuTKtWM5sMXYyIvmQTyrkiVaZHQ9Q+IGjv9KwyyJtcf5eWC3ezfUD6EA== X-Received: by 2002:a17:902:ea12:b0:1de:f18c:cdd with SMTP id s18-20020a170902ea1200b001def18c0cddmr2172556plg.3.1711097621853; Fri, 22 Mar 2024 01:53:41 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Richard Henderson , Alistair Francis , LIU Zhiwei Subject: [PULL 04/15] target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess Date: Fri, 22 Mar 2024 18:53:08 +1000 Message-ID: <20240322085319.1758843-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711097702820100007 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza vmvr_v isn't handling the case where the host might be big endian and the bytes to be copied aren't sequential. Suggested-by: Richard Henderson Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-ID: <20240314175704.478276-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ca79571ae2..34ac4aa808 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5075,9 +5075,17 @@ void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVSta= te *env, uint32_t desc) uint32_t startb =3D env->vstart * sewb; uint32_t i =3D startb; =20 + if (HOST_BIG_ENDIAN && i % 8 !=3D 0) { + uint32_t j =3D ROUND_UP(i, 8); + memcpy((uint8_t *)vd + H1(j - 1), + (uint8_t *)vs2 + H1(j - 1), + j - i); + i =3D j; + } + memcpy((uint8_t *)vd + H1(i), (uint8_t *)vs2 + H1(i), - maxsz - startb); + maxsz - i); =20 env->vstart =3D 0; } --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711098068; cv=none; d=zohomail.com; s=zohoarc; b=jS5jmAjh+bIAteUfVi4yuEMR0SnBdEJl/XNcqVOXfPpTxr6EURudfFvRhjuct77tNNNVA2MkMfvh7BareyjISB+8kj6SkzDZunjX4dWqfcvOUxSboM4tZ5uwY8m2hWm/BEOETS9eUuJN+7xmx7/UB1+4UGWmTu6HTKsW63CJQhw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711098068; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Eain6TjZs4KlayZqmfzJXWzUESCa0jrf8H67G9gsemE=; b=QL79OhjcQxKyrdnu/GF6aF6Xg4EdJK2Qj481Rej1VgolP4iQkNwxvjNEasa93+Ziokswl8Sm0o77GqzoHleGLlTv7mYYGH+YVEhMRIh5PUilj6ADU8q0NHLWDdH9M3hbqCjqKx9Z1RVr0DSUf1X83Jn+A58eikqp74f/ZqwYcZQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711098068755107.8437874119295; Fri, 22 Mar 2024 02:01:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnalh-0002bD-B7; Fri, 22 Mar 2024 05:00:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnalf-0002Ok-G4 for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:00:51 -0400 Received: from mail-ua1-x935.google.com ([2607:f8b0:4864:20::935]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnald-0002GV-Qi for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:00:51 -0400 Received: by mail-ua1-x935.google.com with SMTP id a1e0cc1a2514c-7db1a2c1f96so986399241.0 for ; Fri, 22 Mar 2024 02:00:48 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.53.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:53:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711098048; x=1711702848; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Eain6TjZs4KlayZqmfzJXWzUESCa0jrf8H67G9gsemE=; b=lenyC2nxTJaKTWfzJMvsm8cgJEgAF1aYRSBHLlJ1RlHo1GrZ9UmySNsG3TPYHq7Uuc E+y38IbRiixDd2Q9EuPcCGxKum6bhUZsobkJQFMSQ81ah9Mp0HxCpWNSQniSKOTHFms+ 251Zp+6wPmV3Kc9+QYrR6Swv9mxN2zcJrhQqv/xA5jYJJw+3Qoc/g+dausRdoNrFN/XK /RFpyUgyj2qritXK0tutkE7YsTMyVkyC7CVYRZifp1J3zkS8qBIXDw4fRqGRODWqhIA5 wNdW/IElmjxjqso6Hj689Ay6sENr89ZbG+0NKTaZrzLVn0pHD1Z6b2LSgRRCLQfE0mmt 8oNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711098048; x=1711702848; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Eain6TjZs4KlayZqmfzJXWzUESCa0jrf8H67G9gsemE=; b=iQ42ki4TKouEjzvWUyKyIimN7BAAm1kKswYhrZIHRlf4cwfaT6w+ZZ0Ex81I0Ic+Co wArKRnkhUoLMsPdDo4z7z4gRUN+ze4YMFClMf6tG6HvJHzJh6+yAyho16o4Yek6pNrPd //zqSm0eFYwwNY3c4clF2DwWVlOyZtWd/eWPNqE1YF4DZBnP+eVnFsR/IURs/znUWFP6 47xM58MPJviZgpheKoJVU2KHZQL6E2YABXq6/Z/9fGRQMWOfFQyLPqzIufe9hyCADKAw ElYoyIlKJ90uvqE+fIwESKPsKlOi+uw65WlYVn8x8gyYN4KRP+A7blhbh3NIvfMxSjRj iq5w== X-Gm-Message-State: AOJu0YxCYbkDTTVeghVPM8HHNIvwhw1U+5iT2CHkOu+COailuQ+BTBVi D6+fIzar/RhjED6t91ukQNC9TXBlSKIywuqq3o0LxAjywDVsHqrj5yHWmM8ABR80ZQ== X-Google-Smtp-Source: AGHT+IHMePlEEepUGlYPmQwDEOZ9wktx9ltXupP2zK/RW7bH2Vs1khYrvVAmbixcH7mgpT7feW91ug== X-Received: by 2002:a05:6a20:3d1d:b0:1a3:6f9a:5434 with SMTP id y29-20020a056a203d1d00b001a36f9a5434mr2224347pzi.62.1711097625574; Fri, 22 Mar 2024 01:53:45 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , LIU Zhiwei , Richard Henderson Subject: [PULL 05/15] target/riscv: always clear vstart in whole vec move insns Date: Fri, 22 Mar 2024 18:53:09 +1000 Message-ID: <20240322085319.1758843-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::935; envelope-from=alistair23@gmail.com; helo=mail-ua1-x935.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711098069905100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza These insns have 2 paths: we'll either have vstart already cleared if vstart_eq_zero or we'll do a brcond to check if vstart >=3D maxsz to call the 'vmvr_v' helper. The helper will clear vstart if it executes until the end, or if vstart >=3D vl. For starters, the check itself is wrong: we're checking vstart >=3D maxsz, when in fact we should use vstart in bytes, or 'startb' like 'vmvr_v' is calling, to do the comparison. But even after fixing the comparison we'll still need to clear vstart in the end, which isn't happening too. We want to make the helpers responsible to manage vstart, including these corner cases, precisely to avoid these situations: - remove the wrong vstart >=3D maxsz cond from the translation; - add a 'startb >=3D maxsz' cond in 'vmvr_v', and clear vstart if that happens. This way we're now sure that vstart is being cleared in the end of the execution, regardless of the path taken. Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-ID: <20240314175704.478276-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 5 +++++ target/riscv/insn_trans/trans_rvv.c.inc | 3 --- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 34ac4aa808..bcc553c0e2 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5075,6 +5075,11 @@ void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVSta= te *env, uint32_t desc) uint32_t startb =3D env->vstart * sewb; uint32_t i =3D startb; =20 + if (startb >=3D maxsz) { + env->vstart =3D 0; + return; + } + if (HOST_BIG_ENDIAN && i % 8 !=3D 0) { uint32_t j =3D ROUND_UP(i, 8); memcpy((uint8_t *)vd + H1(j - 1), diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 8c16a9f5b3..52c26a7834 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3664,12 +3664,9 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME= * a) \ vreg_ofs(s, a->rs2), maxsz, maxsz); \ mark_vs_dirty(s); \ } else { \ - TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \ tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v= ); \ mark_vs_dirty(s); \ - gen_set_label(over); \ } \ return true; \ } \ --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711099496; cv=none; d=zohomail.com; s=zohoarc; b=KoeRTcfnNb+PAGKbg7Pz3FFjrqjUIWtSw4Ic87h9A2AmHsfb9gTi0OnTGoOQRfItW8k11c1PjcanS8xWwCWOCKjhj9XyMnKnx/L/hLPMf7PeFjwFExg37FvEW6eITR3IrVQkE37te5BDZQ8LFsuOdfcBgwlQwtC/I5+4h5eXAco= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711099496; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2ZLHwysM1SOLunsTOPiCHJUq8bBNp1FdzR5sg9NjsiA=; b=cPYmFXU5i1Gs7hBIk0zoKAEXPMXSSIZezkafzBRv6Q16HHN3PjGC2xmZEVnkVfsF8IZR0eYx8TJ/kcYA+kjwg3Q27B9mC7sVsXIzRhRO+AjvIPc6R3BAXr7+bRE+T9xk4HTC41RZbG5SReFUEoX92INdRfJnbVbqdFaBk6tep3g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711099496769217.55976396398717; Fri, 22 Mar 2024 02:24:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnb8c-0003jl-H6; Fri, 22 Mar 2024 05:24:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnb8a-0003jF-NN for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:24:32 -0400 Received: from mail-yw1-x112f.google.com ([2607:f8b0:4864:20::112f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnb8Z-0006BP-01 for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:24:32 -0400 Received: by mail-yw1-x112f.google.com with SMTP id 00721157ae682-60fff981e2aso19136117b3.3 for ; Fri, 22 Mar 2024 02:24:30 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.53.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:53:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711099470; x=1711704270; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2ZLHwysM1SOLunsTOPiCHJUq8bBNp1FdzR5sg9NjsiA=; b=nWHLp2ckY73YSaBnVHi8bO9abxLdkVMBNIZGXySplB/tLKtXiTqHn/4gGxd+aOb2RJ Am8rYoAJYgD/QmKoeXr982SlMviE+/RinNg0RIAlcAI00cIOqWiU0ZaQTcX84Yz2P/mY FVG+pw/baVgajtLNKpwBtBxj86Df+ivD+8lV3fieb7j0pmVsdzV5UTw2xxz9Yo+xP6+J g1qhjnd73/9siFtiyW9eC3grtIdIeVHBxZIHt/9rdf0ZSh1Q0JKrk4k4Tt9LHWQvY5jf L/+1rEpPiPR6w2s55kPdV8SnFlfUyIgAhXWCOlxP3/V/0A9aX2zJ5lZT5TnE/mgkbqSJ bZWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711099470; x=1711704270; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2ZLHwysM1SOLunsTOPiCHJUq8bBNp1FdzR5sg9NjsiA=; b=OG5hsQXb3hIbAIRFT3ZtNn/SHlBTuJb/hN5HFbuJMoChDfW9mq9/vPjjpCExoGLdbD O0KvpNruvTJ+lrnrDsQOpMg59dsbgPFnRoIsy4pDPawoz6n9d19DLBRV33SJODiyyEm2 a7hi66Hy77F1JPVgpFc3N7II9kQXaTWork54jFJ5CR8GTmjfLkDqOiasiOSf+YFVpd3I ERpU9O0nqZdfuuLo87zVFyIGqaSbHj63ASYPGtMHSq6J0kPjd+YZ6n45Y6ddy/BvgR5b e/CcYRpHlvqBB/yaFBx0OK7l8tVaCgOyeNu+Y55XaJIQQxvmYODSAwWA9X1VPJVzfixo L3ig== X-Gm-Message-State: AOJu0Yw9hYDFkzN06YVvOF18/WB85T2AcLevQnfB655C9J2pB+KlcId8 /s1nCWRXcDEvgQbZAOUfe5JWtMVFI6BFCCjn9nrXjXqWR7Qt+Am3fzHNWVH2WESLBQ== X-Google-Smtp-Source: AGHT+IF68KOocXaLH0+hKYjPJnHKT+7MM95xdDwd7ik97RMMtCHG84GiF1a27TBF12uxk0JPlS5/qQ== X-Received: by 2002:a05:6a20:431f:b0:1a3:a1c8:96bf with SMTP id h31-20020a056a20431f00b001a3a1c896bfmr1716068pzk.38.1711097628973; Fri, 22 Mar 2024 01:53:48 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Max Chou , Alistair Francis Subject: [PULL 06/15] target/riscv: always clear vstart for ldst_whole insns Date: Fri, 22 Mar 2024 18:53:10 +1000 Message-ID: <20240322085319.1758843-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::112f; envelope-from=alistair23@gmail.com; helo=mail-yw1-x112f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711099497261100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Commit 8ff8ac6329 added a conditional to guard the vext_ldst_whole() helper if vstart >=3D evl. But by skipping the helper we're also not setting vstart =3D 0 at the end of the insns, which is incorrect. We'll move the conditional to vext_ldst_whole(), following in line with the removal of all brconds vstart >=3D vl that the next patch will do. The idea is to make the helpers responsible for their own vstart management. Fix ldst_whole isns by: - remove the brcond that skips the helper if vstart is >=3D evl; - vext_ldst_whole() now does an early exit with the same check, where evl =3D (vlenb * nf) >> log2_esz, but the early exit will also clear vstart. The 'width' param is now unneeded in ldst_whole_trans() and is also removed. It was used for the evl calculation for the brcond and has no other use now. The 'width' is reflected in vext_ldst_whole() via log2_esz, which is encoded by GEN_VEXT_LD_WHOLE() as "ctzl(sizeof(ETYPE))". Suggested-by: Max Chou Fixes: 8ff8ac6329 ("target/riscv: rvv: Add missing early exit condition for= whole register load/store") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Max Chou Message-ID: <20240314175704.478276-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 5 +++ target/riscv/insn_trans/trans_rvv.c.inc | 52 +++++++++++-------------- 2 files changed, 28 insertions(+), 29 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index bcc553c0e2..1f4c276b21 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -572,6 +572,11 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVS= tate *env, uint32_t desc, uint32_t vlenb =3D riscv_cpu_cfg(env)->vlenb; uint32_t max_elems =3D vlenb >> log2_esz; =20 + if (env->vstart >=3D ((vlenb * nf) >> log2_esz)) { + env->vstart =3D 0; + return; + } + k =3D env->vstart / max_elems; off =3D env->vstart % max_elems; =20 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 52c26a7834..1366445e1f 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1097,13 +1097,9 @@ GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld= _us_check) typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32); =20 static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf, - uint32_t width, gen_helper_ldst_whole *fn, + gen_helper_ldst_whole *fn, DisasContext *s) { - uint32_t evl =3D s->cfg_ptr->vlenb * nf / width; - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over); - TCGv_ptr dest; TCGv base; TCGv_i32 desc; @@ -1120,8 +1116,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs= 1, uint32_t nf, =20 fn(dest, base, tcg_env, desc); =20 - gen_set_label(over); - return true; } =20 @@ -1129,42 +1123,42 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t = rs1, uint32_t nf, * load and store whole register instructions ignore vtype and vl setting. * Thus, we don't need to check vill bit. (Section 7.9) */ -#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH) \ +#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF) \ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ { \ if (require_rvv(s) && \ QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \ - return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH, \ + return ldst_whole_trans(a->rd, a->rs1, ARG_NF, \ gen_helper_##NAME, s); \ } \ return false; \ } =20 -GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1) -GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2) -GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4) -GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8) -GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1) -GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2) -GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4) -GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8) -GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1) -GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2) -GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4) -GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8) -GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1) -GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2) -GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4) -GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8) +GEN_LDST_WHOLE_TRANS(vl1re8_v, 1) +GEN_LDST_WHOLE_TRANS(vl1re16_v, 1) +GEN_LDST_WHOLE_TRANS(vl1re32_v, 1) +GEN_LDST_WHOLE_TRANS(vl1re64_v, 1) +GEN_LDST_WHOLE_TRANS(vl2re8_v, 2) +GEN_LDST_WHOLE_TRANS(vl2re16_v, 2) +GEN_LDST_WHOLE_TRANS(vl2re32_v, 2) +GEN_LDST_WHOLE_TRANS(vl2re64_v, 2) +GEN_LDST_WHOLE_TRANS(vl4re8_v, 4) +GEN_LDST_WHOLE_TRANS(vl4re16_v, 4) +GEN_LDST_WHOLE_TRANS(vl4re32_v, 4) +GEN_LDST_WHOLE_TRANS(vl4re64_v, 4) +GEN_LDST_WHOLE_TRANS(vl8re8_v, 8) +GEN_LDST_WHOLE_TRANS(vl8re16_v, 8) +GEN_LDST_WHOLE_TRANS(vl8re32_v, 8) +GEN_LDST_WHOLE_TRANS(vl8re64_v, 8) =20 /* * The vector whole register store instructions are encoded similar to * unmasked unit-stride store of elements with EEW=3D8. */ -GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1) -GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1) -GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1) -GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1) +GEN_LDST_WHOLE_TRANS(vs1r_v, 1) +GEN_LDST_WHOLE_TRANS(vs2r_v, 2) +GEN_LDST_WHOLE_TRANS(vs4r_v, 4) +GEN_LDST_WHOLE_TRANS(vs8r_v, 8) =20 /* *** Vector Integer Arithmetic Instructions --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711097710; cv=none; d=zohomail.com; s=zohoarc; b=jbTjJTf4D/EnAuTI3JBTkIgfUF6lvDitobAXgaSXk8hxjVh5ikLudsTHka2kGxuh5Hcy3QmNXUrKClq2QEq5LHSOZ9B/mG6wsPhsU0iteXXSLeReHznXBzoW35aPRlTr4jprEEKA9ud+Nng8lR9ILZ5M9p16IfnDXlBnxkrDQtM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711097710; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1gN4abpXVFoOBWWLDy0HBm7fpP91yFUDmiVt+iFPKpI=; b=bG1VNTcR2MVS9HaAYlJMOpaKleSrCS2ouwhzGyTT0RS/IphWpe2oLb1XmTOlJjKAjlJ23KLHyfslLadaAHOYCoHmGN2pWQPWSfcpGGmiNK/+6j0/XJKlgXt4kKxZhM7bNfNcvmAnp5JqxPihRpW6vwDtBm9nZJr8Hv2tWCRcSSQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711097710611330.30320412345884; Fri, 22 Mar 2024 01:55:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnaf2-0003pa-D4; Fri, 22 Mar 2024 04:54:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnaf0-0003pS-4X for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:53:58 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnaew-0000za-Lm for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:53:57 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1dca3951ad9so11889515ad.3 for ; Fri, 22 Mar 2024 01:53:54 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.53.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:53:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711097633; x=1711702433; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1gN4abpXVFoOBWWLDy0HBm7fpP91yFUDmiVt+iFPKpI=; b=lG+G/p4rLc3a4tI1/22Fc/OspAVehZtUoJ+GYTeSxYWdYqyD4qLr/ZtsG7he4uduE/ H/3pxeYxnL/UAzozqyvib3z97RcNJTdRVafGBLE0vgcOG4hLDO4oSyUIIRmXXPUwVo/g QVJYguLSfYLVgzohnxnPW9/PqYFFDADYDFVc32ny75E9GGTJIJLgBGllNuaR/4NgQ7hQ u06f30UxJ2AuT7Tb9TrDlHqkON2hYwsekMWBjlYvwBnn5A+3Fsx91JXXxTIC/tvYRjD1 s2/vXUrIc5Lc6GMIuAbT5slhMSoxs5OpeJ+69/rWEJloNrMNAF42DvHNipdZZmmQfUHv qAGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711097633; x=1711702433; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1gN4abpXVFoOBWWLDy0HBm7fpP91yFUDmiVt+iFPKpI=; b=OhtGFirjGlAHHvTgCSU+gidDkmUBtpB9NoM+LiBPvuR7vnRP2BQH0lpq2gQwVeY+2P +jMiJgyxN4LIpWxXnbPncphXW6fcTcWyfwIuzabZJGuHyahfyWVbsTUIJWayNMW5NxXz oeS+HUDPlkuKJSuUFwd6xjwLNE3Y0AUWyB8neJwpaBChUXkmPxruhTGIcKnYxyfcNRkf B6mvWszxLjF+4xQmvX56hHiesN5VY54FWr3yHyK6VzyG/azWeGNRdhxlVKv5iohW7NbU GVv58f5g8vWMGKPCIuBok39mHu2uMA0ig93Gs/FiTYybZZWMpveN22oguZloNVk9eHXh NGng== X-Gm-Message-State: AOJu0YxcA4yvYosAXhJ77eyPEU1TQHcTYcTn7PXAQsOBZXkqlTYA5ZuZ jMt2OB0IR5GtgKrG8RPP9uGo5hfRFiz/4o9GgrMwe4XxwC6JChdIj0g2LwoHR86H5A== X-Google-Smtp-Source: AGHT+IGCMsZe5yjKuV/uLh9FhA0nwu7xru2g5PREXestv5TrlVcVrNBi5QeFa9rBTkvjkKV0sVSDcQ== X-Received: by 2002:a17:902:848a:b0:1e0:1d9d:1447 with SMTP id c10-20020a170902848a00b001e01d9d1447mr1488527plo.64.1711097632750; Fri, 22 Mar 2024 01:53:52 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Richard Henderson , Alistair Francis Subject: [PULL 07/15] target/riscv/vector_helpers: do early exit when vstart >= vl Date: Fri, 22 Mar 2024 18:53:11 +1000 Message-ID: <20240322085319.1758843-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711097710883100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We're going to make changes that will required each helper to be responsible for the 'vstart' management, i.e. we will relieve the 'vstart < vl' assumption that helpers have today. Helpers are usually able to deal with vstart >=3D vl, i.e. doing nothing aside from setting vstart =3D 0 at the end, but the tail update functions will update the tail regardless of vstart being valid or not. Unifying the tail update process in a single function that would handle the vstart >=3D vl case isn't trivial (see [1] for more info). This patch takes a blunt approach: do an early exit in every single vector helper if vstart >=3D vl, unless the helper is guarded with vstart_eq_zero in the translation. For those cases the helper is ready to deal with cases where vl might be zero, i.e. throwing exceptions based on it like vcpop_m() and first_m(). Helpers that weren't changed: - vcpop_m(), vfirst_m(), vmsetm(), GEN_VEXT_VIOTA_M(): these are guarded directly with vstart_eq_zero; - GEN_VEXT_VCOMPRESS_VM(): guarded with vcompress_vm_check() that checks vstart_eq_zero; - GEN_VEXT_RED(): guarded with either reduction_check() or reduction_widen_check(), both check vstart_eq_zero; - GEN_VEXT_FRED(): guarded with either freduction_check() or freduction_widen_check(), both check vstart_eq_zero. Another exception is vext_ldst_whole(), who operates on effective vector length regardless of the current settings in vtype and vl. [1] https://lore.kernel.org/qemu-riscv/1590234b-0291-432a-a0fa-c5a6876097bc= @linux.alibaba.com/ Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20240314175704.478276-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/vector_internals.h | 9 +++++ target/riscv/vcrypto_helper.c | 32 ++++++++++++++++ target/riscv/vector_helper.c | 66 +++++++++++++++++++++++++++++++++ target/riscv/vector_internals.c | 4 ++ 4 files changed, 111 insertions(+) diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal= s.h index 842765f6c1..9e1e15b575 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -24,6 +24,13 @@ #include "tcg/tcg-gvec-desc.h" #include "internals.h" =20 +#define VSTART_CHECK_EARLY_EXIT(env) do { \ + if (env->vstart >=3D env->vl) { \ + env->vstart =3D 0; \ + return; \ + } \ +} while (0) + static inline uint32_t vext_nf(uint32_t desc) { return FIELD_EX32(simd_data(desc), VDATA, NF); @@ -151,6 +158,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ /* set masked-off elements to 1s */ \ diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index e2d719b13b..f7423df226 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -222,6 +222,8 @@ static inline void xor_round_key(AESState *round_state,= AESState *round_key) uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ uint32_t vta =3D vext_vta(desc); = \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ AESState round_key; \ round_key.d[0] =3D *((uint64_t *)vs2 + H8(i * 2 + 0)); = \ @@ -246,6 +248,8 @@ static inline void xor_round_key(AESState *round_state,= AESState *round_key) uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ uint32_t vta =3D vext_vta(desc); = \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ AESState round_key; \ round_key.d[0] =3D *((uint64_t *)vs2 + H8(0)); = \ @@ -305,6 +309,8 @@ void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, = uint32_t uimm, uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); uint32_t vta =3D vext_vta(desc); =20 + VSTART_CHECK_EARLY_EXIT(env); + uimm &=3D 0b1111; if (uimm > 10 || uimm =3D=3D 0) { uimm ^=3D 0b1000; @@ -351,6 +357,8 @@ void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, = uint32_t uimm, uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); uint32_t vta =3D vext_vta(desc); =20 + VSTART_CHECK_EARLY_EXIT(env); + uimm &=3D 0b1111; if (uimm > 14 || uimm < 2) { uimm ^=3D 0b1000; @@ -457,6 +465,8 @@ void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2,= CPURISCVState *env, uint32_t total_elems; uint32_t vta =3D vext_vta(desc); =20 + VSTART_CHECK_EARLY_EXIT(env); + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { if (sew =3D=3D MO_32) { vsha2ms_e32(((uint32_t *)vd) + i * 4, ((uint32_t *)vs1) + i * = 4, @@ -572,6 +582,8 @@ void HELPER(vsha2ch32_vv)(void *vd, void *vs1, void *vs= 2, CPURISCVState *env, uint32_t total_elems; uint32_t vta =3D vext_vta(desc); =20 + VSTART_CHECK_EARLY_EXIT(env); + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, ((uint32_t *)vs1) + 4 * i + 2); @@ -590,6 +602,8 @@ void HELPER(vsha2ch64_vv)(void *vd, void *vs1, void *vs= 2, CPURISCVState *env, uint32_t total_elems; uint32_t vta =3D vext_vta(desc); =20 + VSTART_CHECK_EARLY_EXIT(env); + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, ((uint64_t *)vs1) + 4 * i + 2); @@ -608,6 +622,8 @@ void HELPER(vsha2cl32_vv)(void *vd, void *vs1, void *vs= 2, CPURISCVState *env, uint32_t total_elems; uint32_t vta =3D vext_vta(desc); =20 + VSTART_CHECK_EARLY_EXIT(env); + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, (((uint32_t *)vs1) + 4 * i)); @@ -626,6 +642,8 @@ void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs= 2, CPURISCVState *env, uint32_t total_elems; uint32_t vta =3D vext_vta(desc); =20 + VSTART_CHECK_EARLY_EXIT(env); + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, (((uint64_t *)vs1) + 4 * i)); @@ -658,6 +676,8 @@ void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, v= oid *vs2_vptr, uint32_t *vs1 =3D vs1_vptr; uint32_t *vs2 =3D vs2_vptr; =20 + VSTART_CHECK_EARLY_EXIT(env); + for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { uint32_t w[24]; for (int j =3D 0; j < 8; j++) { @@ -757,6 +777,8 @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, ui= nt32_t uimm, uint32_t *vs2 =3D vs2_vptr; uint32_t v1[8], v2[8], v3[8]; =20 + VSTART_CHECK_EARLY_EXIT(env); + for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { for (int k =3D 0; k < 8; k++) { v2[k] =3D bswap32(vd[H4(i * 8 + k)]); @@ -780,6 +802,8 @@ void HELPER(vghsh_vv)(void *vd_vptr, void *vs1_vptr, vo= id *vs2_vptr, uint32_t vta =3D vext_vta(desc); uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); =20 + VSTART_CHECK_EARLY_EXIT(env); + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { uint64_t Y[2] =3D {vd[i * 2 + 0], vd[i * 2 + 1]}; uint64_t H[2] =3D {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; @@ -817,6 +841,8 @@ void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CP= URISCVState *env, uint32_t vta =3D vext_vta(desc); uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); =20 + VSTART_CHECK_EARLY_EXIT(env); + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { uint64_t Y[2] =3D {brev8(vd[i * 2 + 0]), brev8(vd[i * 2 + 1])}; uint64_t H[2] =3D {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; @@ -853,6 +879,8 @@ void HELPER(vsm4k_vi)(void *vd, void *vs2, uint32_t uim= m5, CPURISCVState *env, uint32_t esz =3D sizeof(uint32_t); uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); =20 + VSTART_CHECK_EARLY_EXIT(env); + for (uint32_t i =3D group_start; i < group_end; ++i) { uint32_t vstart =3D i * egs; uint32_t vend =3D (i + 1) * egs; @@ -909,6 +937,8 @@ void HELPER(vsm4r_vv)(void *vd, void *vs2, CPURISCVStat= e *env, uint32_t desc) uint32_t esz =3D sizeof(uint32_t); uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); =20 + VSTART_CHECK_EARLY_EXIT(env); + for (uint32_t i =3D group_start; i < group_end; ++i) { uint32_t vstart =3D i * egs; uint32_t vend =3D (i + 1) * egs; @@ -943,6 +973,8 @@ void HELPER(vsm4r_vs)(void *vd, void *vs2, CPURISCVStat= e *env, uint32_t desc) uint32_t esz =3D sizeof(uint32_t); uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); =20 + VSTART_CHECK_EARLY_EXIT(env); + for (uint32_t i =3D group_start; i < group_end; ++i) { uint32_t vstart =3D i * egs; uint32_t vend =3D (i + 1) * egs; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 1f4c276b21..63a1083f03 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -207,6 +207,8 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, uint32_t esz =3D 1 << log2_esz; uint32_t vma =3D vext_vma(desc); =20 + VSTART_CHECK_EARLY_EXIT(env); + for (i =3D env->vstart; i < env->vl; i++, env->vstart++) { k =3D 0; while (k < nf) { @@ -272,6 +274,8 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, uint32_t max_elems =3D vext_max_elems(desc, log2_esz); uint32_t esz =3D 1 << log2_esz; =20 + VSTART_CHECK_EARLY_EXIT(env); + /* load bytes from guest memory */ for (i =3D env->vstart; i < evl; i++, env->vstart++) { k =3D 0; @@ -386,6 +390,8 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t esz =3D 1 << log2_esz; uint32_t vma =3D vext_vma(desc); =20 + VSTART_CHECK_EARLY_EXIT(env); + /* load bytes from guest memory */ for (i =3D env->vstart; i < env->vl; i++, env->vstart++) { k =3D 0; @@ -477,6 +483,8 @@ vext_ldff(void *vd, void *v0, target_ulong base, target_ulong addr, offset, remain; int mmu_index =3D riscv_env_mmu_index(env, false); =20 + VSTART_CHECK_EARLY_EXIT(env); + /* probe every access */ for (i =3D env->vstart; i < env->vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { @@ -882,6 +890,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *= vs2, \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ @@ -914,6 +924,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ uint32_t vta =3D vext_vta(desc); = \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { = \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); = \ ETYPE carry =3D vext_elem_mask(v0, i); = \ @@ -949,6 +961,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *= vs2, \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ @@ -987,6 +1001,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,= \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ ETYPE carry =3D !vm && vext_elem_mask(v0, i); \ @@ -1083,6 +1099,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t vma =3D vext_vma(desc); = \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ /* set masked-off elements to 1s */ \ @@ -1130,6 +1148,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ /* set masked-off elements to 1s */ \ @@ -1192,6 +1212,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ @@ -1257,6 +1279,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -1804,6 +1828,8 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState = *env, \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ *((ETYPE *)vd + H(i)) =3D s1; \ @@ -1828,6 +1854,8 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVStat= e *env, \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ *((ETYPE *)vd + H(i)) =3D (ETYPE)s1; \ } \ @@ -1851,6 +1879,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE *vt =3D (!vext_elem_mask(v0, i) ? vs2 : vs1); \ *((ETYPE *)vd + H(i)) =3D *(vt + H(i)); \ @@ -1875,6 +1905,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ ETYPE d =3D (!vext_elem_mask(v0, i) ? s2 : \ @@ -1920,6 +1952,8 @@ vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2, uint32_t vl, uint32_t vm, int vxrm, opivv2_rm_fn *fn, uint32_t vma, uint32_t esz) { + VSTART_CHECK_EARLY_EXIT(env); + for (uint32_t i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { /* set masked-off elements to 1s */ @@ -2045,6 +2079,8 @@ vext_vx_rm_1(void *vd, void *v0, target_long s1, void= *vs2, uint32_t vl, uint32_t vm, int vxrm, opivx2_rm_fn *fn, uint32_t vma, uint32_t esz) { + VSTART_CHECK_EARLY_EXIT(env); + for (uint32_t i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { /* set masked-off elements to 1s */ @@ -2842,6 +2878,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ /* set masked-off elements to 1s */ \ @@ -2885,6 +2923,8 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ /* set masked-off elements to 1s */ \ @@ -3471,6 +3511,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ if (vl =3D=3D 0) { \ return; \ } \ @@ -3992,6 +4034,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ @@ -4032,6 +4076,8 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -4225,6 +4271,8 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ *((ETYPE *)vd + H(i)) =3D \ @@ -4549,6 +4597,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t i; \ int a, b; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ a =3D vext_elem_mask(vs1, i); \ b =3D vext_elem_mask(vs2, i); \ @@ -4742,6 +4792,8 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *= env, uint32_t desc) \ uint32_t vma =3D vext_vma(desc); = \ int i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ /* set masked-off elements to 1s */ \ @@ -4777,6 +4829,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t vma =3D vext_vma(desc); = \ target_ulong offset =3D s1, i_min, i; = \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ i_min =3D MAX(env->vstart, offset); = \ for (i =3D i_min; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -4810,6 +4864,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t vma =3D vext_vma(desc); = \ target_ulong i_max, i_min, i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ i_min =3D MIN(s1 < vlmax ? vlmax - s1 : 0, vl); = \ i_max =3D MAX(i_min, env->vstart); = \ for (i =3D env->vstart; i < i_max; ++i) { = \ @@ -4852,6 +4908,8 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, = uint64_t s1, \ uint32_t vma =3D vext_vma(desc); = \ uint32_t i; = \ = \ + VSTART_CHECK_EARLY_EXIT(env); = \ + = \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { = \ /* set masked-off elements to 1s */ = \ @@ -4901,6 +4959,8 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0= , uint64_t s1, \ uint32_t vma =3D vext_vma(desc); = \ uint32_t i; = \ = \ + VSTART_CHECK_EARLY_EXIT(env); = \ + = \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { = \ /* set masked-off elements to 1s */ = \ @@ -4976,6 +5036,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint64_t index; \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ /* set masked-off elements to 1s */ \ @@ -5019,6 +5081,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint64_t index =3D s1; = \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ /* set masked-off elements to 1s */ \ @@ -5113,6 +5177,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ + VSTART_CHECK_EARLY_EXIT(env); \ + \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ /* set masked-off elements to 1s */ \ diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internal= s.c index 12f5964fbb..996c21eb31 100644 --- a/target/riscv/vector_internals.c +++ b/target/riscv/vector_internals.c @@ -44,6 +44,8 @@ void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, uint32_t vma =3D vext_vma(desc); uint32_t i; =20 + VSTART_CHECK_EARLY_EXIT(env); + for (i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { /* set masked-off elements to 1s */ @@ -68,6 +70,8 @@ void do_vext_vx(void *vd, void *v0, target_long s1, void = *vs2, uint32_t vma =3D vext_vma(desc); uint32_t i; =20 + VSTART_CHECK_EARLY_EXIT(env); + for (i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { /* set masked-off elements to 1s */ --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711098112; cv=none; d=zohomail.com; s=zohoarc; b=Vue4b7setczGLpXlSg2ovLvt6NsZU7IF5FTWl0s4Y0umz+Vq0gMTz32OhW/kCq8zrVqeh9sBAmOjxq7ntGZ52n1iLwkTYuMnjbmvQWBrcbDkJOny5Gi6ta6bXIfIBl3xqsrYxukhXD4QCsKzPgoChFSYNCKLEAEPLsNcfsytN88= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711098112; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lzkJtzrD2AZguEnLS9WQcNcwiid6ehuxGtzXZnitJe4=; b=UXMzsA0dsSylVajhE5pSaTITcB4l2RGRuT8NSMZYPqnosK1RAZyQU2n1HdvDVDuFNCE6OojREGGhSFpCLgdze6QDqEwJNoPaRDVvpr2vjwyri9Tp+MRddHNIkE0A1OGIPALaaHvOF2aOETMKR7G4mBG+O6dPR1RFViYVZaYp+yY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711098112200333.4009459491674; Fri, 22 Mar 2024 02:01:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnamU-0004Qt-17; Fri, 22 Mar 2024 05:01:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnam3-00044E-7h for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:01:18 -0400 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnals-0002Ir-I1 for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:01:07 -0400 Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6e682dbd84bso1074611a34.0 for ; Fri, 22 Mar 2024 02:01:04 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.53.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:53:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711098063; x=1711702863; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lzkJtzrD2AZguEnLS9WQcNcwiid6ehuxGtzXZnitJe4=; b=f1/O59xpDS4zk7rA0tzHAdf1xLmUhj2xlBzqg4acmk8fpnCXZAN2lUy/Pj5gi+ztqL DpA7AIm1nRhQ7Ho9LBjls1e5vmHORzp1Qizvm3FMaE5VblqT6bH9ni4CzQvXNHMe4oTv ctLOZzrvceke5ffiFQrHdog9/6Hoe/SwFxsNjdYBrtDQRPlZ9xuScNfmdRMXi8/oSj7g dOHrDtixEqtQ10itnweBQw3fqr2ULwRy+OY05RdP2XZC4wXa/JKvWK+qUoleCVsunzJ6 SV7LAciOYyBwLMrkcEvwSEyMtBWAi7XeS/ijpvxuU2n+HTlcaE2Xp6X/Rk0SQ6rlCkG/ 4c1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711098063; x=1711702863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lzkJtzrD2AZguEnLS9WQcNcwiid6ehuxGtzXZnitJe4=; b=rpPBGLUfZ6Uipa0DqkM8Rt0MWA/bStcncU9+j/U8M3XjT/6kwPOAu3G2WYpruLdEKR rOWpIh+Frcp8rcaZUr+eKHcL47B2S0gt1rY+nTIsj63MyipMApinQVGSC6v6mu5sC96Q QK9znc/2SVc57/+aL9daXEX58wjVafkzof1PdzbMZvRXfaulP+mBiOPpsKgbJaw5xLSf sUhpFUjqhxoPWTxYW7lT7k8zIAckUeyAKeRwDuBY5+aigOUfJGmAtUe1czL95cBfU3pJ aDEvL0Or4ZwbBEuig94HHbkZdNzkeFiyJsWFzm1dgZNSGaGz55bTCbC8tVvbLH51NtBP A9hw== X-Gm-Message-State: AOJu0YxWmkdw8AlDBd78IJZv1heqv8MkCYyNEJRZ/9n/0VFEH7XcDA7O pJpeLZnm5vXVq0/IPWRGrIC4QFApY0fltSreG96jXMzKq/ui1bas9RFt+waGlsNMMA== X-Google-Smtp-Source: AGHT+IHwqv/deqV5zgpjCzyHMjJ+ZTFkX/ftR4m6i8LpO3G7q5qpZxxK0apbaD4mZdKV/hPbE+phIw== X-Received: by 2002:a05:6a21:789d:b0:1a3:5090:7268 with SMTP id bf29-20020a056a21789d00b001a350907268mr2219119pzc.47.1711097636249; Fri, 22 Mar 2024 01:53:56 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Richard Henderson , Alistair Francis Subject: [PULL 08/15] target/riscv: remove 'over' brconds from vector trans Date: Fri, 22 Mar 2024 18:53:12 +1000 Message-ID: <20240322085319.1758843-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=alistair23@gmail.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711098114021100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza All helpers that rely on vstart >=3D vl are now doing early exits using the VSTART_CHECK_EARLY_EXIT() macro. This macro will not only exit the helper but also clear vstart. We're still left with brconds that are skipping the helper, which is the only place where we're clearing vstart. The pattern goes like this: tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); (... calls helper that clears vstart ...) gen_set_label(over); return true; This means that every time we jump to 'over' we're not clearing vstart, which is an oversight that we're doing across the board. Instead of setting vstart =3D 0 manually after each 'over' jump, remove those brconds that are skipping helpers. The exception will be trans_vmv_s_x() and trans_vfmv_s_f(): they don't use a helper and are already clearing vstart manually in the 'over' label. While we're at it, remove the (vl =3D=3D 0) brconds from trans_rvbf16.c.inc too since they're unneeded. Suggested-by: Richard Henderson Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20240314175704.478276-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvbf16.c.inc | 12 --- target/riscv/insn_trans/trans_rvv.c.inc | 99 ---------------------- target/riscv/insn_trans/trans_rvvk.c.inc | 18 ---- 3 files changed, 129 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn= _trans/trans_rvbf16.c.inc index 8ee99df3f3..a842e76a6b 100644 --- a/target/riscv/insn_trans/trans_rvbf16.c.inc +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc @@ -71,11 +71,8 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, ar= g_vfncvtbf16_f_f_w *a) =20 if (opfv_narrow_check(ctx, a) && (ctx->sew =3D=3D MO_16)) { uint32_t data =3D 0; - TCGLabel *over =3D gen_new_label(); =20 gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, ctx->lmul); @@ -87,7 +84,6 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg= _vfncvtbf16_f_f_w *a) ctx->cfg_ptr->vlenb, data, gen_helper_vfncvtbf16_f_f_w); mark_vs_dirty(ctx); - gen_set_label(over); return true; } return false; @@ -100,11 +96,8 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, a= rg_vfwcvtbf16_f_f_v *a) =20 if (opfv_widen_check(ctx, a) && (ctx->sew =3D=3D MO_16)) { uint32_t data =3D 0; - TCGLabel *over =3D gen_new_label(); =20 gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, ctx->lmul); @@ -116,7 +109,6 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, a= rg_vfwcvtbf16_f_f_v *a) ctx->cfg_ptr->vlenb, data, gen_helper_vfwcvtbf16_f_f_v); mark_vs_dirty(ctx); - gen_set_label(over); return true; } return false; @@ -130,11 +122,8 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, ar= g_vfwmaccbf16_vv *a) if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew =3D=3D MO= _16) && vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) { uint32_t data =3D 0; - TCGLabel *over =3D gen_new_label(); =20 gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, ctx->lmul); @@ -147,7 +136,6 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg= _vfwmaccbf16_vv *a) ctx->cfg_ptr->vlenb, data, gen_helper_vfwmaccbf16_vv); mark_vs_dirty(ctx); - gen_set_label(over); return true; } return false; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 1366445e1f..7931fb2f3f 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -616,9 +616,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, TCGv base; TCGv_i32 desc; =20 - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); - dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); base =3D get_gpr(s, rs1, EXT_NONE); @@ -660,7 +657,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } =20 - gen_set_label(over); return true; } =20 @@ -802,9 +798,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, TCGv base, stride; TCGv_i32 desc; =20 - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); - dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); base =3D get_gpr(s, rs1, EXT_NONE); @@ -819,7 +812,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, =20 fn(dest, mask, base, stride, tcg_env, desc); =20 - gen_set_label(over); return true; } =20 @@ -906,9 +898,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,= uint32_t vs2, TCGv base; TCGv_i32 desc; =20 - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); - dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); index =3D tcg_temp_new_ptr(); @@ -924,7 +913,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,= uint32_t vs2, =20 fn(dest, mask, base, index, tcg_env, desc); =20 - gen_set_label(over); return true; } =20 @@ -1044,9 +1032,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uin= t32_t data, TCGv base; TCGv_i32 desc; =20 - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); - dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); base =3D get_gpr(s, rs1, EXT_NONE); @@ -1059,7 +1044,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uin= t32_t data, fn(dest, mask, base, tcg_env, desc); =20 mark_vs_dirty(s); - gen_set_label(over); return true; } =20 @@ -1189,10 +1173,6 @@ static inline bool do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn, gen_helper_gvec_4_ptr *fn) { - TCGLabel *over =3D gen_new_label(); - - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1), @@ -1210,7 +1190,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3F= n *gvec_fn, s->cfg_ptr->vlenb, data, fn); } mark_vs_dirty(s); - gen_set_label(over); return true; } =20 @@ -1242,9 +1221,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, uint32_t vm, TCGv_i32 desc; uint32_t data =3D 0; =20 - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); - dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); @@ -1265,7 +1241,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, uint32_t vm, fn(dest, mask, src1, src2, tcg_env, desc); =20 mark_vs_dirty(s); - gen_set_label(over); return true; } =20 @@ -1404,9 +1379,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, TCGv_i32 desc; uint32_t data =3D 0; =20 - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); - dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); @@ -1427,7 +1399,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, fn(dest, mask, src1, src2, tcg_env, desc); =20 mark_vs_dirty(s); - gen_set_label(over); return true; } =20 @@ -1489,8 +1460,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, { if (checkfn(s, a)) { uint32_t data =3D 0; - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -1503,7 +1472,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, s->cfg_ptr->vlenb, data, fn); mark_vs_dirty(s); - gen_set_label(over); return true; } return false; @@ -1565,8 +1533,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, { if (opiwv_widen_check(s, a)) { uint32_t data =3D 0; - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -1578,7 +1544,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, tcg_env, s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fn); mark_vs_dirty(s); - gen_set_label(over); return true; } return false; @@ -1637,8 +1602,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, ui= nt32_t vs2, uint32_t vm, gen_helper_gvec_4_ptr *fn, DisasContext *s) { uint32_t data =3D 0; - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -1649,7 +1612,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, ui= nt32_t vs2, uint32_t vm, vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fn); mark_vs_dirty(s); - gen_set_label(over); return true; } =20 @@ -1828,8 +1790,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, \ }; \ - TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ @@ -1842,7 +1802,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ s->cfg_ptr->vlenb, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ - gen_set_label(over); \ return true; \ } \ return false; \ @@ -2039,14 +1998,11 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_= v_v *a) gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h, gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d, }; - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), tcg_env, s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fns[s->sew]); - gen_set_label(over); } mark_vs_dirty(s); return true; @@ -2062,8 +2018,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) /* vmv.v.x has rs2 =3D 0 and vm =3D 1 */ vext_check_ss(s, a->rd, 0, 1)) { TCGv s1; - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 s1 =3D get_gpr(s, a->rs1, EXT_SIGN); =20 @@ -2096,7 +2050,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) } =20 mark_vs_dirty(s); - gen_set_label(over); return true; } return false; @@ -2123,8 +2076,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, }; - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 s1 =3D tcg_constant_i64(simm); dest =3D tcg_temp_new_ptr(); @@ -2134,7 +2085,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) fns[s->sew](dest, s1, tcg_env, desc); =20 mark_vs_dirty(s); - gen_set_label(over); } return true; } @@ -2269,9 +2219,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_w, \ gen_helper_##NAME##_d, \ }; \ - TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ @@ -2286,7 +2234,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ s->cfg_ptr->vlenb, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ - gen_set_label(over); \ return true; \ } \ return false; \ @@ -2304,9 +2251,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, TCGv_i32 desc; TCGv_i64 t1; =20 - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); - dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); @@ -2324,7 +2268,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, fn(dest, mask, t1, src2, tcg_env, desc); =20 mark_vs_dirty(s); - gen_set_label(over); return true; } =20 @@ -2387,9 +2330,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ static gen_helper_gvec_4_ptr * const fns[2] =3D { \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ - TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ @@ -2402,7 +2343,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ s->cfg_ptr->vlenb, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ - gen_set_label(over); \ return true; \ } \ return false; \ @@ -2461,9 +2401,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ static gen_helper_gvec_4_ptr * const fns[2] =3D { \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ - TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ @@ -2476,7 +2414,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ s->cfg_ptr->vlenb, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ - gen_set_label(over); \ return true; \ } \ return false; \ @@ -2578,9 +2515,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, { if (checkfn(s, a)) { uint32_t data =3D 0; - TCGLabel *over =3D gen_new_label(); gen_set_rm_chkfrm(s, rm); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -2591,7 +2526,6 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fn); mark_vs_dirty(s); - gen_set_label(over); return true; } return false; @@ -2690,8 +2624,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, }; - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 t1 =3D tcg_temp_new_i64(); /* NaN-box f[rs1] */ @@ -2705,7 +2637,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) fns[s->sew - 1](dest, t1, tcg_env, desc); =20 mark_vs_dirty(s); - gen_set_label(over); } return true; } @@ -2767,9 +2698,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ gen_helper_##HELPER##_h, \ gen_helper_##HELPER##_w, \ }; \ - TCGLabel *over =3D gen_new_label(); \ gen_set_rm_chkfrm(s, FRM); \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ @@ -2781,7 +2710,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ s->cfg_ptr->vlenb, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ - gen_set_label(over); \ return true; \ } \ return false; \ @@ -2818,9 +2746,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, \ }; \ - TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ @@ -2832,7 +2758,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ s->cfg_ptr->vlenb, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ - gen_set_label(over); \ return true; \ } \ return false; \ @@ -2885,9 +2810,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ gen_helper_##HELPER##_h, \ gen_helper_##HELPER##_w, \ }; \ - TCGLabel *over =3D gen_new_label(); \ gen_set_rm_chkfrm(s, FRM); \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ @@ -2899,7 +2822,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ s->cfg_ptr->vlenb, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ - gen_set_label(over); \ return true; \ } \ return false; \ @@ -2934,9 +2856,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ gen_helper_##HELPER##_h, \ gen_helper_##HELPER##_w, \ }; \ - TCGLabel *over =3D gen_new_label(); \ gen_set_rm_chkfrm(s, FRM); \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ @@ -2948,7 +2868,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ s->cfg_ptr->vlenb, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ - gen_set_label(over); \ return true; \ } \ return false; \ @@ -3025,8 +2944,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) = \ vext_check_isa_ill(s)) { \ uint32_t data =3D 0; \ gen_helper_gvec_4_ptr *fn =3D gen_helper_##NAME; \ - TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D \ @@ -3037,7 +2954,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) = \ s->cfg_ptr->vlenb, \ s->cfg_ptr->vlenb, data, fn); \ mark_vs_dirty(s); \ - gen_set_label(over); \ return true; \ } \ return false; \ @@ -3125,8 +3041,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ s->vstart_eq_zero) { \ uint32_t data =3D 0; \ gen_helper_gvec_3_ptr *fn =3D gen_helper_##NAME; \ - TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ @@ -3139,7 +3053,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ s->cfg_ptr->vlenb, \ data, fn); \ mark_vs_dirty(s); \ - gen_set_label(over); \ return true; \ } \ return false; \ @@ -3165,8 +3078,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_= m *a) require_align(a->rd, s->lmul) && s->vstart_eq_zero) { uint32_t data =3D 0; - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -3181,7 +3092,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_= m *a) s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fns[s->sew]); mark_vs_dirty(s); - gen_set_label(over); return true; } return false; @@ -3195,8 +3105,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) require_align(a->rd, s->lmul) && require_vm(a->vm, a->rd)) { uint32_t data =3D 0; - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -3211,7 +3119,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) s->cfg_ptr->vlenb, data, fns[s->sew]); mark_vs_dirty(s); - gen_set_label(over); return true; } return false; @@ -3624,8 +3531,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r= *a) gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h, gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d, }; - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); @@ -3635,7 +3540,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r= *a) s->cfg_ptr->vlenb, data, fns[s->sew]); mark_vs_dirty(s); - gen_set_label(over); return true; } return false; @@ -3689,8 +3593,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, u= int8_t seq) { uint32_t data =3D 0; gen_helper_gvec_3_ptr *fn; - TCGLabel *over =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 static gen_helper_gvec_3_ptr * const fns[6][4] =3D { { @@ -3735,7 +3637,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, u= int8_t seq) s->cfg_ptr->vlenb, data, fn); =20 mark_vs_dirty(s); - gen_set_label(over); return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index a5cdd1b67f..6d640e4596 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -164,8 +164,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_che= ck) gen_helper_##NAME##_w, = \ gen_helper_##NAME##_d, = \ }; = \ - TCGLabel *over =3D gen_new_label(); = \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); = \ = \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ @@ -177,7 +175,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_che= ck) s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, = \ data, fns[s->sew]); = \ mark_vs_dirty(s); = \ - gen_set_label(over); = \ return true; = \ } = \ return false; = \ @@ -249,14 +246,12 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vws= ll_vx_check) TCGv_ptr rd_v, rs2_v; = \ TCGv_i32 desc, egs; = \ uint32_t data =3D 0; = \ - TCGLabel *over =3D gen_new_label(); = \ = \ if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { = \ /* save opcode for unwinding in case we throw an exception= */ \ decode_save_opc(s); = \ egs =3D tcg_constant_i32(EGS); = \ gen_helper_egs_check(egs, tcg_env); = \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);= \ } = \ = \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ @@ -272,7 +267,6 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll= _vx_check) tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); = \ gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); = \ mark_vs_dirty(s); = \ - gen_set_label(over); = \ return true; = \ } = \ return false; = \ @@ -325,14 +319,12 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED= _EGS) TCGv_ptr rd_v, rs2_v; = \ TCGv_i32 uimm_v, desc, egs; = \ uint32_t data =3D 0; = \ - TCGLabel *over =3D gen_new_label(); = \ = \ if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { = \ /* save opcode for unwinding in case we throw an exception= */ \ decode_save_opc(s); = \ egs =3D tcg_constant_i32(EGS); = \ gen_helper_egs_check(egs, tcg_env); = \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);= \ } = \ = \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ @@ -350,7 +342,6 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_E= GS) tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); = \ gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); = \ mark_vs_dirty(s); = \ - gen_set_label(over); = \ return true; = \ } = \ return false; = \ @@ -394,7 +385,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED= _EGS) { = \ if (CHECK(s, a)) { = \ uint32_t data =3D 0; = \ - TCGLabel *over =3D gen_new_label(); = \ TCGv_i32 egs; = \ = \ if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { = \ @@ -402,7 +392,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED= _EGS) decode_save_opc(s); = \ egs =3D tcg_constant_i32(EGS); = \ gen_helper_egs_check(egs, tcg_env); = \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);= \ } = \ = \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ @@ -417,7 +406,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED= _EGS) data, gen_helper_##NAME); = \ = \ mark_vs_dirty(s); = \ - gen_set_label(over); = \ return true; = \ } = \ return false; = \ @@ -448,7 +436,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr = *a) { if (vsha_check(s, a)) { uint32_t data =3D 0; - TCGLabel *over =3D gen_new_label(); TCGv_i32 egs; =20 if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { @@ -456,7 +443,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr = *a) decode_save_opc(s); egs =3D tcg_constant_i32(ZVKNH_EGS); gen_helper_egs_check(egs, tcg_env); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); } =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -472,7 +458,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr = *a) gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv); =20 mark_vs_dirty(s); - gen_set_label(over); return true; } return false; @@ -482,7 +467,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr = *a) { if (vsha_check(s, a)) { uint32_t data =3D 0; - TCGLabel *over =3D gen_new_label(); TCGv_i32 egs; =20 if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { @@ -490,7 +474,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr = *a) decode_save_opc(s); egs =3D tcg_constant_i32(ZVKNH_EGS); gen_helper_egs_check(egs, tcg_env); - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); } =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -506,7 +489,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr = *a) gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv); =20 mark_vs_dirty(s); - gen_set_label(over); return true; } return false; --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711097664; cv=none; d=zohomail.com; s=zohoarc; b=W+Pi2WgNMHxQJBXZmFAlR5XeJ/5wpqJl1zIoOnLonejM71HM8VZo4GG1r7rhKASTvFTq+oHgncvsV3oTJzGEk5B9+G1w6t8qRZ2S5VnzQDrlQbxex4CaRSD058rtu+UkwCPmDdVwlsxxpgAjzsfIamI1q2l6b55gJqcA37mY8EA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711097664; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wWvKppuqYrGsgdS9wSeB9R/qpdaidAtK5C4zNP5nZZA=; b=UzaaW6zPKcckwktM5fViAjJ2w/zJlUy+SI4E1cusPe907hzehqy1FZ6EPJA8kv8PsKqzmeqT1mO2Bf8592rm5xRPZDqhiKhYsIy5nUsit2R50RbTx/XkvtlaNzbbNKZYXtycqk7Fc/RfpUDNL/0wYU8Vp3pBsw852dLBfoJuWdU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711097664399627.930421768492; Fri, 22 Mar 2024 01:54:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnaf7-00040K-U4; Fri, 22 Mar 2024 04:54:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnaf5-0003xF-Fk for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:54:03 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnaf3-00011F-U9 for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:54:03 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1dff837d674so14950935ad.3 for ; Fri, 22 Mar 2024 01:54:01 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.53.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:53:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711097640; x=1711702440; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wWvKppuqYrGsgdS9wSeB9R/qpdaidAtK5C4zNP5nZZA=; b=bDKz51yG0hOwu5+WSY4qG6IYG8AbFkKm3W6KFiWjOlq5eNExgexsI2KlK0oAAo7pmI XQvd9LwnisPh36iK+kxa0FcQHPTICQ5ehfLaw3iR1Za+B2llnyvA3db7oPqd5zDIleTj i81Gy3q6FBNzSY30YFr9aV0O4FTWfVLcImlLU2UrpponHKsR4EDoVkwYHXXAkkyNurDD 457f3fZoJ/Ixy6LMoqHu+530C5k7dseGCzTML/F4g0pX2KIayxY5Z6VqrxnhR9YVMbVG mjIIXCSm3sF/cmocK/u6kdRMgIV06G0HIylm68SN411H/JEwWK2dKzTkSoOS63meStLH fTYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711097640; x=1711702440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wWvKppuqYrGsgdS9wSeB9R/qpdaidAtK5C4zNP5nZZA=; b=crxuQui4I1RFGS1ilcKtyojF4FppCVLMdsEGRhTZwZmNlOb8ZcjOEg6bjweJuSEnJL LoZDNDSUTuamtccbmXYjLShg5HIwms9wm7LucZd4zvzuW2LkZ+LG8ZRKV621ePTfjZin T1OuEwvfzOpa5x401Ne2tzNA6IlqWEEJLnn1MGcw1kaqhMHc5aNXw6MyVnj6pMIwHZFp lO3lsblyDTOHPcWsg8bKDQsrLNZdCWbohB68A1XyqRksPyyEG/SgL2a9qyY2ecyNkVZe Mkge4TuUJvBNALaJPZbg99LXZ+5/3Xq5qH2VfKA4SY7HxzTrdlCqUj7BG2FEKpS81aeg PKFA== X-Gm-Message-State: AOJu0Yyb48T/27NYzcijdL5WyuQLcvVlY54D0QoRCR/UTcbx0Roe1s59 ItvkXR+QI94K6IE3ysvEkxA5a9KtcZEwH27Z+FWRBSwyHSsNc4joOzKAGPGT89PhBA== X-Google-Smtp-Source: AGHT+IHwfKE7UJy/io8A9/WoYhVqJIA4aAgNzdojtA8wVpPjmoXZZSnZ+I0R6jz/KuLO3SyOnG37Pg== X-Received: by 2002:a17:903:11c4:b0:1e0:64bd:51ac with SMTP id q4-20020a17090311c400b001e064bd51acmr2165727plh.22.1711097640023; Fri, 22 Mar 2024 01:54:00 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Richard Henderson , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 09/15] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Date: Fri, 22 Mar 2024 18:53:13 +1000 Message-ID: <20240322085319.1758843-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711097664658100001 From: Daniel Henrique Barboza trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of their 'ifs'. conditionals. Call it just once in the end like other functions are doing. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20240314175704.478276-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 7931fb2f3f..401ee939b8 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2065,7 +2065,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), simm); - mark_vs_dirty(s); } else { TCGv_i32 desc; TCGv_i64 s1; @@ -2083,9 +2082,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) s->cfg_ptr->vlenb, data)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1, tcg_env, desc); - - mark_vs_dirty(s); } + mark_vs_dirty(s); return true; } return false; @@ -2612,7 +2610,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) =20 tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), t1); - mark_vs_dirty(s); } else { TCGv_ptr dest; TCGv_i32 desc; @@ -2635,9 +2632,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd)); =20 fns[s->sew - 1](dest, t1, tcg_env, desc); - - mark_vs_dirty(s); } + mark_vs_dirty(s); return true; } return false; @@ -3560,12 +3556,11 @@ static bool trans_##NAME(DisasContext *s, arg_##NAM= E * a) \ if (s->vstart_eq_zero) { \ tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), \ vreg_ofs(s, a->rs2), maxsz, maxsz); \ - mark_vs_dirty(s); \ } else { \ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \ tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v= ); \ - mark_vs_dirty(s); \ } \ + mark_vs_dirty(s); \ return true; \ } \ return false; \ --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711098055; cv=none; d=zohomail.com; s=zohoarc; b=jnBTGH7tL6+oNlipen14xx4syFwau3DcVVCl2orCBjM/FLJqLu1HRiQKlRJbH8rcqwimxaT6rWxd0c1DSfV9fZgApGiuGnY99VeUr1O71KEdiBx9Bu5eoMbwkGr3vCuzq2w5aJZ61gNbjE0hi1qPALFVGGkpCccq3exKO7NnV48= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711098055; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cJdnSS4KFv/eLevUHZVNJQnW4+egP8pig8yKDZGXOck=; b=NL8SYSGNy4b2i4Zi+XyzzI7lKg6iAi0hDa0SsAyj6anLt90XP+38oFpNmlwqNsPwSO0e96Vn1LJMGTxrpCdaZQQo3e0lHvBWScPR8rg1gi7pPDH0kBgZjcz84VoqB5I8+fylU0v5uxlQlkHReOHEvwzbQ6dhsifzImWItJQGqIo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711098055283579.4291839828834; Fri, 22 Mar 2024 02:00:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnalO-0001Xc-UA; Fri, 22 Mar 2024 05:00:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnalN-0001X2-La for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:00:33 -0400 Received: from mail-qk1-x734.google.com ([2607:f8b0:4864:20::734]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnalK-0002Ev-WC for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:00:33 -0400 Received: by mail-qk1-x734.google.com with SMTP id af79cd13be357-789db917876so118753085a.1 for ; Fri, 22 Mar 2024 02:00:30 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.54.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:54:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711098029; x=1711702829; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cJdnSS4KFv/eLevUHZVNJQnW4+egP8pig8yKDZGXOck=; b=ZX8+k7wDw81kbZB1G3k2EGMdY7pJ5viPTkkZTC82fR1daYwF6JVZUjN+Fudx50fDBY 8RaDI2gV35vnhKY964Yy4Js8FPGUxd/G3EIgedP019HatWJk9V3695DdZtu5D8gG7QUO P9ekTIjTEaAoU5Soi3H0nS8XNCN8em4yiwmJlagjEY54Mu6SjzustnMA6VN8598wcyAo 4gCXG9DFBdd1q/IOgjyfqaUcOdXlgnyFAupfrabQmGrOQLwDFB5ap7SamFpUMC4VDWuC 2RnmTSq1bun5QOFeGo+t4TM/5aP9e3ZyqP2dNGGZLOukiXjIZuVJPSoawOzHgjRWSOl4 XjEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711098029; x=1711702829; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cJdnSS4KFv/eLevUHZVNJQnW4+egP8pig8yKDZGXOck=; b=e7I5zhNZ9y6fq+T5or1ZwmRddFn8srE6tgM0PDkVIMuCKEhO92mxpD64xXeahD7xvY ivqe9uEIxGsmT0ZqvLoSWkb6SkQhz8vXNelPHMKpfh6quh/zXRgfPvm+UHiaRlKcmUE8 uYZ/lqW2yafWHyj9WqQjjUL1NZ5PFtj01yEGFL3pJF/3zXgVXGwxji16VYzLLNuuxPbf jN307SszKbAm6Ro86rqbizwrTOfV7Q+jVxI0kHYMwcrpHnD8Zn/ARCjL4RZyky3dktRR ZF8UIzBHG0zSGVmpZmxNq87UZ2z248V5OkzZ88MRGXwd+slLVsnYPZKIYwKqpYw+DmTN Z8PA== X-Gm-Message-State: AOJu0YzL0NRmI8rQOBQii4+cyxx69GlW0RUYIkjT1hW6k/x6yAJmZKZv XRfruPvdQYiuHv1qUsWawYwzfVYkzp055jGFO4JN/QBRc3jB7xmwDPh9WR2aP7JiZg== X-Google-Smtp-Source: AGHT+IFo49HKmug5ZaPJZnaR7/agj3zpi17lEUjNJM7AvyX+6o9BI3aGxNDeg+9DLznYP/hbDP1O2Q== X-Received: by 2002:a05:6a20:2d2c:b0:1a3:6f26:6b83 with SMTP id g44-20020a056a202d2c00b001a36f266b83mr2519286pzl.46.1711097643858; Fri, 22 Mar 2024 01:54:03 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Ivan Klokov , Daniel Henrique Barboza , Richard Henderson , Alistair Francis Subject: [PULL 10/15] target/riscv: enable 'vstart_eq_zero' in the end of insns Date: Fri, 22 Mar 2024 18:53:14 +1000 Message-ID: <20240322085319.1758843-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::734; envelope-from=alistair23@gmail.com; helo=mail-qk1-x734.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711098055885100001 Content-Type: text/plain; charset="utf-8" From: Ivan Klokov The vstart_eq_zero flag is updated at the beginning of the translation phase from the env->vstart variable. During the execution phase all functions will set env->vstart =3D 0 after a successful execution, but the vstart_eq_zero flag remains the same as at the start of the block. This will wrongly cause SIGILLs in translations that requires env->vstart =3D 0 and might be reading vstart_eq_zero =3D false. This patch adds a new finalize_rvv_inst() helper that is called at the end of each vector instruction that will both update vstart_eq_zero and do a mark_vs_dirty(). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976 Signed-off-by: Ivan Klokov Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20240314175704.478276-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 6 ++ target/riscv/insn_trans/trans_rvbf16.c.inc | 6 +- target/riscv/insn_trans/trans_rvv.c.inc | 83 ++++++++++++---------- target/riscv/insn_trans/trans_rvvk.c.inc | 12 ++-- 4 files changed, 59 insertions(+), 48 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ea5d52b2ef..9d57089fcc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -676,6 +676,12 @@ static void mark_vs_dirty(DisasContext *ctx) static inline void mark_vs_dirty(DisasContext *ctx) { } #endif =20 +static void finalize_rvv_inst(DisasContext *ctx) +{ + mark_vs_dirty(ctx); + ctx->vstart_eq_zero =3D true; +} + static void gen_set_rm(DisasContext *ctx, int rm) { if (ctx->frm =3D=3D rm) { diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn= _trans/trans_rvbf16.c.inc index a842e76a6b..0a9cd1ec31 100644 --- a/target/riscv/insn_trans/trans_rvbf16.c.inc +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc @@ -83,7 +83,7 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg= _vfncvtbf16_f_f_w *a) ctx->cfg_ptr->vlenb, ctx->cfg_ptr->vlenb, data, gen_helper_vfncvtbf16_f_f_w); - mark_vs_dirty(ctx); + finalize_rvv_inst(ctx); return true; } return false; @@ -108,7 +108,7 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, a= rg_vfwcvtbf16_f_f_v *a) ctx->cfg_ptr->vlenb, ctx->cfg_ptr->vlenb, data, gen_helper_vfwcvtbf16_f_f_v); - mark_vs_dirty(ctx); + finalize_rvv_inst(ctx); return true; } return false; @@ -135,7 +135,7 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg= _vfwmaccbf16_vv *a) ctx->cfg_ptr->vlenb, ctx->cfg_ptr->vlenb, data, gen_helper_vfwmaccbf16_vv); - mark_vs_dirty(ctx); + finalize_rvv_inst(ctx); return true; } return false; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 401ee939b8..7d84e7d812 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -167,7 +167,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,= TCGv s2) =20 gen_helper_vsetvl(dst, tcg_env, s1, s2); gen_set_gpr(s, rd, dst); - mark_vs_dirty(s); + finalize_rvv_inst(s); =20 gen_update_pc(s, s->cur_insn_len); lookup_and_goto_ptr(s); @@ -187,7 +187,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s= 1, TCGv s2) =20 gen_helper_vsetvl(dst, tcg_env, s1, s2); gen_set_gpr(s, rd, dst); - mark_vs_dirty(s); + finalize_rvv_inst(s); gen_update_pc(s, s->cur_insn_len); lookup_and_goto_ptr(s); s->base.is_jmp =3D DISAS_NORETURN; @@ -657,6 +657,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } =20 + finalize_rvv_inst(s); return true; } =20 @@ -812,6 +813,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, =20 fn(dest, mask, base, stride, tcg_env, desc); =20 + finalize_rvv_inst(s); return true; } =20 @@ -913,6 +915,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,= uint32_t vs2, =20 fn(dest, mask, base, index, tcg_env, desc); =20 + finalize_rvv_inst(s); return true; } =20 @@ -1043,7 +1046,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uin= t32_t data, =20 fn(dest, mask, base, tcg_env, desc); =20 - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } =20 @@ -1100,6 +1103,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs= 1, uint32_t nf, =20 fn(dest, base, tcg_env, desc); =20 + finalize_rvv_inst(s); return true; } =20 @@ -1189,7 +1193,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3F= n *gvec_fn, tcg_env, s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fn); } - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } =20 @@ -1240,7 +1244,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, uint32_t vm, =20 fn(dest, mask, src1, src2, tcg_env, desc); =20 - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } =20 @@ -1265,7 +1269,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2s= Fn *gvec_fn, gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), src1, MAXSZ(s), MAXSZ(s)); =20 - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); @@ -1398,7 +1402,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, =20 fn(dest, mask, src1, src2, tcg_env, desc); =20 - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } =20 @@ -1412,7 +1416,7 @@ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2i= Fn *gvec_fn, if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s)); - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, imm_mode); @@ -1471,7 +1475,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, tcg_env, s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fn); - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -1543,7 +1547,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fn); - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -1611,7 +1615,7 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, ui= nt32_t vs2, uint32_t vm, tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1), vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fn); - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } =20 @@ -1744,7 +1748,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVe= cGen2sFn32 *gvec_fn, gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), src1, MAXSZ(s), MAXSZ(s)); =20 - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); @@ -1801,7 +1805,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ s->cfg_ptr->vlenb, \ s->cfg_ptr->vlenb, data, \ fns[s->sew]); \ - mark_vs_dirty(s); \ + finalize_rvv_inst(s); \ return true; \ } \ return false; \ @@ -2004,7 +2008,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_= v *a) s->cfg_ptr->vlenb, data, fns[s->sew]); } - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -2049,7 +2053,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) fns[s->sew](dest, s1_i64, tcg_env, desc); } =20 - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -2083,7 +2087,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1, tcg_env, desc); } - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -2231,7 +2235,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ s->cfg_ptr->vlenb, \ s->cfg_ptr->vlenb, data, \ fns[s->sew - 1]); \ - mark_vs_dirty(s); \ + finalize_rvv_inst(s); \ return true; \ } \ return false; \ @@ -2265,7 +2269,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, =20 fn(dest, mask, t1, src2, tcg_env, desc); =20 - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } =20 @@ -2340,7 +2344,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ s->cfg_ptr->vlenb, \ s->cfg_ptr->vlenb, data, \ fns[s->sew - 1]); \ - mark_vs_dirty(s); \ + finalize_rvv_inst(s); \ return true; \ } \ return false; \ @@ -2411,7 +2415,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ s->cfg_ptr->vlenb, \ s->cfg_ptr->vlenb, data, \ fns[s->sew - 1]); \ - mark_vs_dirty(s); \ + finalize_rvv_inst(s); \ return true; \ } \ return false; \ @@ -2523,7 +2527,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fn); - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -2633,7 +2637,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) =20 fns[s->sew - 1](dest, t1, tcg_env, desc); } - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -2705,7 +2709,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ s->cfg_ptr->vlenb, \ s->cfg_ptr->vlenb, data, \ fns[s->sew - 1]); \ - mark_vs_dirty(s); \ + finalize_rvv_inst(s); \ return true; \ } \ return false; \ @@ -2753,7 +2757,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ s->cfg_ptr->vlenb, \ s->cfg_ptr->vlenb, data, \ fns[s->sew]); \ - mark_vs_dirty(s); \ + finalize_rvv_inst(s); \ return true; \ } \ return false; \ @@ -2817,7 +2821,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ s->cfg_ptr->vlenb, \ s->cfg_ptr->vlenb, data, \ fns[s->sew - 1]); \ - mark_vs_dirty(s); \ + finalize_rvv_inst(s); \ return true; \ } \ return false; \ @@ -2863,7 +2867,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ s->cfg_ptr->vlenb, \ s->cfg_ptr->vlenb, data, \ fns[s->sew]); \ - mark_vs_dirty(s); \ + finalize_rvv_inst(s); \ return true; \ } \ return false; \ @@ -2949,7 +2953,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) = \ vreg_ofs(s, a->rs2), tcg_env, \ s->cfg_ptr->vlenb, \ s->cfg_ptr->vlenb, data, fn); \ - mark_vs_dirty(s); \ + finalize_rvv_inst(s); \ return true; \ } \ return false; \ @@ -3048,7 +3052,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ tcg_env, s->cfg_ptr->vlenb, \ s->cfg_ptr->vlenb, \ data, fn); \ - mark_vs_dirty(s); \ + finalize_rvv_inst(s); \ return true; \ } \ return false; \ @@ -3087,7 +3091,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_= m *a) vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fns[s->sew]); - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -3114,7 +3118,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) tcg_env, s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fns[s->sew]); - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -3271,7 +3275,7 @@ static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_= s *a) tcg_gen_trunc_i64_tl(dest, t1); gen_set_gpr(s, a->rd, dest); tcg_gen_movi_tl(cpu_vstart, 0); - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -3300,7 +3304,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) vec_element_storei(s, a->rd, 0, t1); gen_set_label(over); tcg_gen_movi_tl(cpu_vstart, 0); - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -3328,7 +3332,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_= f_s *a) =20 mark_fs_dirty(s); tcg_gen_movi_tl(cpu_vstart, 0); - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -3354,9 +3358,10 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv= _s_f *a) do_nanbox(s, t1, cpu_fpr[a->rs1]); =20 vec_element_storei(s, a->rd, 0, t1); + gen_set_label(over); tcg_gen_movi_tl(cpu_vstart, 0); - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -3462,7 +3467,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rm= rr *a) =20 tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), dest); - mark_vs_dirty(s); + finalize_rvv_inst(s); } else { static gen_helper_opivx * const fns[4] =3D { gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, @@ -3490,7 +3495,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rm= rr *a) endian_ofs(s, a->rs2, a->rs1), MAXSZ(s), MAXSZ(s)); } - mark_vs_dirty(s); + finalize_rvv_inst(s); } else { static gen_helper_opivx * const fns[4] =3D { gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, @@ -3535,7 +3540,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r= *a) tcg_env, s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fns[s->sew]); - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -3560,7 +3565,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME = * a) \ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \ tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v= ); \ } \ - mark_vs_dirty(s); \ + finalize_rvv_inst(s); \ return true; \ } \ return false; \ @@ -3631,7 +3636,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, u= int8_t seq) s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, fn); =20 - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 6d640e4596..ae1f40174a 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -174,7 +174,7 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_che= ck) vreg_ofs(s, a->rs2), tcg_env, = \ s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, = \ data, fns[s->sew]); = \ - mark_vs_dirty(s); = \ + finalize_rvv_inst(s); = \ return true; = \ } = \ return false; = \ @@ -266,7 +266,7 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll= _vx_check) tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); = \ tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); = \ gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); = \ - mark_vs_dirty(s); = \ + finalize_rvv_inst(s); = \ return true; = \ } = \ return false; = \ @@ -341,7 +341,7 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_E= GS) tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); = \ tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); = \ gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); = \ - mark_vs_dirty(s); = \ + finalize_rvv_inst(s); = \ return true; = \ } = \ return false; = \ @@ -405,7 +405,7 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED= _EGS) s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, = \ data, gen_helper_##NAME); = \ = \ - mark_vs_dirty(s); = \ + finalize_rvv_inst(s); = \ return true; = \ } = \ return false; = \ @@ -457,7 +457,7 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr = *a) s->sew =3D=3D MO_32 ? gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv); =20 - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; @@ -488,7 +488,7 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr = *a) s->sew =3D=3D MO_32 ? gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv); =20 - mark_vs_dirty(s); + finalize_rvv_inst(s); return true; } return false; --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711098070; cv=none; d=zohomail.com; s=zohoarc; b=LetXEe0ku3Dbw6miCl3OjCtb5dJmD0ual6jw/HGVPc+Xmv60puDTwP5ULovB4MZG4vTK5W4D5E4BfbF0SNzX8p4gLn+OwXG0ZG1ZsCOr7JH7dp2A4ld6xdtDca7L7FzBQALtJ8uS2NGzBO76UFrbFIWy9z8DGofBeGWjzSXwwJY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711098070; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JFOwsLoUeHy61UpIhgty+6bsINYXEMHB7YYoX+Io5XM=; b=XLcP9r4NuwvVIF27V+m11LXT9ZA1ppVI60m5noZKoi7MfA1/7SEivuFOR4ho8hzqcV55b8jF3TCi9kHv96bsm0FgMbV2xyUeFoqgHm4ZOVzQBIeN6UlnxnRPu0GUq5qctOVET9KB2DiSHatVv2SwWRQg+VxYF1msNXfN0NiRilI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711098070873214.98305386645984; Fri, 22 Mar 2024 02:01:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnalE-0001Tj-Ps; Fri, 22 Mar 2024 05:00:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnalD-0001TW-7N for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:00:23 -0400 Received: from mail-yw1-x1131.google.com ([2607:f8b0:4864:20::1131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnalB-00029J-PS for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:00:22 -0400 Received: by mail-yw1-x1131.google.com with SMTP id 00721157ae682-609ff069a40so21235917b3.1 for ; Fri, 22 Mar 2024 02:00:21 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.54.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:54:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711098020; x=1711702820; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JFOwsLoUeHy61UpIhgty+6bsINYXEMHB7YYoX+Io5XM=; b=VHfce5NwZBw8a8vzgkYOjL8DvrrOQ4IhUk4TyIJug4xrwbMMK+YwWQiC9ZMzX5o6Ve yk9+4Ue9UIzGP87JM6M1R4sHAyeHuf0TqF9FZX6ZS1LQhzVPstNhAhNMuolJF9hb7Med UqPG120PTbQHe+29LsVvyjJM7F+9q79OKIIuePkEXMrIY82Kx/z3PcEVk9A2xPNh6ajl MzsRog1Bw3S9kIRAhRkfO4aGlXogOKZ39Pu99+iDzJzFQBYCO7eQ8bSASBGIau+znW1k 3QmEUukKxsVrNfQVxxaU02UAyDhZjxuqy713CaIY13WU0hUGM3AX1duCvxoP/n8UAZ5f zlsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711098020; x=1711702820; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JFOwsLoUeHy61UpIhgty+6bsINYXEMHB7YYoX+Io5XM=; b=GzenIBGhg2zDYCldva4ieoye3G1HD71JLl3DVO57zDrS052AI/9IxOwoE1GqIhiw+u yeYJvN2QOb8jgfv2nMAaLX4QBvpFcsfYEVT5pDf+yZaEkbjJA/hYfNZmaduSCWf+J+31 27jge9hmhiG0p5kKBp7xMu0YWD2D3l0lwrtybN0qWTP5dl0D/IOHjUiqecknBDAWasJy YtI4BKCCMYuEXTycIzBLQZhzqyGY9n6cFnCTovasRc7+2JfD3XZbpvTw+J1rVlAA7kYg HSirlZhdsp0KdX1triowvdK532Arta5kcFksRnl9gwT1/tLP1ZIQ3Lqr1TGi10IJFeCO FuMw== X-Gm-Message-State: AOJu0YwhKYe7563coj9AiIQvY0KSnl4W1/Rw3mWQla+2n6dEeWL54FYl G19cgCY4ajbWhMjoTQX7ffROoWFG09y8Gm05dlHOj809iH+Z5jEkQeIrEHawcjZ5Mw== X-Google-Smtp-Source: AGHT+IHn+f5j/qhYtuThW/7TrxJMVc2tQJ+O8bbPdtZkUWg3N127WYAui4gWoCGx+Sp68QXw545H/g== X-Received: by 2002:a05:6a20:2587:b0:1a3:a9ee:853a with SMTP id k7-20020a056a20258700b001a3a9ee853amr308102pzd.40.1711097647260; Fri, 22 Mar 2024 01:54:07 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Richard Henderson , Alistair Francis Subject: [PULL 11/15] target/riscv/vector_helper.c: optimize loops in ldst helpers Date: Fri, 22 Mar 2024 18:53:15 +1000 Message-ID: <20240322085319.1758843-12-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1131; envelope-from=alistair23@gmail.com; helo=mail-yw1-x1131.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711098071828100005 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Change the for loops in ldst helpers to do a single increment in the counter, and assign it env->vstart, to avoid re-reading from vstart every time. Suggested-by: Richard Henderson Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-ID: <20240314175704.478276-11-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 63a1083f03..fa139040f8 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -209,7 +209,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, =20 VSTART_CHECK_EARLY_EXIT(env); =20 - for (i =3D env->vstart; i < env->vl; i++, env->vstart++) { + for (i =3D env->vstart; i < env->vl; env->vstart =3D ++i) { k =3D 0; while (k < nf) { if (!vm && !vext_elem_mask(v0, i)) { @@ -277,7 +277,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, VSTART_CHECK_EARLY_EXIT(env); =20 /* load bytes from guest memory */ - for (i =3D env->vstart; i < evl; i++, env->vstart++) { + for (i =3D env->vstart; i < evl; env->vstart =3D ++i) { k =3D 0; while (k < nf) { target_ulong addr =3D base + ((i * nf + k) << log2_esz); @@ -393,7 +393,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, VSTART_CHECK_EARLY_EXIT(env); =20 /* load bytes from guest memory */ - for (i =3D env->vstart; i < env->vl; i++, env->vstart++) { + for (i =3D env->vstart; i < env->vl; env->vstart =3D ++i) { k =3D 0; while (k < nf) { if (!vm && !vext_elem_mask(v0, i)) { --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711097699; cv=none; d=zohomail.com; s=zohoarc; b=ZLiSUi3VTq0L7nQ6rQA6l7b1BkwgV1G+hWLsOpIvZtp+BNz9hUzmaxNJmPKo7Yvq3/q/j7N2xkmaojQLolpAzgS+knk0PYFIYk9fyhDI8+igeVUQszx/8wL9zR3TNeuQUxjYg71Xv4IxrDG8sJWdHnggEAVpVXSK7HpZd92+CDc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711097699; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gggN9oJqY5bBdrfB5/j/DAwZ/Z57rRd8F4t6/CMnQ6k=; b=C9xUSqu6dPYdaAdiZsHubJSV9kMJQkvzGuzsCN62UEa8L/VfMhcHO9NWHwtYixPNiUPLE7fkTOwDui7jQSXUPPPozWSpYRVlxQ/OyKUdPzMQIJFIinWZ7wHv2ozv1TsbVxJBfLqHus5VnJraYiqPCT+193HVzz20p361bcAF5bI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711097699430150.77539498204578; Fri, 22 Mar 2024 01:54:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnafH-0004J5-22; Fri, 22 Mar 2024 04:54:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnafF-0004FZ-Ro for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:54:13 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnafE-00011t-41 for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:54:13 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1dddad37712so15712665ad.3 for ; Fri, 22 Mar 2024 01:54:11 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.54.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:54:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711097650; x=1711702450; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gggN9oJqY5bBdrfB5/j/DAwZ/Z57rRd8F4t6/CMnQ6k=; b=Ao3eFCFLIXNv2Uj/pT/2TIPEx8t1r1K4Op7l+XyC35LkRbVB1wNCGKaqnKdhnnoC2m mHPic4cL4V/+NE4wzwXsMXJo6M1EYjyQlLCK3Q+yM9xeioswYSiNqpx5tIqL2H5Da2yl 957f41oMQOFTJU9gppCZNTHB34Xjr5CvdAxo15Si7WiiQw9oYGLK78GZquDGuGRG7jCe pvpTTxyGY0WVQQlWsBHPtiWGhBchY/8wWtVw1st1NpWdZkUjhQDXu4HwPMW8tJsd2H6E EZ7vHS3CC+tuQy7JI4HpXuziFL20MYZ8AsHKTldpxjbAJYyh6aKta4QPfJom8A57ofvg /WMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711097650; x=1711702450; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gggN9oJqY5bBdrfB5/j/DAwZ/Z57rRd8F4t6/CMnQ6k=; b=M29AlhEU6uVq9fzGR71EnbByFK4xG8czhSorDvYsjHWsherRzSRkdxfsxjiLCmlbg9 4jdDBdKD4mMTL+r1rfRkLiCVf54+07K9uwBKH5yOoICf/iV8YsI2q6i603nRHTL4njGa Cw12NX/nrZDSI6ST5025nIqHLvjVEoNewWtajNkTbza4l1x8QOo8Eq3+P2u8llcKkk1v 0tnp78yVO3xn2JLW1Qhtekly8iQGKJ1sRJseuuz0tcqiZoguBB49X20FXKBZM6UJTjv0 1Gcoh3yGFC36fQ7nsA1S/Dac0nwCTCCBf+9S7WMVhfv/M4c9Q+NO21hoi/mxJlJMwnEp rLEg== X-Gm-Message-State: AOJu0Yw2IpMXG7/A66MJKpYTvu9aA4Z4Kr2MN3snlSQZTWXry4h/ctwN wZkqjh23Uepe+6Hb6C5cqa3qGRYPBl7BhUcIdPfZZSinH9OI/9kPd1cHy6iOPezoxw== X-Google-Smtp-Source: AGHT+IEiuqoY3YgKcT+0OGq6dN7j3f4prsO+0GxfLfd/dAoamgkuCvNL/yF1ccWKE2UAA6K1rCXeDg== X-Received: by 2002:a17:902:d485:b0:1df:fa83:2cdf with SMTP id c5-20020a170902d48500b001dffa832cdfmr2268237plg.18.1711097650472; Fri, 22 Mar 2024 01:54:10 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Frank Chang , Jim Shu , Alistair Francis Subject: [PULL 12/15] hw/intc: Update APLIC IDC after claiming iforce register Date: Fri, 22 Mar 2024 18:53:16 +1000 Message-ID: <20240322085319.1758843-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711097700819100003 Content-Type: text/plain; charset="utf-8" From: Frank Chang Currently, QEMU only sets the iforce register to 0 and returns early when claiming the iforce register. However, this may leave mip.meip remains at 1 if a spurious external interrupt triggered by iforce register is the only pending interrupt to be claimed, and the interrupt cannot be lowered as expected. This commit fixes this issue by calling riscv_aplic_idc_update() to update the IDC status after the iforce register is claimed. Signed-off-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Alistair Francis Message-ID: <20240321104951.12104-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aplic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 6a7fbfa861..fc5df0d598 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -488,6 +488,7 @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState = *aplic, uint32_t idc) =20 if (!topi) { aplic->iforce[idc] =3D 0; + riscv_aplic_idc_update(aplic, idc); return 0; } =20 --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711097715; cv=none; d=zohomail.com; s=zohoarc; b=CtQUFm3XOocZzNIPYEJIo0EuUf+dcS5plfFaOR84sIC22nK79oIaFSSfzWMyi/13pccbf7Q+KeU85hhSVGG0wxlYNX6TU+h884q8Jfn0aHKv3PC3ny7V1/K9GJN5XDp0nNypaY/3T67byU2I6zyTQgbXUM4uT5OEsvnofMiircU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711097715; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SYRuYu6Nyn7zXJDQL50vurRoO71Bn8A9O+6ORi9MHIc=; b=WXeUrYZ5Y6PNm1jD5V6xd45Advb99TAnTymDfCaAqDdbC/+/AvQnmuRA+lAA7cjLITqBjrlOKsOQZivsne/Wm2SKxh6JDhTJKur535QE3261WpH8hi4hZS7E1b2icxusxMWaJ+3VkhRuiHg4zpBxzYtzrXbZlAYi2Xs67UwZNSo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711097715802867.7491366986267; Fri, 22 Mar 2024 01:55:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnafL-0004b3-7O; Fri, 22 Mar 2024 04:54:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnafI-0004ON-VL for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:54:17 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnafH-00012N-EL for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:54:16 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-6e709e0c123so1540232b3a.1 for ; Fri, 22 Mar 2024 01:54:15 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.54.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:54:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711097653; x=1711702453; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SYRuYu6Nyn7zXJDQL50vurRoO71Bn8A9O+6ORi9MHIc=; b=WWPrwROg38cFGX1ky35ZpI7lJ8wzDtaM+zCSdGwC8VY8BZLtxDlDmkmiCcE7cIOjLl R1TJDMb+CRGRT1y4pNgY0MNaEs9fD5OWvONnZFbdkrMbmkj+5PqTZgYupyfWumAeEkUw vUicYZWD4YmOPuVnqtfANN9bhSnEr9cHvdzZd6/huq+tsVdZ/V/TFILFUn17sIGeYecq vBNIfIlkn/485y0X/vC0iOziSW5r4jrqBWHMY0At7pwlJXoaFkfInMngAtrUS2rw+im5 4BiSOlGaOql59ZlBTRfYD4oXFnWOT8xZT3oHYAuzAHOUySUwgu0jmK1d7q+DbETgs33c hkaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711097653; x=1711702453; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SYRuYu6Nyn7zXJDQL50vurRoO71Bn8A9O+6ORi9MHIc=; b=DSDKfF2KKA+ARkqRpVuEwOJBMh+Oio93RfLkTRJCOgjcXkY9BxgKRPUOj3MVHWbqVC t4Eg/IoUebnrMihFztmkey0NHp+LCTXs7lBMlRjk5QMcskNlsGlXVD3CoRblHW4IyuhR oEEZ3oVl7kzM2rSDwWEzY5AAydluzhP5A19LoluAoe95jAYCRBuHI8yMhWhYDULNsME5 deFIeO4QF6c4mhQ1EIzq6u6O+nB0e70E4xXaJkbKT5HvSgYb4Xl8qGZd5/X7gY/3BLnR d6I9Q2t36FjWIEJYARJrp0iNHFksgtGB7P8+uoZXHvRvYgGAGZrgunDXKjmLi/GvgBiK bOCw== X-Gm-Message-State: AOJu0YwHXOXq/lec+R4sSER+mOHIZyTwkt/Z/ucTzYFPWSVCmI+YB49Z n4DDR5Lul5iRROO78Yldr6Hhxxybu+Wtj4zUfIl5e3YFN0ojTi+aZXfjWYSqzbgezg== X-Google-Smtp-Source: AGHT+IFH6/kCtfYWPkatpO2OdwfvTL7AFvu/F83LklLVrc89fsjfPZk99J5JAm9/EQvetj2f7cdjDQ== X-Received: by 2002:a17:902:ec8b:b0:1e0:98f3:fe56 with SMTP id x11-20020a170902ec8b00b001e098f3fe56mr134456plg.26.1711097653512; Fri, 22 Mar 2024 01:54:13 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Max Chou , Alistair Francis Subject: [PULL 13/15] target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin Date: Fri, 22 Mar 2024 18:53:17 +1000 Message-ID: <20240322085319.1758843-14-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711097716855100003 Content-Type: text/plain; charset="utf-8" From: Max Chou According to the Zvfbfmin definition in the RISC-V BF16 extensions spec, the Zvfbfmin extension only requires either the V extension or the Zve32f extension. Signed-off-by: Max Chou Reviewed-by: Alistair Francis Message-ID: <20240321170929.1162507-1-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 63192ef54f..b5b95e052d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -530,11 +530,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 - if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { - error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"= ); - return; - } - if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); return; --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711097685; cv=none; d=zohomail.com; s=zohoarc; b=Xrh8Dc940uT4xjj071dXrnrSk1ihrA9lYNvb50K6KoANVkiisxGpXuZ35Chdr63ZV4fVsWONmgaSfgabTG532aLYNmmMlOoLLmZtXo6NrkguiJnq1hrqvthKfCEi9rG9cAhg5WSYutyupikByeid/hjyybYK8IHdB2MmMNwd6xI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711097685; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oSFo3fIToAxpMkyPRv8jExYnTdr2jvQxba3OkQ37IQ0=; b=ApmgnyMu4ulNzHGGiyD3NOLlosPNiTiqT+Ycpd6+gRcP8c5JnHYodMY4xxD+eFpONAMPqwo3FJeyLOZf2goiS5kwEpMoDfrJmK9SYsr4hmYCcF6dqPOlxhg8P77u/vWN3dKAi3XWvIEsIkGJ16fTnBAu1wG3hKy7PVa7PCZi0AY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711097685536732.4973405268761; Fri, 22 Mar 2024 01:54:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnafN-0004h8-V1; Fri, 22 Mar 2024 04:54:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnafM-0004fJ-6G for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:54:20 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnafK-00012Y-MV for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:54:19 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1dfff641d10so12230625ad.2 for ; Fri, 22 Mar 2024 01:54:18 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.54.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:54:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711097657; x=1711702457; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oSFo3fIToAxpMkyPRv8jExYnTdr2jvQxba3OkQ37IQ0=; b=YY7VDde5wrf1rJZ9hGDIqoqb/84e5admDpIWkdicTlLS+MbCx7mg7bzrQJNqI7Sqbe zRKLhDmX+PBRYS/OrtR+HKE1ExfeYw+YQoRcAwCx7n+8SaZkEySwDdWORPTje4yu/DI1 lsCTQxDE3+RK5ud+m6lnGsCDc5ezwgEuEIyOeJ6KEt6PtTg+spxmsqdKMGq0LuecnddH TDueOXYJ0CcdFF+1hwPQMV2nZt4eehgbsTsMOulQIG9gMmS7mFR1NFvN/yLAqVYpabvY i3BUjKkr9axoF9S1wosbSIWMbRHLsE8sJ4ps/d6i5FkBpyavAghRlfs3etydKfCLGY4T AElg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711097657; x=1711702457; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oSFo3fIToAxpMkyPRv8jExYnTdr2jvQxba3OkQ37IQ0=; b=Z1ES4rGe64paqMko/VwgB3RuyY3yRZAaGThHUa5R/CjZJQnc1cFnxOXljl68ngvIMD EF5/HqVo0i3ZzMPH/bYFsUBfyRK4+1U+knzPoZTb4v99DtVwwgZdaldBpGiv+vCaE9ki yoRk+j+lvYjQ4OIpx+xnjr+hUrlphUHGz46bjk1cXzdOmsMOqno89W058N2QFYJZLrdP jp0eSdtV4QJZCq/yixayUV4XRdMyMuNLAAWQMZQJ81jA9yhHV76blX6yp2C79jKvHPPs urkh0pa31GO3m/s/PLgCV0+rwwOhNVomjRp/XWYgEI2hfLM46heVPC7EXJgee7GbbF15 wYEA== X-Gm-Message-State: AOJu0YymYSAwp0xNqK1fsR3SHOOXgyQPFuaj6eLoLbbQ2CuczHmsVssQ JAWShFdtx48xcza/gw2Y5g8tVA1qYvbpLVhoA+bTsszKL5Yl7gkduSAaXGTzRzx62Q== X-Google-Smtp-Source: AGHT+IGaRQNrh8prHyItgTFsN50K1NZ4FsYvWQaiRTBFjhjxiIpzzeVj0AYqYr7f4zRlHPBlcwGaBw== X-Received: by 2002:a17:903:2a86:b0:1de:ee01:56d7 with SMTP id lv6-20020a1709032a8600b001deee0156d7mr1915632plb.51.1711097656797; Fri, 22 Mar 2024 01:54:16 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Irina Ryapolova , Alistair Francis , Daniel Henrique Barboza Subject: [PULL 14/15] target/riscv: Fix mode in riscv_tlb_fill Date: Fri, 22 Mar 2024 18:53:18 +1000 Message-ID: <20240322085319.1758843-15-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711097686742100003 Content-Type: text/plain; charset="utf-8" From: Irina Ryapolova Need to convert mmu_idx to privilege mode for PMP function. Signed-off-by: Irina Ryapolova Fixes: b297129ae1 ("target/riscv: propagate PMP permission to TLB page") Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20240320172828.23965-1-irina.ryapolova@syntacore.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ce7322011d..fc090d729a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1315,7 +1315,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, bool two_stage_lookup =3D mmuidx_2stage(mmu_idx); bool two_stage_indirect_error =3D false; int ret =3D TRANSLATE_FAIL; - int mode =3D mmu_idx; + int mode =3D mmuidx_priv(mmu_idx); /* default TLB page size */ target_ulong tlb_size =3D TARGET_PAGE_SIZE; =20 --=20 2.44.0 From nobody Fri May 10 15:05:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1711097730; cv=none; d=zohomail.com; s=zohoarc; b=hcEjeMJTV1rRv9XiDiUkiXtEcqmQz9iLGL4jDJ6UlUSwfztnjBwujoS5P0Nt/eszlKlzKs6oXJjJF5IPlQIqGEY5B18bKhLOkF9b7KWToA6LkXWDKIPxEXZHLEc1++wipDRQkd0koteS3d8Jjn8dRkQ2Ef/IOyiMWzlDxg8JWSY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711097730; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ljw0MvRJZooGVgJY7PB96wXwwjw3QI+ulH/dM68Nsmw=; b=BEt7eN3hNT2ULyynQUxXYkjpq3j1lXHrVUvtFttdsE2ynQiwH3ovDHKybh3iEAp23XW+gQtQiZDjn2HWXB8hpkHBLmvxu2ofOmdZkjKZnB/pjgkMwkwgRY2FrCs09CkwlA9Op1B6v3pkRcbvJKb92FQSj23z/dR8ux0eQkICPPU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711097730013112.70059170651473; Fri, 22 Mar 2024 01:55:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnafR-0004tO-Kv; Fri, 22 Mar 2024 04:54:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnafP-0004hu-Bb for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:54:23 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnafN-00012j-RM for qemu-devel@nongnu.org; Fri, 22 Mar 2024 04:54:23 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1e04ac200a6so13924285ad.1 for ; Fri, 22 Mar 2024 01:54:21 -0700 (PDT) Received: from toolbox.wdc.com ([129.253.180.114]) by smtp.gmail.com with ESMTPSA id h5-20020a170902680500b001ddde07af12sm1369048plk.143.2024.03.22.01.54.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:54:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711097660; x=1711702460; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ljw0MvRJZooGVgJY7PB96wXwwjw3QI+ulH/dM68Nsmw=; b=AxEjTgd2DLrq2uW00bdkmDXrMegA1fn3eSm7X+BBF/3m26ZqYyY01vTacP4locq7/H ABddoiJwhgQ2rdc/jeyce/epS+0ScYZMGDZ/MuWWIGTshFIGrESHmaW/6XJqtSvMHTjb gUm5SVlznctlbCo8ZztookH0hjgIswHn+puCO3zC9BousTMG4M1qz4Dx48ty1xDen9Cf gIn6yZMIzsKnHsAOXCcVO6it1VVBpK8prlTlKJKr0+w0Mac5WVQRavJTcobXYAcHe63W p6SjFUV9aOvm7PkYOjqIYit4Yd41fNlaYOQub4VU2jY6MqCMsduhU9vFYv64CD66CXPj 5q5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711097660; x=1711702460; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ljw0MvRJZooGVgJY7PB96wXwwjw3QI+ulH/dM68Nsmw=; b=jTUtEzVgIfbBsfgc5uz/AE3Xfe62ljfHHsVAdTRpvEyLr9ZgT1SZJYI7WES4u/8l01 1E8lCN4jchitmBFjmclMY9gC3hBHimpudnm8gPQQ2ayR2mEENtjmoamFw3xYeyJSJv9m HV5mEKu/elYWgncNgrLOvHTShh3QbDxbHL4yKl6zQaHJaSszsxUgmJpkpyQQg/xmVtBY B8rqFnhCUqu/RugewxAP6JZQ7DqOGrzbVCExZUtd1ThMNYMPdAUp6qKAmlplbNqJFzi1 BnfZNhBabLSKhIClNvyxF24CqdYzYG/yw+8Jw8ZgGMLb1bJk85HI0EGJi+o5cow7sIeE LgaQ== X-Gm-Message-State: AOJu0Yx+Yd/wLnvNe/SG996ZMhCqS9fcmBKmreLHmXC9ij3EPnPqv7TT lCynbl+TXMrvm1dbIQAHz1ZL0x4Ejo6wF8kA+86A46tqZ4c7nmD6bSkb5Gi3TC0LPA== X-Google-Smtp-Source: AGHT+IHKYCEZLbiYG243f/RtVaRve+3mp80pY5awYn/fFu1TYObDXv4119eyxLh50rGuZoLXWJVbUg== X-Received: by 2002:a17:902:6808:b0:1e0:8b17:58b5 with SMTP id h8-20020a170902680800b001e08b1758b5mr1726224plk.13.1711097660268; Fri, 22 Mar 2024 01:54:20 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yong-Xuan Wang , Andrew Jones , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 15/15] target/riscv/kvm: fix timebase-frequency when using KVM acceleration Date: Fri, 22 Mar 2024 18:53:19 +1000 Message-ID: <20240322085319.1758843-16-alistair.francis@wdc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240322085319.1758843-1-alistair.francis@wdc.com> References: <20240322085319.1758843-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=alistair23@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1711097730892100003 From: Yong-Xuan Wang The timebase-frequency of guest OS should be the same with host machine. The timebase-frequency value in DTS should be got from hypervisor when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Message-ID: <20240314061510.9800-1-yongxuan.wang@sifive.com> Reviewed-by: Andrew Jones Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm_riscv.h | 1 + hw/riscv/virt.c | 2 ++ target/riscv/kvm/kvm-cpu.c | 9 +++++++++ 3 files changed, 12 insertions(+) diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h index 4bd98fddc7..5851898868 100644 --- a/target/riscv/kvm/kvm_riscv.h +++ b/target/riscv/kvm/kvm_riscv.h @@ -28,5 +28,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t= group_shift, void riscv_kvm_aplic_request(void *opaque, int irq, int level); int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state); void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp); +uint64_t kvm_riscv_get_timebase_frequency(CPUState *cs); =20 #endif diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 72a55b8af1..d171e74f7b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -711,6 +711,8 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, =20 qemu_fdt_add_subnode(ms->fdt, "/cpus"); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", + kvm_enabled() ? + kvm_riscv_get_timebase_frequency(first_cpu) : RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index cda7d78a77..6a6c6cae80 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -739,6 +739,15 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) env->kvm_timer_dirty =3D false; } =20 +uint64_t kvm_riscv_get_timebase_frequency(CPUState *cs) +{ + uint64_t reg; + + KVM_RISCV_GET_TIMER(cs, frequency, reg); + + return reg; +} + static int kvm_riscv_get_regs_vector(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); --=20 2.44.0