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Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-9.1 17/21] target/xtensa: Prefix MMU API with 'xtensa_' Date: Thu, 21 Mar 2024 16:48:33 +0100 Message-ID: <20240321154838.95771-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1711036329079100005 In order to extract the MMU API to a new "mmu.h" header, prefix it with the target name. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/xtensa/cpu.h | 4 ++-- target/xtensa/cpu.c | 2 +- target/xtensa/mmu_helper.c | 41 +++++++++++++++++++++----------------- target/xtensa/monitor.c | 2 +- 4 files changed, 27 insertions(+), 22 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 6b8d0636d2..b2cfc78e9d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -692,8 +692,8 @@ static inline int xtensa_get_cring(const CPUXtensaState= *env) int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, uint32_t vaddr, int is_write, int mmu_idx, uint32_t *paddr, uint32_t *page_size, unsigned *access); -void reset_mmu(CPUXtensaState *env); -void dump_mmu(CPUXtensaState *env); +void xtensa_reset_mmu(CPUXtensaState *env); +void xtensa_dump_mmu(CPUXtensaState *env); =20 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) { diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 875cf843c9..ae0c4aab24 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -130,7 +130,7 @@ static void xtensa_cpu_reset_hold(Object *obj) env->exclusive_addr =3D -1; =20 #ifndef CONFIG_USER_ONLY - reset_mmu(env); + xtensa_reset_mmu(env); cs->halted =3D env->runstall; #endif set_no_signaling_nans(!dfpu, &env->fp_status); diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 47063b0a57..31ee3fa957 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -139,7 +139,8 @@ static uint32_t xtensa_tlb_get_addr_mask(const CPUXtens= aState *env, * Get bit mask for the 'VPN without index' field. * See ISA, 4.6.5.6, data format for RxTLB0 */ -static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_= t way) +static uint32_t xtensa_get_vpn_mask(const CPUXtensaState *env, bool dtlb, + uint32_t way) { if (way < 4) { bool is32 =3D (dtlb ? @@ -168,9 +169,10 @@ static uint32_t get_vpn_mask(const CPUXtensaState *env= , bool dtlb, uint32_t way) * Split virtual address into VPN (with index) and entry index * for the given TLB way */ -static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, - bool dtlb, uint32_t *vpn, - uint32_t wi, uint32_t *ei) +static void xtensa_split_tlb_entry_spec_way(const CPUXtensaState *env, + uint32_t v, + bool dtlb, uint32_t *vpn, + uint32_t wi, uint32_t *ei) { bool varway56 =3D dtlb ? env->config->dtlb.varway56 : @@ -224,13 +226,15 @@ static void split_tlb_entry_spec_way(const CPUXtensaS= tate *env, uint32_t v, * Split TLB address into TLB way, entry index and VPN (with index). * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format */ -static bool split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtl= b, - uint32_t *vpn, uint32_t *wi, uint32_t *ei) +static bool xtensa_split_tlb_entry_spec(CPUXtensaState *env, + uint32_t v, bool dtlb, + uint32_t *vpn, uint32_t *wi, + uint32_t *ei) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { *wi =3D v & (dtlb ? 0xf : 0x7); if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nway= s)) { - split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); + xtensa_split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); return true; } else { return false; @@ -254,14 +258,14 @@ static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXten= saState *env, bool dtlb, env->itlb[wi] + ei; } =20 -static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, +static xtensa_tlb_entry *xtensa_get_tlb_entry(CPUXtensaState *env, uint32_t v, bool dtlb, uint32_t *pwi) { uint32_t vpn; uint32_t wi; uint32_t ei; =20 - if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { + if (xtensa_split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { if (pwi) { *pwi =3D wi; } @@ -405,7 +409,7 @@ static void reset_tlb_region_way0(CPUXtensaState *env, } } =20 -void reset_mmu(CPUXtensaState *env) +void xtensa_reset_mmu(CPUXtensaState *env) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { env->sregs[RASID] =3D 0x04030201; @@ -470,7 +474,7 @@ static int xtensa_tlb_lookup(const CPUXtensaState *env, for (wi =3D 0; wi < tlb->nways; ++wi) { uint32_t vpn; uint32_t ei; - split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); + xtensa_split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); if (entry[wi][ei].vaddr =3D=3D vpn && entry[wi][ei].asid) { unsigned ring =3D get_ring(env, entry[wi][ei].asid); if (ring < 4) { @@ -493,10 +497,11 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t = v, uint32_t dtlb) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { uint32_t wi; - const xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); + const xtensa_tlb_entry *entry =3D xtensa_get_tlb_entry(env, v, dtl= b, &wi); =20 if (entry) { - return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->a= sid; + return (entry->vaddr & xtensa_get_vpn_mask(env, dtlb, wi)) + | entry->asid; } else { return 0; } @@ -507,7 +512,7 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v,= uint32_t dtlb) =20 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) { - const xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, NULL); + const xtensa_tlb_entry *entry =3D xtensa_get_tlb_entry(env, v, dtlb, N= ULL); =20 if (entry) { return entry->paddr | entry->attr; @@ -520,7 +525,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint= 32_t dtlb) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { uint32_t wi; - xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); + xtensa_tlb_entry *entry =3D xtensa_get_tlb_entry(env, v, dtlb, &wi= ); if (entry && entry->variable && entry->asid) { tlb_flush_page(env_cpu(env), entry->vaddr); entry->asid =3D 0; @@ -559,7 +564,7 @@ void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint= 32_t v, uint32_t dtlb) uint32_t vpn; uint32_t wi; uint32_t ei; - if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { + if (xtensa_split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); } } @@ -818,7 +823,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, b= ool update_tlb, may_lookup_pt && get_pte(env, vaddr, &pte)) { ring =3D (pte >> 4) & 0x3; wi =3D 0; - split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); + xtensa_split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); =20 if (update_tlb) { wi =3D ++env->autorefill_idx & 0x3; @@ -1192,7 +1197,7 @@ static void dump_mpu(CPUXtensaState *env, } } =20 -void dump_mmu(CPUXtensaState *env) +void xtensa_dump_mmu(CPUXtensaState *env) { if (xtensa_option_bits_enabled(env->config, XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | diff --git a/target/xtensa/monitor.c b/target/xtensa/monitor.c index fbf60d5553..ce1b791a5c 100644 --- a/target/xtensa/monitor.c +++ b/target/xtensa/monitor.c @@ -35,5 +35,5 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict) monitor_printf(mon, "No CPU available\n"); return; } - dump_mmu(env1); + xtensa_dump_mmu(env1); } --=20 2.41.0