From nobody Mon Feb 9 18:18:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1711031379; cv=none; d=zohomail.com; s=zohoarc; b=HRsbWjiFW48t+thmxeUZ34cqqR+fUH8VHljF2XBgYDrTs3OFILkhm1yYlJixa4LQXdpl6uMuNRmq+lhvANji7du2Tn41g6L+/BpdiOHasGQhVP9jU8aiD4KlpyQvwat547pOnR6zp0xT2fPg6jF+U1KbsTS88sMZtfTjr/y0w2I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711031379; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OVlbdW/A0FgZbR9hmfP/AKVGjFpE85kMvdgDliFuIbE=; b=Bop2m4WLxVKhEPtngEz5jUu2WOUq/yqJBJ2/JMJrRIMokMSrZOWNLeEKGpYzE0KrYSfk72hJDrqaqFlsIurBCN+f5SaNMP0wILkR2GN01C31MLexJeCgLaBKWu48FuyTpQiF8f/SkCUWeQeP4qvK3T/CfC2RuOVoh11bp5StNuQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1711031379814679.2335830995712; Thu, 21 Mar 2024 07:29:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnJOs-0008Fy-O5; Thu, 21 Mar 2024 10:28:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnJOr-0008Fq-JN for qemu-devel@nongnu.org; Thu, 21 Mar 2024 10:28:09 -0400 Received: from mgamail.intel.com ([198.175.65.15]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnJOm-0002mA-TQ for qemu-devel@nongnu.org; Thu, 21 Mar 2024 10:28:09 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2024 07:28:03 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa009.jf.intel.com with ESMTP; 21 Mar 2024 07:27:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1711031285; x=1742567285; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JxmKg9znHiM4ZxOUvsstDqgH6lgWIoCF2yjSUZdkR8o=; b=mg5duF6nbpN1e4bQomXd3cOAKHrygDwth2xRymlcKMruX+LP6gSqYwqA /+Y9hl4c8PW+fwdc/tfPEe+wJmkyJxWZgEZxb2sQwZtlpvdzxcoEP4+Se VzjaByrUySnhjg/jhuRI7vwCOb3cN1snGBGuXiw80vbZ+I0Scf+aNxW9n 4F6pq03Lp/k/blPdDstS4VUXTBVVuNALmwklJPZd+7NmV5R44gAwkboEe hfcgNU2Qpc7/MZUF6qFGd4BbOMW4orpzcIAgeiCN7+gEoXWEnBiOJeO+d U9gkaUbwC0dYzGW5yXmqE35kroqVEWwIDbAdAD0Qs1UfjgvuPN7UjC8F9 w==; X-IronPort-AV: E=McAfee;i="6600,9927,11020"; a="9806496" X-IronPort-AV: E=Sophos;i="6.07,143,1708416000"; d="scan'208";a="9806496" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,143,1708416000"; d="scan'208";a="14528048" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Xiaoyao Li Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Babu Moger , Yongwei Ma , Zhao Liu Subject: [PATCH v10 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Date: Thu, 21 Mar 2024 22:40:37 +0800 Message-Id: <20240321144048.3699388-11-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240321144048.3699388-1-zhao1.liu@linux.intel.com> References: <20240321144048.3699388-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.175.65.15; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.372, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1711031380242100009 From: Zhao Liu CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared by Intel and AMD CPUs. But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU (in CPUID[0x80000026]) have the different definitions with different enumeration values. Though CPUID[0x80000026] hasn't been implemented in QEMU, to avoid possible misunderstanding, split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] and introduce CPUID[0x1F]-specific topology types. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Babu Moger --- Changes since v8: * Add Philippe's reviewed-by tag. Changes since v3: * New commit to prepare to refactor CPUID[0x1F] encoding. --- target/i386/cpu.c | 14 +++++++------- target/i386/cpu.h | 13 +++++++++---- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6b159298fea5..d030b45f9c3e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6266,17 +6266,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, case 0: *eax =3D apicid_core_offset(&topo_info); *ebx =3D topo_info.threads_per_core; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + *ecx |=3D CPUID_B_ECX_TOPO_LEVEL_SMT << 8; break; case 1: *eax =3D apicid_pkg_offset(&topo_info); *ebx =3D threads_per_pkg; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + *ecx |=3D CPUID_B_ECX_TOPO_LEVEL_CORE << 8; break; default: *eax =3D 0; *ebx =3D 0; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + *ecx |=3D CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; } =20 assert(!(*eax & ~0x1f)); @@ -6301,22 +6301,22 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, case 0: *eax =3D apicid_core_offset(&topo_info); *ebx =3D topo_info.threads_per_core; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_SMT << 8; break; case 1: *eax =3D apicid_die_offset(&topo_info); *ebx =3D topo_info.cores_per_die * topo_info.threads_per_core; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_CORE << 8; break; case 2: *eax =3D apicid_pkg_offset(&topo_info); *ebx =3D threads_per_pkg; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_DIE << 8; break; default: *eax =3D 0; *ebx =3D 0; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_INVALID << 8; } assert(!(*eax & ~0x1f)); *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 60ebc6378064..2e24f457468d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1017,10 +1017,15 @@ uint64_t x86_cpu_get_supported_feature_word(Feature= Word w, #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ =20 /* CPUID[0xB].ECX level types */ -#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) -#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) -#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) -#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) +#define CPUID_B_ECX_TOPO_LEVEL_INVALID 0 +#define CPUID_B_ECX_TOPO_LEVEL_SMT 1 +#define CPUID_B_ECX_TOPO_LEVEL_CORE 2 + +/* COUID[0x1F].ECX level types */ +#define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID +#define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT +#define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE +#define CPUID_1F_ECX_TOPO_LEVEL_DIE 5 =20 /* MSR Feature Bits */ #define MSR_ARCH_CAP_RDCL_NO (1U << 0) --=20 2.34.1