From nobody Mon Feb 9 00:42:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1710960537; cv=none; d=zohomail.com; s=zohoarc; b=E5Mdzkw5kJ53OXQby0EP0/D88OY6lA9B3ydh/dat9rg3xgzbdeET+vOsLA0QeHiLnxe/OniSRKhy5clJonfZL0qHy3hZVT+iSKQDsCWF6MBrCGb/lle94zmLQYHS9YF4vnQG6x4u4GV+jvhpb8OAn/po8rViRJ0+E3cIny1QGcI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1710960537; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=s8eHfqxCJ4+LBDvckwGxtN6BjZ4R5Ucl4tZMRUUvIEU=; b=IQniJwrKqmrImPoCcdW4HlzTiBl0MMT8+V2TZtmUhHen6S3KqPK7+RWoiLz5wJ5gVl+asKPfUB19SvBC9gZppXxY8ZBPe68JjXgUlK8cvxGdNuXTFDocew2nwI+7Y1/FI1PZgaYi4Q1ZtkhVto8D1b44Pi64rxS/l0P8bbKi3ZI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1710960537948587.7134261626027; Wed, 20 Mar 2024 11:48:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rn0zC-0003h5-TS; Wed, 20 Mar 2024 14:48:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rn0zA-0003gi-Oh for qemu-devel@nongnu.org; Wed, 20 Mar 2024 14:48:24 -0400 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rn0z8-0007Ki-IJ for qemu-devel@nongnu.org; Wed, 20 Mar 2024 14:48:24 -0400 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id C6CF1CE11DF; Wed, 20 Mar 2024 18:48:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9826C433F1; Wed, 20 Mar 2024 18:48:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1710960491; bh=2mN88b/umYUpNkVd9Y67o3TZZWJCHz6vGznnkN8CKzo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RHYFlDkWtQpYT+2VLSF+icAxmaWeR6NZynf73KviFdFlAnhz38mA8UHbx+xkJuvtE UszUIdNYn6mqxH40a4YVa11bvzQs5hw9eIBBjuauInDQ1fapUaV6+eaMEDdhbNikXU /QRJH1tUsmyUQpmQrJdsYNFjPzKv6/dectyi0ykDOoYHgD9HjfHNzifWzHHPczQl17 iK+lEaUpLdcJ4nsVsZ8OGhTxY0/CPdAoQuChz5DEXSs1bUpW/Eedi9b8I+tlBacpmJ 6abYAkJ4VeQhTKy0QwG3/2XKX94Fe7WkfH+nnXAvX6OQyyh4jgFyEOgBjVNoiRGjq5 43it2JeA8NDqQ== From: Felipe Balbi To: qemu-devel@nongnu.org Cc: Felipe Balbi Subject: [PATCH 2/2] hw/arm: Add nucleo-g071rb board Date: Wed, 20 Mar 2024 20:47:59 +0200 Message-ID: <20240320184759.754619-3-balbi@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240320184759.754619-1-balbi@kernel.org> References: <20240320184759.754619-1-balbi@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2604:1380:40e1:4800::1; envelope-from=balbi@kernel.org; helo=sin.source.kernel.org X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.417, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1710960538910100007 Content-Type: text/plain; charset="utf-8" From: Felipe Balbi This board is based around STM32G071RB SoC, a Cortex-M0 based device. More information can be found at: https://www.st.com/en/product/nucleo-g071rb.html Signed-off-by: Felipe Balbi --- hw/arm/Kconfig | 6 ++++ hw/arm/meson.build | 1 + hw/arm/nucleo-g071rb.c | 70 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 hw/arm/nucleo-g071rb.c diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 28a46d2b1ad3..5938bb8208a1 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -310,6 +310,12 @@ config STM32VLDISCOVERY depends on TCG && ARM select STM32F100_SOC =20 +config NUCLEO_G071RB + bool + default y + depends on TCG && ARM + select STM32G000_SOC + config STRONGARM bool select PXA2XX diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 9c4137a988e1..580c2d55fc3f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -18,6 +18,7 @@ arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realv= iew.c')) arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscove= ry.c')) +arm_ss.add(when: 'CONFIG_NUCLEO_G071RB', if_true: files('nucleo-g071rb.c')) arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c')) arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c')) =20 diff --git a/hw/arm/nucleo-g071rb.c b/hw/arm/nucleo-g071rb.c new file mode 100644 index 000000000000..580b52bacf2c --- /dev/null +++ b/hw/arm/nucleo-g071rb.c @@ -0,0 +1,70 @@ +/* + * ST Nucleo G071RB + * + * Copyright (c) 2024 Felipe Balbi + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" +#include "qemu/error-report.h" +#include "hw/arm/stm32g000_soc.h" +#include "hw/arm/boot.h" + +/* nucleo_g071rb implementation is derived from olimex-stm32-h405.c */ + +/* Main SYSCLK frequency in Hz (48MHz) */ +#define SYSCLK_FRQ 48000000ULL + +static void nucleo_g071rb_init(MachineState *machine) +{ + DeviceState *dev; + Clock *sysclk; + + /* This clock doesn't need migration because it is fixed-frequency */ + sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, SYSCLK_FRQ); + + dev =3D qdev_new(TYPE_STM32G000_SOC); + object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); + qdev_connect_clock_in(dev, "sysclk", sysclk); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + armv7m_load_kernel(ARM_CPU(first_cpu), + machine->kernel_filename, + 0, FLASH_SIZE); +} + +static void nucleo_g071rb_machine_init(MachineClass *mc) +{ + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m0"), + NULL + }; + + mc->desc =3D "ST Nucleo-G071RB (Cortex-M0)"; + mc->init =3D nucleo_g071rb_init; + mc->valid_cpu_types =3D valid_cpu_types; +} + +DEFINE_MACHINE("nucleo-g071rb", nucleo_g071rb_machine_init) --=20 2.44.0