From nobody Wed May 15 10:30:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1710955218; cv=none; d=zohomail.com; s=zohoarc; b=ZLy2uvS9FSM1JusWGSQ6ZrAE+QV1a+3E0uhwwVNU2wUAKQNpS7eOZUlw+GNQelcG2dXzPxU91kSXuJ1o3oxtFBr6/EV5xn5HREJBUysc7fPGFo9SB6OtVxcrnXfKqAdDWmfeae8BeEIhkTv8uO497qfURxzD2a8Gura/H3Yz4N8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1710955218; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:Message-Id:Reply-To:To; bh=M3zg+TJOwT1YZDeI03C6xkLyuJzaKqAbiBHCFsf4Vtc=; b=XMNFRdZcfOZX5eD1juIBIeQPV4mH4WU9J8KeGd7uMI1wxC9QD3Ufzbl8tL72ynRb/NUxN+Ynm4ToXoirkY5yvul50jl2jTDSrjIgB/E2Ty+eRkE7dtJpTEMJG77uTICHYevQ1ebabuWnqNc3BcTIOMcGTDAp0k7wrp2k34J523s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1710955218025230.63520617490065; Wed, 20 Mar 2024 10:20:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rmzam-0003Aa-4t; Wed, 20 Mar 2024 13:19:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rmzak-00039H-Nu; Wed, 20 Mar 2024 13:19:06 -0400 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rmzah-0006cu-Eb; Wed, 20 Mar 2024 13:19:06 -0400 Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-a46f60cc80aso11391066b.0; Wed, 20 Mar 2024 10:19:02 -0700 (PDT) Received: from freya.midgard (broadband-188-255-126-251.ip.moscow.rt.ru. [188.255.126.251]) by smtp.gmail.com with ESMTPSA id pv27-20020a170907209b00b00a4576dd5a8csm7481639ejb.201.2024.03.20.10.18.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Mar 2024 10:19:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1710955141; x=1711559941; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M3zg+TJOwT1YZDeI03C6xkLyuJzaKqAbiBHCFsf4Vtc=; b=GAV12DWYB0XwGyxGOpugipLJjqvawMA/tOIecpKM4G0Q+cno/7gnTjmzGQie9Q6/+C 9ZlUtVimkobnacJegS9aL636o559jkcfJydlYztDcM9v4dgFgWIzPxAtfVAR5kogGJty a0DV6/7KXvv9l2ZSDkhs6T2g+V4AeS1/f4KVJEh/UWXBlEdM7wb8mHBe5yqEbIfLNhq9 6e8Fms9PizCkn4saWqTu+jgM+4qHmV0MOafRSA8R1LMYBdeNfHvUkfkfL6owGBuo5/df vyZU742cylDIZpecO+DOWVCtdTKb0h6aaQ8dVMmVWpl9xwvRuSB48Y/cgwaWre5ccwjU 0KHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710955141; x=1711559941; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M3zg+TJOwT1YZDeI03C6xkLyuJzaKqAbiBHCFsf4Vtc=; b=IdEw7ihZ7pHbeZiy14pfGrJpRIGBQ68uamPYfaWmqPsq47D7TcEBFqukbfQTPgjAoN V+z7wHd8Qe22CMZP8wqrCHZLkawianPguXRHnEEMBlIaxxNDgNdwuMnhxgTiypI5x9SM ImoDdHRky5k51X1Ip4Pc4rTInNiY/7+DqisvlrX56mM7yQ3DE5zLII3pAUsGIwR1ju5i 0CSci+BI+e+f6FNGxraFD+yVzbAyyCmf1Sj6CNrY+sF0xmT9G7lAtiFgcILclzqUIqoO GcITcAZJkC9jqMLjiBdmk9xQZPaZESB1Fu7HVTQfhU7FVOPk+b5GJPnoXFNJrknqHG6D ZYrg== X-Forwarded-Encrypted: i=1; AJvYcCX/DZDglwVsgJ9WNlKBg+tgvhj5Ay1s1Pma152UeYYhKHVwTYJhlHdsuGrtwaLYkdxLqX59QLJL8jxXR5H3N0h5M3/LHqdIfjfawjPa9T5hu6nLDL5zLFQnVcIMaA== X-Gm-Message-State: AOJu0YyzxbNCqMIDSEquuL8W0NitL1q3yN/ypErv86N7viBOcmyKUysI fS9NNyz8QV2lXugsavqmNP1pesxhiVRkdO2qdteg/8xAorZ02zfm X-Google-Smtp-Source: AGHT+IHtSjCXmxjQ3HQbezSFMZ9EwBpndneNZaq414+nUvnAOQmzzS1RwxqNkEDDoww4f6B2eFEWgg== X-Received: by 2002:a17:907:e91:b0:a46:2c22:7f4c with SMTP id ho17-20020a1709070e9100b00a462c227f4cmr2073559ejc.35.1710955141392; Wed, 20 Mar 2024 10:19:01 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, space.monkey.delivers@gmail.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v8 1/6] target/riscv: Remove obsolete pointer masking extension code. Date: Wed, 20 Mar 2024 20:18:45 +0300 Message-Id: <20240320171850.1197824-2-me@deliversmonkey.space> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240320171850.1197824-1-me@deliversmonkey.space> References: <20240320171850.1197824-1-me@deliversmonkey.space> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1710955218802100001 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing = one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alistair Francis --- target/riscv/cpu.c | 13 +- target/riscv/cpu.h | 30 +--- target/riscv/cpu_bits.h | 87 ---------- target/riscv/cpu_helper.c | 52 ------ target/riscv/csr.c | 326 ----------------------------------- target/riscv/machine.c | 14 +- target/riscv/tcg/tcg-cpu.c | 5 +- target/riscv/translate.c | 27 +-- target/riscv/vector_helper.c | 2 +- 9 files changed, 13 insertions(+), 543 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c160b9216b..73c69f3d0a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -42,7 +42,7 @@ /* RISC-V CPU definitions */ static const char riscv_single_letter_exts[] =3D "IEMAFDQCBPVH"; const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, RVD, RVV, - RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0}; + RVC, RVS, RVU, RVH, RVG, RVB, 0}; =20 /* * From vector_helper.c @@ -793,13 +793,6 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f= , int flags) CSR_MSCRATCH, CSR_SSCRATCH, CSR_SATP, - CSR_MMTE, - CSR_UPMBASE, - CSR_UPMMASK, - CSR_SPMBASE, - CSR_SPMMASK, - CSR_MPMBASE, - CSR_MPMMASK, }; =20 for (i =3D 0; i < ARRAY_SIZE(dump_csrs); ++i) { @@ -979,8 +972,6 @@ static void riscv_cpu_reset_hold(Object *obj) } i++; } - /* mmte is supposed to have pm.current hardwired to 1 */ - env->mmte |=3D (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); =20 /* * Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor @@ -1002,7 +993,6 @@ static void riscv_cpu_reset_hold(Object *obj) pmp_unlock_entries(env); #endif env->xl =3D riscv_cpu_mxl(env); - riscv_cpu_update_mask(env); cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); @@ -1393,7 +1383,6 @@ static const MISAExtInfo misa_ext_info_arr[] =3D { MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"), MISA_EXT_INFO(RVU, "u", "User-level instructions"), MISA_EXT_INFO(RVH, "h", "Hypervisor"), - MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), MISA_EXT_INFO(RVV, "v", "Vector operations"), MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)") diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3b1a02b944..cfad5281a1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -68,7 +68,6 @@ typedef struct CPUArchState CPURISCVState; #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') -#define RVJ RV('J') #define RVG RV('G') #define RVB RV('B') =20 @@ -395,17 +394,6 @@ struct CPUArchState { /* True if in debugger mode. */ bool debugger; =20 - /* - * CSRs for PointerMasking extension - */ - target_ulong mmte; - target_ulong mpmmask; - target_ulong mpmbase; - target_ulong spmmask; - target_ulong spmbase; - target_ulong upmmask; - target_ulong upmbase; - /* CSRs for execution environment configuration */ uint64_t menvcfg; uint64_t mstateen[SMSTATEEN_MAX_COUNT]; @@ -414,9 +402,6 @@ struct CPUArchState { target_ulong senvcfg; uint64_t henvcfg; #endif - target_ulong cur_pmmask; - target_ulong cur_pmbase; - /* Fields from here on are preserved across CPU reset. */ QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ @@ -565,16 +550,14 @@ FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 16, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) -FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) -FIELD(TB_FLAGS, VTA, 20, 1) -FIELD(TB_FLAGS, VMA, 21, 1) +FIELD(TB_FLAGS, VTA, 18, 1) +FIELD(TB_FLAGS, VMA, 19, 1) /* Native debug itrigger */ -FIELD(TB_FLAGS, ITRIGGER, 22, 1) +FIELD(TB_FLAGS, ITRIGGER, 20, 1) /* Virtual mode enabled */ -FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) -FIELD(TB_FLAGS, PRIV, 24, 2) -FIELD(TB_FLAGS, AXL, 26, 2) +FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) +FIELD(TB_FLAGS, PRIV, 22, 2) +FIELD(TB_FLAGS, AXL, 24, 2) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) @@ -707,7 +690,6 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, u= int32_t vsew, void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags); =20 -void riscv_cpu_update_mask(CPURISCVState *env); bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fc2068ee4d..5098d2d613 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -484,37 +484,6 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f =20 -/* - * User PointerMasking registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_UMTE 0x4c0 -#define CSR_UPMMASK 0x4c1 -#define CSR_UPMBASE 0x4c2 - -/* - * Machine PointerMasking registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_MMTE 0x3c0 -#define CSR_MPMMASK 0x3c1 -#define CSR_MPMBASE 0x3c2 - -/* - * Supervisor PointerMaster registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_SMTE 0x1c0 -#define CSR_SPMMASK 0x1c1 -#define CSR_SPMBASE 0x1c2 - -/* - * Hypervisor PointerMaster registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_VSMTE 0x2c0 -#define CSR_VSPMMASK 0x2c1 -#define CSR_VSPMBASE 0x2c2 #define CSR_SCOUNTOVF 0xda0 =20 /* Crypto Extension */ @@ -734,11 +703,6 @@ typedef enum RISCVException { #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) =20 -/* General PointerMasking CSR bits */ -#define PM_ENABLE 0x00000001ULL -#define PM_CURRENT 0x00000002ULL -#define PM_INSN 0x00000004ULL - /* Execution environment configuration bits */ #define MENVCFG_FIOM BIT(0) #define MENVCFG_CBIE (3UL << 4) @@ -771,57 +735,6 @@ typedef enum RISCVException { #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE =20 -/* Offsets for every pair of control bits per each priv level */ -#define XS_OFFSET 0ULL -#define U_OFFSET 2ULL -#define S_OFFSET 5ULL -#define M_OFFSET 8ULL - -#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET) -#define U_PM_ENABLE (PM_ENABLE << U_OFFSET) -#define U_PM_CURRENT (PM_CURRENT << U_OFFSET) -#define U_PM_INSN (PM_INSN << U_OFFSET) -#define S_PM_ENABLE (PM_ENABLE << S_OFFSET) -#define S_PM_CURRENT (PM_CURRENT << S_OFFSET) -#define S_PM_INSN (PM_INSN << S_OFFSET) -#define M_PM_ENABLE (PM_ENABLE << M_OFFSET) -#define M_PM_CURRENT (PM_CURRENT << M_OFFSET) -#define M_PM_INSN (PM_INSN << M_OFFSET) - -/* mmte CSR bits */ -#define MMTE_PM_XS_BITS PM_XS_BITS -#define MMTE_U_PM_ENABLE U_PM_ENABLE -#define MMTE_U_PM_CURRENT U_PM_CURRENT -#define MMTE_U_PM_INSN U_PM_INSN -#define MMTE_S_PM_ENABLE S_PM_ENABLE -#define MMTE_S_PM_CURRENT S_PM_CURRENT -#define MMTE_S_PM_INSN S_PM_INSN -#define MMTE_M_PM_ENABLE M_PM_ENABLE -#define MMTE_M_PM_CURRENT M_PM_CURRENT -#define MMTE_M_PM_INSN M_PM_INSN -#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INS= N | \ - MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INS= N | \ - MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INS= N | \ - MMTE_PM_XS_BITS) - -/* (v)smte CSR bits */ -#define SMTE_PM_XS_BITS PM_XS_BITS -#define SMTE_U_PM_ENABLE U_PM_ENABLE -#define SMTE_U_PM_CURRENT U_PM_CURRENT -#define SMTE_U_PM_INSN U_PM_INSN -#define SMTE_S_PM_ENABLE S_PM_ENABLE -#define SMTE_S_PM_CURRENT S_PM_CURRENT -#define SMTE_S_PM_INSN S_PM_INSN -#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INS= N | \ - SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INS= N | \ - SMTE_PM_XS_BITS) - -/* umte CSR bits */ -#define UMTE_U_PM_ENABLE U_PM_ENABLE -#define UMTE_U_PM_CURRENT U_PM_CURRENT -#define UMTE_U_PM_INSN U_PM_INSN -#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_IN= SN) - /* MISELECT, SISELECT, and VSISELECT bits (AIA) */ #define ISELECT_IPRIO0 0x30 #define ISELECT_IPRIO15 0x3f diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ce7322011d..d20bffdd5a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -138,61 +138,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *= pc, flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); - if (env->cur_pmmask !=3D 0) { - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); - } - if (env->cur_pmbase !=3D 0) { - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); - } =20 *pflags =3D flags; } =20 -void riscv_cpu_update_mask(CPURISCVState *env) -{ - target_ulong mask =3D 0, base =3D 0; - RISCVMXL xl =3D env->xl; - /* - * TODO: Current RVJ spec does not specify - * how the extension interacts with XLEN. - */ -#ifndef CONFIG_USER_ONLY - int mode =3D cpu_address_mode(env); - xl =3D cpu_get_xl(env, mode); - if (riscv_has_ext(env, RVJ)) { - switch (mode) { - case PRV_M: - if (env->mmte & M_PM_ENABLE) { - mask =3D env->mpmmask; - base =3D env->mpmbase; - } - break; - case PRV_S: - if (env->mmte & S_PM_ENABLE) { - mask =3D env->spmmask; - base =3D env->spmbase; - } - break; - case PRV_U: - if (env->mmte & U_PM_ENABLE) { - mask =3D env->upmmask; - base =3D env->upmbase; - } - break; - default: - g_assert_not_reached(); - } - } -#endif - if (xl =3D=3D MXL_RV32) { - env->cur_pmmask =3D mask & UINT32_MAX; - env->cur_pmbase =3D base & UINT32_MAX; - } else { - env->cur_pmmask =3D mask; - env->cur_pmbase =3D base; - } -} - #ifndef CONFIG_USER_ONLY =20 /* @@ -724,7 +673,6 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv) /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; env->xl =3D cpu_recompute_xl(env); - riscv_cpu_update_mask(env); =20 /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 726096444f..ffb5a1102e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -486,16 +486,6 @@ static RISCVException hgatp(CPURISCVState *env, int cs= rno) return hmode(env, csrno); } =20 -/* Checks if PointerMasking registers could be accessed */ -static RISCVException pointer_masking(CPURISCVState *env, int csrno) -{ - /* Check if j-ext is present */ - if (riscv_has_ext(env, RVJ)) { - return RISCV_EXCP_NONE; - } - return RISCV_EXCP_ILLEGAL_INST; -} - static RISCVException aia_hmode(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_ssaia) { @@ -1401,7 +1391,6 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, env->xl =3D cpu_recompute_xl(env); } =20 - riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } =20 @@ -3968,302 +3957,6 @@ static RISCVException write_mcontext(CPURISCVState = *env, int csrno, return RISCV_EXCP_NONE; } =20 -/* - * Functions to access Pointer Masking feature registers - * We have to check if current priv lvl could modify - * csr in given mode - */ -static bool check_pm_current_disabled(CPURISCVState *env, int csrno) -{ - int csr_priv =3D get_field(csrno, 0x300); - int pm_current; - - if (env->debugger) { - return false; - } - /* - * If priv lvls differ that means we're accessing csr from higher priv= lvl, - * so allow the access - */ - if (env->priv !=3D csr_priv) { - return false; - } - switch (env->priv) { - case PRV_M: - pm_current =3D get_field(env->mmte, M_PM_CURRENT); - break; - case PRV_S: - pm_current =3D get_field(env->mmte, S_PM_CURRENT); - break; - case PRV_U: - pm_current =3D get_field(env->mmte, U_PM_CURRENT); - break; - default: - g_assert_not_reached(); - } - /* It's same priv lvl, so we allow to modify csr only if pm.current=3D= =3D1 */ - return !pm_current; -} - -static RISCVException read_mmte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mmte & MMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mmte(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - target_ulong wpri_val =3D val & MMTE_MASK; - - if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x= ", - val, "vs expected 0x", wpri_val); - } - /* for machine mode pm.current is hardwired to 1 */ - wpri_val |=3D MMTE_M_PM_CURRENT; - - /* hardwiring pm.instruction bit to 0, since it's not supported yet */ - wpri_val &=3D ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); - env->mmte =3D wpri_val | EXT_STATUS_DIRTY; - riscv_cpu_update_mask(env); - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_smte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mmte & SMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_smte(CPURISCVState *env, int csrno, - target_ulong val) -{ - target_ulong wpri_val =3D val & SMTE_MASK; - - if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x= ", - val, "vs expected 0x", wpri_val); - } - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - - wpri_val |=3D (env->mmte & ~SMTE_MASK); - write_mmte(env, csrno, wpri_val); - return RISCV_EXCP_NONE; -} - -static RISCVException read_umte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mmte & UMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_umte(CPURISCVState *env, int csrno, - target_ulong val) -{ - target_ulong wpri_val =3D val & UMTE_MASK; - - if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x= ", - val, "vs expected 0x", wpri_val); - } - - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - - wpri_val |=3D (env->mmte & ~UMTE_MASK); - write_mmte(env, csrno, wpri_val); - return RISCV_EXCP_NONE; -} - -static RISCVException read_mpmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mpmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mpmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - env->mpmmask =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE))= { - env->cur_pmmask =3D val; - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_spmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->spmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_spmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->spmmask =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE))= { - env->cur_pmmask =3D val; - if (cpu_get_xl(env, PRV_S) =3D=3D MXL_RV32) { - env->cur_pmmask &=3D UINT32_MAX; - } - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_upmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->upmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_upmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->upmmask =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE))= { - env->cur_pmmask =3D val; - if (cpu_get_xl(env, PRV_U) =3D=3D MXL_RV32) { - env->cur_pmmask &=3D UINT32_MAX; - } - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_mpmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mpmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mpmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - env->mpmbase =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE))= { - env->cur_pmbase =3D val; - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_spmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->spmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_spmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->spmbase =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE))= { - env->cur_pmbase =3D val; - if (cpu_get_xl(env, PRV_S) =3D=3D MXL_RV32) { - env->cur_pmbase &=3D UINT32_MAX; - } - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_upmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->upmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_upmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->upmbase =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE))= { - env->cur_pmbase =3D val; - if (cpu_get_xl(env, PRV_U) =3D=3D MXL_RV32) { - env->cur_pmbase &=3D UINT32_MAX; - } - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - #endif =20 /* Crypto Extension */ @@ -4869,25 +4562,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_TINFO] =3D { "tinfo", debug, read_tinfo, write_ignore = }, [CSR_MCONTEXT] =3D { "mcontext", debug, read_mcontext, write_mcontex= t }, =20 - /* User Pointer Masking */ - [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write_u= mte }, - [CSR_UPMMASK] =3D { "upmmask", pointer_masking, read_upmmask, - write_upmmask = }, - [CSR_UPMBASE] =3D { "upmbase", pointer_masking, read_upmbase, - write_upmbase = }, - /* Machine Pointer Masking */ - [CSR_MMTE] =3D { "mmte", pointer_masking, read_mmte, write_m= mte }, - [CSR_MPMMASK] =3D { "mpmmask", pointer_masking, read_mpmmask, - write_mpmmask = }, - [CSR_MPMBASE] =3D { "mpmbase", pointer_masking, read_mpmbase, - write_mpmbase = }, - /* Supervisor Pointer Masking */ - [CSR_SMTE] =3D { "smte", pointer_masking, read_smte, write_s= mte }, - [CSR_SPMMASK] =3D { "spmmask", pointer_masking, read_spmmask, - write_spmmask = }, - [CSR_SPMBASE] =3D { "spmbase", pointer_masking, read_spmbase, - write_spmbase = }, - /* Performance Counters */ [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_hpmcounter }, [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_hpmcounter }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 76f2150f78..64ab66e332 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -152,10 +152,7 @@ static const VMStateDescription vmstate_vector =3D { =20 static bool pointermasking_needed(void *opaque) { - RISCVCPU *cpu =3D opaque; - CPURISCVState *env =3D &cpu->env; - - return riscv_has_ext(env, RVJ); + return false; } =20 static const VMStateDescription vmstate_pointermasking =3D { @@ -164,14 +161,6 @@ static const VMStateDescription vmstate_pointermasking= =3D { .minimum_version_id =3D 1, .needed =3D pointermasking_needed, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL(env.mmte, RISCVCPU), - VMSTATE_UINTTL(env.mpmmask, RISCVCPU), - VMSTATE_UINTTL(env.mpmbase, RISCVCPU), - VMSTATE_UINTTL(env.spmmask, RISCVCPU), - VMSTATE_UINTTL(env.spmbase, RISCVCPU), - VMSTATE_UINTTL(env.upmmask, RISCVCPU), - VMSTATE_UINTTL(env.upmbase, RISCVCPU), - VMSTATE_END_OF_LIST() } }; @@ -266,7 +255,6 @@ static int riscv_cpu_post_load(void *opaque, int versio= n_id) CPURISCVState *env =3D &cpu->env; =20 env->xl =3D cpu_recompute_xl(env); - riscv_cpu_update_mask(env); return 0; } =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ab6db817db..0332203a1f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -988,7 +988,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { MISA_CFG(RVS, true), MISA_CFG(RVU, true), MISA_CFG(RVH, true), - MISA_CFG(RVJ, false), MISA_CFG(RVV, false), MISA_CFG(RVG, false), MISA_CFG(RVB, false), @@ -1275,8 +1274,8 @@ static void riscv_init_max_cpu_extensions(Object *obj) CPURISCVState *env =3D &cpu->env; const RISCVCPUMultiExtConfig *prop; =20 - /* Enable RVG, RVJ and RVV that are disabled by default */ - riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV); + /* Enable RVG and RVV that are disabled by default */ + riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVV); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { isa_ext_update_enabled(cpu, prop->offset, true); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ea5d52b2ef..3382eb0a5f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -42,9 +42,6 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cp= u_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; -/* globals for PM CSRs */ -static TCGv pm_mask; -static TCGv pm_base; =20 /* * If an operation is being performed on less than TARGET_LONG_BITS, @@ -106,9 +103,6 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; - /* PointerMasking extension */ - bool pm_mask_enabled; - bool pm_base_enabled; /* Ztso */ bool ztso; /* Use icount trigger for native debug */ @@ -584,14 +578,9 @@ static TCGv get_address(DisasContext *ctx, int rs1, in= t imm) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_addi_tl(addr, src1, imm); - if (ctx->pm_mask_enabled) { - tcg_gen_andc_tl(addr, addr, pm_mask); - } else if (get_address_xl(ctx) =3D=3D MXL_RV32) { + if (get_address_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } - if (ctx->pm_base_enabled) { - tcg_gen_or_tl(addr, addr, pm_base); - } =20 return addr; } @@ -603,14 +592,9 @@ static TCGv get_address_indexed(DisasContext *ctx, int= rs1, TCGv offs) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_add_tl(addr, src1, offs); - if (ctx->pm_mask_enabled) { - tcg_gen_andc_tl(addr, addr, pm_mask); - } else if (get_xl(ctx) =3D=3D MXL_RV32) { + if (get_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } - if (ctx->pm_base_enabled) { - tcg_gen_or_tl(addr, addr, pm_base); - } return addr; } =20 @@ -1196,8 +1180,6 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; - ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); - ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->ztso =3D cpu->cfg.ext_ztso; ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero =3D tcg_constant_tl(0); @@ -1330,9 +1312,4 @@ void riscv_translate_init(void) "load_res"); load_val =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= val), "load_val"); - /* Assign PM CSRs to tcg globals */ - pm_mask =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pm= mask), - "pmmask"); - pm_base =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pm= base), - "pmbase"); } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index fe56c007d5..4934b43722 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -104,7 +104,7 @@ static inline uint32_t vext_max_elems(uint32_t desc, ui= nt32_t log2_esz) =20 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) { - return (addr & ~env->cur_pmmask) | env->cur_pmbase; + return addr; } =20 /* --=20 2.34.1 From nobody Wed May 15 10:30:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1710955207340704.4756948051681; Wed, 20 Mar 2024 10:20:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rmzap-0003DY-0B; Wed, 20 Mar 2024 13:19:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rmzan-0003BE-GJ; Wed, 20 Mar 2024 13:19:09 -0400 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rmzaj-0006dD-Hr; Wed, 20 Mar 2024 13:19:09 -0400 Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-a46dd7b4bcbso8855766b.3; Wed, 20 Mar 2024 10:19:04 -0700 (PDT) Received: from freya.midgard (broadband-188-255-126-251.ip.moscow.rt.ru. [188.255.126.251]) by smtp.gmail.com with ESMTPSA id pv27-20020a170907209b00b00a4576dd5a8csm7481639ejb.201.2024.03.20.10.19.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Mar 2024 10:19:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1710955143; x=1711559943; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2ogrwyf87r+mMPq4/c/DH5Cr2l4Fo5V98Q/D5Kllk7U=; b=i9KJ+EakPiryxYWKpVm14tJYfARLrg/rRXV0emypdqB2mhY45i0WwdTW5ke5vpI7YV CiAXbsO8u9s4tSVl//YdWsJWh78+LDY98PgEri5jT9/44FOo5fG75kbOiR6iHLKzRedh 6TTOqizGZlrweJIxd8/01Xcoc6XiOgAqmn/62lYFhcsGY2Fx8bhJJsLJ7Cx+wni8TOZe PN443w+INlHcWI252S1++vTObBCKzqh2sPEy4BI6sqgAN2et0dflYtU0ZdC68eAbgOWn 27AWk8O9KZ+JW3hEc6BM4ycQ49XgI7Co2u0AqGcmveyLi/G/wBW5mQk2+aCLyNwuPf2R 3VbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710955143; x=1711559943; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2ogrwyf87r+mMPq4/c/DH5Cr2l4Fo5V98Q/D5Kllk7U=; b=UM2SYFxZMIPOeOx5dmbV26fUeAfqLdNBRI324JdOjGSAa/cPqCJvXdJvYtFJpQpMJN ItcjHx1hmLiy9TYPnaW8DrDG1cyMV8myQ/MXpmxu0iIUNJPcGKuGLtVvz7zCmh1pzf5S woj1Mw4zBUCiXsxEbl4eLsW7GFAaGdeZMR7vj8FhH3rgisGmNqwX5P6zQ29Y9t+Os81U rc6AteItNjmhuuYT783b1I2UeYEarDSL9hmiG/y0aV3QZ3FJyIsELD1h38SpDnriDU+C WcxloXJn5cwwKdaYB/5DIm2bl9ZlDMgt7TMtbB66wPCbRnt5W0iMEeKesju3Hms3ltI0 4oLQ== X-Forwarded-Encrypted: i=1; AJvYcCVl7WYZbxD60GShPt5huzRWpJ7KqUFdj5bAmtF8vmoRza4V00krKMrH/WyKizLvsifcx3b+G+1miw4oV5z7t7hWoNmKWBktuFKCyavP7dGC65D3jISL3aU9vaGm9w== X-Gm-Message-State: AOJu0YzNTU8jLXc8LR8XNgD/clpoaBAwVIj2xaZZATLuxS5xaCLg/kIX UQm92BA5G4/V2g6tlvntH47usGBEEWZ/T7PJq7L4kJozw9IWkPhFoKBNxbSykRw= X-Google-Smtp-Source: AGHT+IFs7lVb9rKt35pvMBpDK/YiRburThSxa8wPKhYK67qz22OSD7fI0dXKJzR2rrl3IxLATGYjfw== X-Received: by 2002:a17:906:f75a:b0:a44:1fcf:9b97 with SMTP id jp26-20020a170906f75a00b00a441fcf9b97mr11116669ejb.24.1710955143298; Wed, 20 Mar 2024 10:19:03 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, space.monkey.delivers@gmail.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v8 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 Date: Wed, 20 Mar 2024 20:18:46 +0300 Message-Id: <20240320171850.1197824-3-me@deliversmonkey.space> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240320171850.1197824-1-me@deliversmonkey.space> References: <20240320171850.1197824-1-me@deliversmonkey.space> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1710955208743100003 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 ++++++++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++++++++++ target/riscv/machine.c | 10 +++++++--- target/riscv/pmp.c | 13 ++++++++++--- target/riscv/pmp.h | 11 ++++++----- 7 files changed, 48 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cfad5281a1..b694cc62bf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -123,6 +123,14 @@ typedef enum { EXT_STATUS_DIRTY, } RISCVExtStatus; =20 +/* Enum holds PMM field values for Zjpm v0.8 extension */ +typedef enum { + PMM_FIELD_DISABLED =3D 0, + PMM_FIELD_RESERVED =3D 1, + PMM_FIELD_PMLEN7 =3D 2, + PMM_FIELD_PMLEN16 =3D 3, +} RISCVPmPmm; + #define MMU_USER_IDX 3 =20 #define MAX_RISCV_PMPS (16) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5098d2d613..e9e6e1f952 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -708,6 +708,7 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_PMM (3ULL << 32) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) @@ -721,11 +722,13 @@ typedef enum RISCVException { #define SENVCFG_CBIE MENVCFG_CBIE #define SENVCFG_CBCFE MENVCFG_CBCFE #define SENVCFG_CBZE MENVCFG_CBZE +#define SENVCFG_PMM MENVCFG_PMM =20 #define HENVCFG_FIOM MENVCFG_FIOM #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_PMM MENVCFG_PMM #define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2040b90da0..963de724c2 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -118,6 +118,9 @@ struct RISCVCPUConfig { bool ext_ssaia; bool ext_sscofpmf; bool ext_smepmp; + bool ext_ssnpm; + bool ext_smnpm; + bool ext_smmpm; bool rvv_ta_all_1s; bool rvv_ma_all_1s; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ffb5a1102e..69c0279c12 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -530,6 +530,9 @@ static RISCVException have_mseccfg(CPURISCVState *env, = int csrno) if (riscv_cpu_cfg(env)->ext_zkr) { return RISCV_EXCP_NONE; } + if (riscv_cpu_cfg(env)->ext_smmpm) { + return RISCV_EXCP_NONE; + } =20 return RISCV_EXCP_ILLEGAL_INST; } @@ -2080,6 +2083,10 @@ static RISCVException write_menvcfg(CPURISCVState *e= nv, int csrno, (cfg->ext_sstc ? MENVCFG_STCE : 0) | (cfg->ext_svadu ? MENVCFG_ADUE : 0); } + /* Update PMM field only if the value is valid according to Zjpm v0.8 = */ + if (((val & MENVCFG_PMM) >> 32) !=3D PMM_FIELD_RESERVED) { + mask |=3D MENVCFG_PMM; + } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); =20 return RISCV_EXCP_NONE; @@ -2124,6 +2131,10 @@ static RISCVException write_senvcfg(CPURISCVState *e= nv, int csrno, target_ulong val) { uint64_t mask =3D SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCF= G_CBZE; + /* Update PMM field only if the value is valid according to Zjpm v0.8 = */ + if (((val & SENVCFG_PMM) >> 32) !=3D PMM_FIELD_RESERVED) { + mask |=3D SENVCFG_PMM; + } RISCVException ret; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 64ab66e332..bbbb28f373 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -152,15 +152,19 @@ static const VMStateDescription vmstate_vector =3D { =20 static bool pointermasking_needed(void *opaque) { - return false; + RISCVCPU *cpu =3D opaque; + return cpu->cfg.ext_ssnpm || cpu->cfg.ext_smnpm || cpu->cfg.ext_smmpm; } =20 static const VMStateDescription vmstate_pointermasking =3D { .name =3D "cpu/pointer_masking", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D pointermasking_needed, .fields =3D (const VMStateField[]) { + VMSTATE_UINTTL(env.mseccfg, RISCVCPU), + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), + VMSTATE_UINTTL(env.menvcfg, RISCVCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 2a76b611a0..7ddb9dbf0b 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -574,6 +574,12 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint= 32_t addr_index) void mseccfg_csr_write(CPURISCVState *env, target_ulong val) { int i; + uint64_t mask =3D MSECCFG_MMWP | MSECCFG_MML; + + /* Update PMM field only if the value is valid according to Zjpm v0.8 = */ + if (((val & MSECCFG_PMM) >> 32) !=3D PMM_FIELD_RESERVED) { + mask |=3D MSECCFG_PMM; + } =20 trace_mseccfg_csr_write(env->mhartid, val); =20 @@ -589,12 +595,13 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulo= ng val) =20 if (riscv_cpu_cfg(env)->ext_smepmp) { /* Sticky bits */ - val |=3D (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML)); - if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) { + val |=3D (env->mseccfg & mask); + if ((val ^ env->mseccfg) & mask) { tlb_flush(env_cpu(env)); } } else { - val &=3D ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB); + mask |=3D MSECCFG_RLB; + val &=3D ~(mask); } =20 env->mseccfg =3D val; diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index f5c10ce85c..ccff0eb9b6 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -40,11 +40,12 @@ typedef enum { } pmp_am_t; =20 typedef enum { - MSECCFG_MML =3D 1 << 0, - MSECCFG_MMWP =3D 1 << 1, - MSECCFG_RLB =3D 1 << 2, - MSECCFG_USEED =3D 1 << 8, - MSECCFG_SSEED =3D 1 << 9 + MSECCFG_MML =3D 1 << 0, + MSECCFG_MMWP =3D 1 << 1, + MSECCFG_RLB =3D 1 << 2, + MSECCFG_USEED =3D 1 << 8, + MSECCFG_SSEED =3D 1 << 9, + MSECCFG_PMM =3D 3UL << 32, } mseccfg_field_t; =20 typedef struct { --=20 2.34.1 From nobody Wed May 15 10:30:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1710955224; cv=none; d=zohomail.com; s=zohoarc; b=JL9FcZTub2nohgKEOPXDf1wFavLlZD6RlL2jDZlW+MjgEdwn3ZYy1cbdT8MJyatvYG7/wlgzdJ3TXRXy8HwW+c9ouae+yCP0rXXMyz5KoEK8I2kFs8PJakHlnLTKsdaDlXkfVrsx33Y3JUdsf0tOspXXo47sv49znIR9+OU+5fc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1710955224; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:Message-Id:Reply-To:To; bh=nSE+cP7Lt5Sq8d6PTtVQTI1qKeIysjk+nWyIdSqtTIQ=; b=brHfcsl86JdvrK/eM6SLOtNNe04LY6/z/DfZBJDw0wLSBqiDirw7O49B5w9LnthcGcm/236xTC3hBPYpct6ca2SjEVlbDDvljE4xsVh55lVHspGY/DwBoPSkF007yvxkWoVdarP3HMt1Wi9XYorD4J5lqkC0Hv3y70mHzJgnedk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1710955224445760.2440886367706; Wed, 20 Mar 2024 10:20:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rmzap-0003EC-Ir; Wed, 20 Mar 2024 13:19:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rmzan-0003BF-Gh; Wed, 20 Mar 2024 13:19:09 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rmzak-0006dK-Pr; Wed, 20 Mar 2024 13:19:09 -0400 Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-56bb5d61c5bso8265a12.3; Wed, 20 Mar 2024 10:19:06 -0700 (PDT) Received: from freya.midgard (broadband-188-255-126-251.ip.moscow.rt.ru. [188.255.126.251]) by smtp.gmail.com with ESMTPSA id pv27-20020a170907209b00b00a4576dd5a8csm7481639ejb.201.2024.03.20.10.19.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Mar 2024 10:19:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1710955145; x=1711559945; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nSE+cP7Lt5Sq8d6PTtVQTI1qKeIysjk+nWyIdSqtTIQ=; b=B15JFonr5OxZPdKSTIXMOO4/ZV9xYmyCns758t8g4FRY4Tacs8rfre5iABvYQAdfuj XZUcBIDKhlxBbBI11nBetkM3dlDEpYUmXF52BxQvjQpHIls3PQ0jnqnttzrADBTd1eMB JZ04vOhJii55MethWn+3xhmWLo8PfiXhMnTHczNRVsMGW1zTKSRz5u3wUkp1UhgO5tZ9 ZCtj+AGg7m8SLSdoK8C1HQUqX33ZaMM2swMobtX5SkkG08cGhAIYCzWvRGT8NEU7mIyg Dj7nwhtXhiZNKlHalhGgYm9Sl7gpGtRDQjk2aMzOnK7mrAwlmW+W0JnzPOzaTXl6KKD2 F3SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710955145; x=1711559945; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nSE+cP7Lt5Sq8d6PTtVQTI1qKeIysjk+nWyIdSqtTIQ=; b=FIpmUEWsbSpjnBXrLohaw3yYR2WhUXJpzyQg+m7TrclPQfk1PuuCOQfqaDF8vBI7BV zBtp39dMqkgdCHwv7ESGAlj4zCzEM+Ax67WfBd+zB6dqwpOdFEa0n8wcMvdXdcnpKkUp OjU6Xd7O/Mfy9ouSQRE3UeutpSGR312fWhV2SVsAE02W1kLhpz6wntrU+OcpQlpfzkNz goMwebgFbvNNg1bN30w6VapQrvF2hQVxq8q72LINqeiggyVCFusvlFzris1bZLFjw4tF pUIbsJuQOUSJ/1WewbD8ImypwyGRes+GgfNQsuYhrIxzVCFJGHk2GSlq0N5MUBnhvawQ pX5Q== X-Forwarded-Encrypted: i=1; AJvYcCVDXzsZsYamifE4A6WAdsYBeVtfiMEyzXZvicBcQlF2PeMF/tOllitCm1GNJKpdcTH05yuvf1/hZWtBJ+2jWd2uW2HewsBn6YOAtWYiFIlPVzuXglsRszyIb43ZHA== X-Gm-Message-State: AOJu0YwP3ub/aNFEXY7AxQaJVhaR4rQpsT578TKJW/2FkFQa6eUVCb9+ Usnf/iHalSRLFy04uvuzGOHWfCKMIvQ4v2iGymaAmJGzdfJYXNeg X-Google-Smtp-Source: AGHT+IFIenEPHdDGHL4L+xANfAS8jS9IfYxYdqagoJPpZJ1CudU1wqAPf0K+ImqB/8gHMJbnYIAq4A== X-Received: by 2002:a17:906:6bd0:b0:a46:f58c:33b1 with SMTP id t16-20020a1709066bd000b00a46f58c33b1mr1746758ejs.7.1710955144921; Wed, 20 Mar 2024 10:19:04 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, space.monkey.delivers@gmail.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v8 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Date: Wed, 20 Mar 2024 20:18:47 +0300 Message-Id: <20240320171850.1197824-4-me@deliversmonkey.space> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240320171850.1197824-1-me@deliversmonkey.space> References: <20240320171850.1197824-1-me@deliversmonkey.space> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=baturo.alexey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1710955224836100001 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 4 +++ target/riscv/cpu_helper.c | 58 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b694cc62bf..0112b568a0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -700,6 +700,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, =20 bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); +int riscv_pm_get_pmlen(RISCVPmPmm pmm); + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask= ); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d20bffdd5a..a563451c48 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -142,6 +142,64 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, *pflags =3D flags; } =20 +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) +{ + int pmm =3D 0; +#ifndef CONFIG_USER_ONLY + int priv_mode =3D cpu_address_mode(env); + /* Get current PMM field */ + switch (priv_mode) { + case PRV_M: + pmm =3D riscv_cpu_cfg(env)->ext_smmpm ? + get_field(env->mseccfg, MSECCFG_PMM) : PMM_FIELD_DISABLE= D; + break; + case PRV_S: + pmm =3D riscv_cpu_cfg(env)->ext_smnpm ? + get_field(env->menvcfg, MENVCFG_PMM) : PMM_FIELD_DISABLE= D; + break; + case PRV_U: + pmm =3D riscv_cpu_cfg(env)->ext_ssnpm ? + get_field(env->senvcfg, SENVCFG_PMM) : PMM_FIELD_DISABLE= D; + break; + default: + g_assert_not_reached(); + } +#endif + return pmm; +} + +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env) +{ + bool virt_mem_en =3D false; +#ifndef CONFIG_USER_ONLY + int satp_mode =3D 0; + int priv_mode =3D cpu_address_mode(env); + /* Get current PMM field */ + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + satp_mode =3D get_field(env->satp, SATP32_MODE); + } else { + satp_mode =3D get_field(env->satp, SATP64_MODE); + } + virt_mem_en =3D ((satp_mode !=3D VM_1_10_MBARE) && (priv_mode !=3D PRV= _M)); +#endif + return virt_mem_en; +} + +int riscv_pm_get_pmlen(RISCVPmPmm pmm) +{ + switch (pmm) { + case PMM_FIELD_DISABLED: + return 0; + case PMM_FIELD_PMLEN7: + return 7; + case PMM_FIELD_PMLEN16: + return 16; + default: + g_assert_not_reached(); + } + return -1; +} + #ifndef CONFIG_USER_ONLY =20 /* --=20 2.34.1 From nobody Wed May 15 10:30:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1710955224; cv=none; d=zohomail.com; s=zohoarc; b=IZC5zLUiuBY/Twzc4uwckPToWF5+CEGI+dug6nLyz8PkVI2WDBoR98A7y0ULVwbI5l5vYp9TW9LWn/epQ6AZ38GCVmzlDRt/5Xm4KkoMGDsTO2z/1/PSOv3+Oo/UbQ0atG0ZaovsRWilpLRckNAnAFU39yt0FVmxb2/7Dssx4NY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1710955224; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:Message-Id:Reply-To:To; bh=7nInynHLgmsZQVaTOvTBwe6136gOIvfQkQAoCQ5NVmY=; b=exupogJDXsZ5Lv9thHy/C7bTlT0m4dai9YNrI7MtzLgE943njuNEmZ2IBlxUt+TR6MeIYRgPaUlY1K74hdAOlsih1mfQcTeCIKUnQfJOPtQ+R4z64Jiikae/W8kKO+Z1al4OiVrXQZpV4tqIpdXH9Qk/sZMzid2viX960IeI8/E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1710955224677723.3954447777894; Wed, 20 Mar 2024 10:20:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rmzar-0003HM-HW; Wed, 20 Mar 2024 13:19:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rmzap-0003FY-WB; Wed, 20 Mar 2024 13:19:12 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rmzao-0006de-1I; Wed, 20 Mar 2024 13:19:11 -0400 Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-565c6cf4819so2071101a12.1; Wed, 20 Mar 2024 10:19:08 -0700 (PDT) Received: from freya.midgard (broadband-188-255-126-251.ip.moscow.rt.ru. [188.255.126.251]) by smtp.gmail.com with ESMTPSA id pv27-20020a170907209b00b00a4576dd5a8csm7481639ejb.201.2024.03.20.10.19.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Mar 2024 10:19:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1710955146; x=1711559946; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7nInynHLgmsZQVaTOvTBwe6136gOIvfQkQAoCQ5NVmY=; b=BG0/8j/hhv8V8gwm7NlQpukafTehg3Zig8apJ5IBTINjrsA3F6CCG7bCZdi/76rcBi IaRPzZSoVIAcbU0jJwFtB2wx3h+GxtKZA5SjcZNr+sfSqFu+XucnjLN9VXe881OBnMIh OUfSmN3WLTA+Fe/wJ5dFBNV/ZtXkMI8RIXhs+IgfZQ50LxdEA/RdmUdDEtOQ3bHJX8pN 6m3+W87H/44GdQRT3b+JhkrzaW7dx9o/J7e3i7QmzFBZKr8FGaP5qSYp8BO8X+DT7mQc CIQWxVo7xOSC/ZaAWEG+ZQPsG8YUElwUkxxbhIit6pa57LT7UPpm4JdZ4sRCUp80zo7e sNRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710955146; x=1711559946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7nInynHLgmsZQVaTOvTBwe6136gOIvfQkQAoCQ5NVmY=; b=IfVsxU/kmSiNxC11zARe5QflCRY7D3rYK5GDQKsAxmNZtf5B37BEZ2d5/CyU7AFvib GnW6zsH5iFnj+WFuTVrM8oPtrQ3GfGKTgTwWkBMSX/nkNBdQwn9Jq6qNxhEWfW/Uvd6W lZuxsGFj+hR/SiBHkk9SQGn/kJ/8rnhsXiRQXUZxzWbw2O/ICUkgikJU1VrHlRObO/kX /ptPS8eaDlkxFcT9mWp7Ad+qv0y3lPKVZCFJx8Zt5I4fAnwrJx3UvhR2jsRsfdloVita 53k192oaB3vvleWJPqk9M4O5WDvNYz4t177XheOGaX1dLsAK4r8NmZwA3IpzNgBIBKk9 iEJA== X-Forwarded-Encrypted: i=1; AJvYcCXI4gVzLd1N6ObMRLPj/Jd4O2/lT5aJDSpZHcqJ3rKHm0vQSsgwyzHRMlz0gENUP+NELzC2RDcSy7SAxz1wV4RVToHzqkGU4YzXdHAzcMAtqzTmT/d8wlVXkX4/cQ== X-Gm-Message-State: AOJu0YyvNpWk7Kx108pqBIcT7BXdoBd/MruBfhzg7S1G0ew6WWj2FLKg /YT5Httcymxfuo1y4Rag3lf5z0xkixn3tn78jSPGj3EjmJrkRaLv X-Google-Smtp-Source: AGHT+IHWMWAfuKmdfMPW23LTSjcrmEa6G9tM8KEYgBb2xWOCHCiiKZtThYVkiCsJ9cYABGLkl29ajQ== X-Received: by 2002:a17:906:b2cf:b0:a46:ba8f:bcdc with SMTP id cf15-20020a170906b2cf00b00a46ba8fbcdcmr259895ejb.8.1710955146597; Wed, 20 Mar 2024 10:19:06 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, space.monkey.delivers@gmail.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v8 4/6] target/riscv: Add pointer masking tb flags Date: Wed, 20 Mar 2024 20:18:48 +0300 Message-Id: <20240320171850.1197824-5-me@deliversmonkey.space> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240320171850.1197824-1-me@deliversmonkey.space> References: <20240320171850.1197824-1-me@deliversmonkey.space> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=baturo.alexey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1710955226782100007 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 +++++ 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0112b568a0..404f6ec50d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -566,6 +566,9 @@ FIELD(TB_FLAGS, ITRIGGER, 20, 1) FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) FIELD(TB_FLAGS, PRIV, 22, 2) FIELD(TB_FLAGS, AXL, 24, 2) +/* If pointer masking should be applied and address sign extended */ +FIELD(TB_FLAGS, PM_PMM, 26, 2) +FIELD(TB_FLAGS, PM_SIGNEXTEND, 28, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a563451c48..4dea564fd8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -68,6 +68,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, RISCVCPU *cpu =3D env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags =3D 0; + bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); =20 *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base =3D 0; @@ -138,6 +139,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 *pflags =3D flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3382eb0a5f..a85a2abf2e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -103,6 +103,9 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; + /* actual address width */ + uint8_t addr_width; + bool addr_signed; /* Ztso */ bool ztso; /* Use icount trigger for native debug */ @@ -1180,6 +1183,8 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; + ctx->addr_width =3D 0; + ctx->addr_signed =3D false; ctx->ztso =3D cpu->cfg.ext_ztso; ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero =3D tcg_constant_tl(0); --=20 2.34.1 From nobody Wed May 15 10:30:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1710955251; cv=none; d=zohomail.com; s=zohoarc; b=mcyhKJjGqTUpsJpUCbJdMHqt6JsTKFWWn42Ur35JP0pxuNT8vgXsGfL4G+sADYEfosujxmWzVE74W/CRdRGN98k0J/xMEJvIivV4m7uPWf5bMj2OhDRZDJ9GbSUM+sRew6QgzKSwkIr0JmWpiewAip8obOyMMltPboa4aNQdV0U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1710955251; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:Message-Id:Reply-To:To; bh=6nPBlyXh9PstQrdc2QN20ZOIAAOUlM+tDmlK8yXosHE=; b=DfLYwbkP62FZqYOHx7PsvdADY11j6UxrqfzZrofPpQB/eYoyd+rFnCF+RUW35wGceaROfTIkNmVIMDzrg4PEpQvHdcFA07sEZJETD9PoyLJOn2bg+mx3oUciqAemTJ44rNhvJLSDd7+Zzw54BmwLcXTWH6hQYK4No5QTbkXTw1U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1710955251906686.2428422658458; Wed, 20 Mar 2024 10:20:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rmzat-0003IT-Jy; Wed, 20 Mar 2024 13:19:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rmzar-0003H5-8k; Wed, 20 Mar 2024 13:19:13 -0400 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rmzao-0006dk-QT; Wed, 20 Mar 2024 13:19:12 -0400 Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-565c6cf4819so2071153a12.1; Wed, 20 Mar 2024 10:19:10 -0700 (PDT) Received: from freya.midgard (broadband-188-255-126-251.ip.moscow.rt.ru. [188.255.126.251]) by smtp.gmail.com with ESMTPSA id pv27-20020a170907209b00b00a4576dd5a8csm7481639ejb.201.2024.03.20.10.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Mar 2024 10:19:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1710955148; x=1711559948; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6nPBlyXh9PstQrdc2QN20ZOIAAOUlM+tDmlK8yXosHE=; b=S1/35plK6g1InP4LUNxAmwWcYciutqS2SHTWfS/gDz80RLG301QEruuCVUr052tp94 jSJOCjj8ddM7dkuu9q8mdnOLdN8uZ4eE+ie1D4VkOZ2Oh18IVPUcDZVOHzwfDjb81cR9 Dtu+w6X6p230koD2lUCrtvRGZm2C441EEFAREq2cXghuOnwoZi8Vj8v+eEa7y7iVKOXj cm0O7MNUyYX1HpaUUQ/D4SzLybEQ6T5k35nvyDcxPz6XG7j67As67yzNsPnk2qMeUEqZ ScURyBH1RTx3QpkiOqbN/PsKw8nxeG7GMcgJ0E1UfWdfmdT+adjjax4vwXDAaaHSbnip claQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710955148; x=1711559948; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6nPBlyXh9PstQrdc2QN20ZOIAAOUlM+tDmlK8yXosHE=; b=hAgHunJtBPCg8PsAeF+hDk0V9foli+zVBSApsQj3364PyNm0qmhYe4qQ4mys1A8xt9 704GaxNz0n2CuB2gKXevkGWmi6VNIREGLUzyY/0rM8MwAuQ97t6L7+ZgU5TGK6NUtJmB Kdhz6XHUznAvfydB3kqCezjw+tu5H7Gg0prqSAOZcpVH5WTABHhTBEB96dO6LxRcKLzs ujGMZPDfd1SEoVnpLT8+pFL++U7wuAv3zmvmfN9DCxBi9iRuOFrgnL5+Qr8tfSGd+jvO /tB6jeqhWiO5w4yuPRbN59SS/MTGEMcah+oqiHRwErw1Auot2jcrpD6gT2APnjlgmJoc ruRw== X-Forwarded-Encrypted: i=1; AJvYcCUYV8Y0HtIJgpUYzFSKThpkHexoJNst6W2Xx2ckY8Kb4TC7hyL37LrXxSL5qerD45GKh1rySguTpSnPEEQJrTVKONVDu+aX0Ul7UzewW2d11PDnwf+3ab5nETlKfA== X-Gm-Message-State: AOJu0Yw+X7a8XpO04IoZUIhgI2YixG4gh9o03a3BQyCH3GBowdjs2KhJ /NY0sYyhieLIeEnWZ0ZD0CynK8PmFNRtPGrwwafRn1jVu9DNOzQv X-Google-Smtp-Source: AGHT+IGLzZL6Aas8em91WPvq67iXB5/pT6DqhnD//NMI7o4VQI9cAyqTi1VdoFk/a7OqLFFjeu0b6w== X-Received: by 2002:a17:906:b094:b0:a46:8227:2d0c with SMTP id x20-20020a170906b09400b00a4682272d0cmr252650ejy.1.1710955148280; Wed, 20 Mar 2024 10:19:08 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, space.monkey.delivers@gmail.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v8 5/6] target/riscv: Update address modify functions to take into account pointer masking Date: Wed, 20 Mar 2024 20:18:49 +0300 Message-Id: <20240320171850.1197824-6-me@deliversmonkey.space> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240320171850.1197824-1-me@deliversmonkey.space> References: <20240320171850.1197824-1-me@deliversmonkey.space> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=baturo.alexey@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1710955252892100001 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 22 ++++++++++++++++------ target/riscv/vector_helper.c | 13 +++++++++++++ 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a85a2abf2e..99c5c6a530 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -581,8 +581,10 @@ static TCGv get_address(DisasContext *ctx, int rs1, in= t imm) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_addi_tl(addr, src1, imm); - if (get_address_xl(ctx) =3D=3D MXL_RV32) { - tcg_gen_ext32u_tl(addr, addr); + if (ctx->addr_signed) { + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width); + } else { + tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width); } =20 return addr; @@ -595,8 +597,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int= rs1, TCGv offs) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_add_tl(addr, src1, offs); - if (get_xl(ctx) =3D=3D MXL_RV32) { - tcg_gen_ext32u_tl(addr, addr); + if (ctx->addr_signed) { + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width); + } else { + tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width); } return addr; } @@ -1183,8 +1187,14 @@ static void riscv_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; - ctx->addr_width =3D 0; - ctx->addr_signed =3D false; + if (get_xl(ctx) =3D=3D MXL_RV32) { + ctx->addr_width =3D 32; + ctx->addr_signed =3D false; + } else { + int pm_pmm =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM); + ctx->addr_width =3D 64 - riscv_pm_get_pmlen(pm_pmm); + ctx->addr_signed =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND); + } ctx->ztso =3D cpu->cfg.ext_ztso; ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero =3D tcg_constant_tl(0); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 4934b43722..c77fbd8929 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -104,6 +104,19 @@ static inline uint32_t vext_max_elems(uint32_t desc, u= int32_t log2_esz) =20 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) { + RISCVPmPmm pmm =3D riscv_pm_get_pmm(env); + if (pmm =3D=3D PMM_FIELD_DISABLED) { + return addr; + } + int pmlen =3D riscv_pm_get_pmlen(pmm); + bool signext =3D riscv_cpu_virt_mem_enabled(env); + addr =3D addr << pmlen; + /* sign/zero extend masked address by N-1 bit */ + if (signext) { + addr =3D (target_long)addr >> pmlen; + } else { + addr =3D addr >> pmlen; + } return addr; } =20 --=20 2.34.1 From nobody Wed May 15 10:30:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1710955244; cv=none; d=zohomail.com; s=zohoarc; b=fdCx8AO7UjkKKB+qaq5qEnzjpA8Oa4nergIcmH0bPNfghTiooyxOPPb8mmGVdAO2CBP8wH5kmCf75t36uXGX5fDj8QMSM7u+4t3rEu5wFF4Wtle8SjczFxgc1mAlqGtDxXxqHH/CMvyO4bC8P3+/tnh1w7/hAcySScsy8XA1jug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1710955244; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:Message-Id:Reply-To:To; bh=3pEt6Y91A7HM8RCal+AzIsE2i5XHB8wZ5gv0UJ8gFKI=; b=jICYTB6wA1FVpWUsj0lbGVsTJKzZf2oG3xErQbUCgOpBSPYGu6ABcAscnIEv6GkyjxQaagf4gxINg3FPT2lF6iV1eZgjGzETZj23xoDqhmOPiETD6yZOBm66De5KR4j7j7c2uMYO97kikpv07DAEX3JtxOSy12IMywdWlPYi9qk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1710955244532414.1053331114624; Wed, 20 Mar 2024 10:20:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rmzat-0003IR-JZ; Wed, 20 Mar 2024 13:19:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rmzar-0003HR-Ia; Wed, 20 Mar 2024 13:19:13 -0400 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rmzap-0006eF-Tc; Wed, 20 Mar 2024 13:19:13 -0400 Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-a468004667aso6379066b.2; Wed, 20 Mar 2024 10:19:11 -0700 (PDT) Received: from freya.midgard (broadband-188-255-126-251.ip.moscow.rt.ru. [188.255.126.251]) by smtp.gmail.com with ESMTPSA id pv27-20020a170907209b00b00a4576dd5a8csm7481639ejb.201.2024.03.20.10.19.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Mar 2024 10:19:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1710955150; x=1711559950; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3pEt6Y91A7HM8RCal+AzIsE2i5XHB8wZ5gv0UJ8gFKI=; b=d7KTUuUDSssPzdsMYYDQ+2VQHw9qcQ3FUsVc2/NCP7U71+F1uA9+XdgvjwkJoZ954X kpdJAkVYDcjasBatMbM25FVCYFzHSMXlUb+76nOX0dBSJrNFSoxsxVcOKt2KaqMjpj/4 EbH61s5FVD6aJJws7A0Ws8QcIhHCj+SJAXz+d4S5E+t2YjM/c9pOC3vBWLgCCz+4gw7z s51a334DPWEx6vYjTQqQksZ2csejgtgjO9eCNOum+OfRmnU92+hTEGxatOmWjg/WuJ2f wd7htxIyuonahtrvsiGGRj1PcEE9aI66OBN8hhpf/Ev8uR4EXyZFMYpI0EUN4PxjD+mG duiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710955150; x=1711559950; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3pEt6Y91A7HM8RCal+AzIsE2i5XHB8wZ5gv0UJ8gFKI=; b=c56ZUmYRPsqftpLga3P6jKeAcxSE1utpTLa7f/aN0B5ZZhL8R8VctV/7XtV5FSAnwl zghB23VuL3y++e2KOzvfpz4REjlingjT2BfWVjzlqmm7DV7xhfkvh64NRxAAsk+e+/Tw d/CM6MQd+ZXew7pOJ34f+tNzOgvT94j5EdrmIynlHPihPo41J8/08RtJh3X5nUA//Gu1 suYsMZV01TdKSRi8v5sunnRmmP9xI9Pgw8AaNx6mjN2xTQoFcxmzuFquDRNruqIhNl0H UJALKodqGv7wEjhkOYwoGzzOG9Qi82uxoeKjW56J6jC0+U7uY0atpWtFcIQ2vt9U8MUm 3uGw== X-Forwarded-Encrypted: i=1; AJvYcCVbYnvLFkICnC+hud2csLuj/mGD+VUKv63hj8Nl2HrRxDoi6dW3N5uU0+6mTAUAhvEtUgL/1632f5LYrVArD3+8+NcWVh6piiOYk5fUOOvUXX6uhj47S7Y74ofYCg== X-Gm-Message-State: AOJu0YzTWw+Svt4VPiEKLvIbLHO9BuaHtVqcFu+vjQrVF6njmHp5k8Ly TZ7MTG6SZPR614L8CymGb/m6yqj+o28cEgwF8tW7wsIO6lxQm7SS X-Google-Smtp-Source: AGHT+IE+KBVk9BqSUknzL5iFw4h7Upe8/Rni/qGxT+ubhbC8jkdIhz6ecUUbu9nE0gQgSTI0eTGgjw== X-Received: by 2002:a17:907:5cb:b0:a46:c56f:fe39 with SMTP id wg11-20020a17090705cb00b00a46c56ffe39mr6820068ejb.39.1710955150086; Wed, 20 Mar 2024 10:19:10 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, space.monkey.delivers@gmail.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v8 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Date: Wed, 20 Mar 2024 20:18:50 +0300 Message-Id: <20240320171850.1197824-7-me@deliversmonkey.space> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240320171850.1197824-1-me@deliversmonkey.space> References: <20240320171850.1197824-1-me@deliversmonkey.space> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1710955244804100003 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 73c69f3d0a..9e3bf6c5c5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -190,6 +190,9 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_12_0, ext_ssnpm), + ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_12_0, ext_smnpm), + ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_12_0, ext_smmpm), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -1561,6 +1564,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]= =3D { =20 /* These are experimental so mark with 'x-' */ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { + /* Zjpm v0.8 extensions */ + MULTI_EXT_CFG_BOOL("x-ssnpm", ext_ssnpm, false), + MULTI_EXT_CFG_BOOL("x-smnpm", ext_smnpm, false), + MULTI_EXT_CFG_BOOL("x-smmpm", ext_smmpm, false), + DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.34.1