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Fri, 15 Mar 2024 06:10:07 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Markus Armbruster Cc: qemu-riscv@nongnu.org, Anton Johansson , qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Paolo Bonzini , Eduardo Habkost , Claudio Fontana , Richard Henderson , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Manos Pitsidianakis , Zhao Liu , qemu-arm@nongnu.org, Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH-for-9.1 08/21] target/sparc: Make SPARC_CPU common to new SPARC32_CPU/SPARC64_CPU types Date: Fri, 15 Mar 2024 14:08:56 +0100 Message-ID: <20240315130910.15750-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240315130910.15750-1-philmd@linaro.org> References: <20240315130910.15750-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=philmd@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710508720085100002 "target/foo/cpu-qom.h" can not use any target specific definitions. Currently "target/sparc/cpu-qom.h" defines TYPE_SPARC_CPU depending on the sparc(32)/sparc64 build type. This doesn't scale in a heterogeneous context where we need to access both types concurrently. In order to do that, introduce the new SPARC32_CPU / SPARC64_CPU types, both inheriting a common TYPE_SPARC_CPU base type. Keep the current CPU types registered in sparc_register_cpudef_type() as 32 or 64-bit, depending on the binary built. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Mark Cave-Ayland --- target/sparc/cpu-qom.h | 9 +++++---- target/sparc/cpu.c | 12 +++++++++++- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index a86331bd58..6ad283506e 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -22,14 +22,15 @@ =20 #include "hw/core/cpu.h" =20 -#ifdef TARGET_SPARC64 -#define TYPE_SPARC_CPU "sparc64-cpu" -#else #define TYPE_SPARC_CPU "sparc-cpu" -#endif +#define TYPE_SPARC32_CPU "sparc32-cpu" +#define TYPE_SPARC64_CPU "sparc64-cpu" =20 OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU) =20 +OBJECT_DECLARE_CPU_TYPE(SPARC32CPU, SPARCCPUClass, SPARC32_CPU) +OBJECT_DECLARE_CPU_TYPE(SPARC64CPU, SPARCCPUClass, SPARC64_CPU) + #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 42b13ab63f..9e27e16b75 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -959,6 +959,12 @@ static const TypeInfo sparc_cpu_types[] =3D { .abstract =3D true, .class_size =3D sizeof(SPARCCPUClass), .class_init =3D sparc_cpu_class_init, + }, { + .name =3D TYPE_SPARC32_CPU, + .parent =3D TYPE_SPARC_CPU, + }, { + .name =3D TYPE_SPARC64_CPU, + .parent =3D TYPE_SPARC_CPU, } }; =20 @@ -975,7 +981,11 @@ static void sparc_register_cpudef_type(const struct sp= arc_def_t *def) char *typename =3D sparc_cpu_type_name(def->name); TypeInfo ti =3D { .name =3D typename, - .parent =3D TYPE_SPARC_CPU, +#ifdef TARGET_SPARC64 + .parent =3D TYPE_SPARC64_CPU, +#else + .parent =3D TYPE_SPARC32_CPU, +#endif .class_init =3D sparc_cpu_cpudef_class_init, .class_data =3D (void *)def, }; --=20 2.41.0