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Fri, 15 Mar 2024 06:10:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Markus Armbruster Cc: qemu-riscv@nongnu.org, Anton Johansson , qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Paolo Bonzini , Eduardo Habkost , Claudio Fontana , Richard Henderson , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Manos Pitsidianakis , Zhao Liu , qemu-arm@nongnu.org, Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-9.1 13/21] system: Introduce cpu_typename_by_arch_bit() Date: Fri, 15 Mar 2024 14:09:01 +0100 Message-ID: <20240315130910.15750-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240315130910.15750-1-philmd@linaro.org> References: <20240315130910.15750-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=philmd@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1710508355684100001 Introduce a helper to return the CPU type name given a QemuArchBit. The TYPE_PPC_CPU target have different 32/64-bit definitions so we can not include it yet. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- --- MAINTAINERS | 1 + include/sysemu/arch_init.h | 2 ++ system/cpu-qom-helpers.c | 58 ++++++++++++++++++++++++++++++++++++++ system/meson.build | 1 + 4 files changed, 62 insertions(+) create mode 100644 system/cpu-qom-helpers.c diff --git a/MAINTAINERS b/MAINTAINERS index ed98814398..af27490243 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -148,6 +148,7 @@ M: Richard Henderson R: Paolo Bonzini S: Maintained F: system/cpus.c +F: system/cpu-qom-helpers.c F: system/watchpoint.c F: cpu-common.c F: cpu-target.c diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index cf597c40a3..1874f18e67 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -27,6 +27,8 @@ typedef enum QemuArchBit { QEMU_ARCH_BIT_LAST =3D QEMU_ARCH_BIT_LOONGARCH } QemuArchBit; =20 +const char *cpu_typename_by_arch_bit(QemuArchBit arch_bit); + enum QemuArchMask { QEMU_ARCH_ALL =3D -1, QEMU_ARCH_ALPHA =3D (1 << QEMU_ARCH_BIT_ALPHA), diff --git a/system/cpu-qom-helpers.c b/system/cpu-qom-helpers.c new file mode 100644 index 0000000000..0d402ee3a0 --- /dev/null +++ b/system/cpu-qom-helpers.c @@ -0,0 +1,58 @@ +/* + * Helpers for CPU QOM types + * + * SPDX-FileCopyrightText: 2024 Linaro Ltd. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "sysemu/arch_init.h" + +#include "target/alpha/cpu-qom.h" +#include "target/arm/cpu-qom.h" +#include "target/avr/cpu-qom.h" +#include "target/cris/cpu-qom.h" +#include "target/hexagon/cpu-qom.h" +#include "target/hppa/cpu-qom.h" +#include "target/i386/cpu-qom.h" +#include "target/loongarch/cpu-qom.h" +#include "target/m68k/cpu-qom.h" +#include "target/microblaze/cpu-qom.h" +#include "target/mips/cpu-qom.h" +#include "target/nios2/cpu-qom.h" +#include "target/openrisc/cpu-qom.h" +#include "target/riscv/cpu-qom.h" +#include "target/rx/cpu-qom.h" +#include "target/s390x/cpu-qom.h" +#include "target/sparc/cpu-qom.h" +#include "target/sh4/cpu-qom.h" +#include "target/tricore/cpu-qom.h" +#include "target/xtensa/cpu-qom.h" + +const char *cpu_typename_by_arch_bit(QemuArchBit arch_bit) +{ + static const char *cpu_bit_to_typename[QEMU_ARCH_BIT_LAST + 1] =3D { + [QEMU_ARCH_BIT_ALPHA] =3D TYPE_ALPHA_CPU, + [QEMU_ARCH_BIT_ARM] =3D TYPE_ARM_CPU, + [QEMU_ARCH_BIT_CRIS] =3D TYPE_CRIS_CPU, + [QEMU_ARCH_BIT_I386] =3D TYPE_I386_CPU, + [QEMU_ARCH_BIT_M68K] =3D TYPE_M68K_CPU, + [QEMU_ARCH_BIT_MICROBLAZE] =3D TYPE_MICROBLAZE_CPU, + [QEMU_ARCH_BIT_MIPS] =3D TYPE_MIPS_CPU, + /* TODO: TYPE_PPC_CPU */ + [QEMU_ARCH_BIT_S390X] =3D TYPE_S390_CPU, + [QEMU_ARCH_BIT_SH4] =3D TYPE_SUPERH_CPU, + [QEMU_ARCH_BIT_SPARC] =3D TYPE_SPARC_CPU, + [QEMU_ARCH_BIT_XTENSA] =3D TYPE_XTENSA_CPU, + [QEMU_ARCH_BIT_OPENRISC] =3D TYPE_OPENRISC_CPU, + [QEMU_ARCH_BIT_TRICORE] =3D TYPE_TRICORE_CPU, + [QEMU_ARCH_BIT_NIOS2] =3D TYPE_NIOS2_CPU, + [QEMU_ARCH_BIT_HPPA] =3D TYPE_HPPA_CPU, + [QEMU_ARCH_BIT_RISCV] =3D TYPE_RISCV_CPU, + [QEMU_ARCH_BIT_RX] =3D TYPE_RX_CPU, + [QEMU_ARCH_BIT_AVR] =3D TYPE_AVR_CPU, + [QEMU_ARCH_BIT_HEXAGON] =3D TYPE_HEXAGON_CPU, + [QEMU_ARCH_BIT_LOONGARCH] =3D TYPE_LOONGARCH_CPU, + }; + return cpu_bit_to_typename[arch_bit]; +} diff --git a/system/meson.build b/system/meson.build index 25e2117250..c6ee97e3b2 100644 --- a/system/meson.build +++ b/system/meson.build @@ -10,6 +10,7 @@ system_ss.add(files( 'balloon.c', 'bootdevice.c', 'cpus.c', + 'cpu-qom-helpers.c', 'cpu-throttle.c', 'cpu-timers.c', 'datadir.c', --=20 2.41.0